Vias, Annular Rings on All Layers or Just Some Layers?

[TinyMirrors]

For vias, are the annular rings only for the layers which you would like to connect? If this is true, can I remove the annular ring for layers the via doesn't connect to gain extra clearance or move traces just a bit closer to the via?

For example, routing a signal from the top layer to layer 3, would layer 2 and the bottom layer need a ring as well? I have no idea what happens in the manufacturing of boards for this.

I'm trying to route a bga for the first time, and I've never thought about what annular rings on vias are actually for. If I leave them, I don't have room to route. It seems like Altium allows you to choose the annular ring size per layer.

I'm trying to route a 0.8mm xilinx fpga bga with 4mil traces and 0.2mm vias. I need a 6 mil annular ring by manufacture's spec for lower cost boards. If I use the advanced production the boards cost twice as much. 

Thanks for the help guys!

Here's the settings for a via in Altium.

[T3sl4co1l]

It's done automatically at output generation.

If you absolutely, positively need the extra clearance from removing copper on that layer, you can do this.

You shouldn't set the clearance (from unconnected copper to hole) less than 10 mils (0.25mm) or so, otherwise you run the risk of drill plus layer alignment errors causing shorts.  Your board fab will charge extra as a result.

Tim

[Psi]

For vias, are the annular rings only for the layers which you would like to connect? If this is true, can I remove the annular ring for layers the via doesn't connect to gain extra clearance or move traces just a bit closer to the via?

yep, that's normal for getting extra room to run tracks under a bga