I'm trying both the suggested pads in the datasheets and a bit larger ones on one dimension, similar to QFN. But one thing I did wrong before is have a 0% shrinkage in the stencil hole sizes, now I'm using 10%.
I asked Chatgpt and gave some interesting reply:
PC standards (e.g., IPC-7351 for SMD land patterns) provide a good starting point. These standards define three pad size categories based on density levels:
Nominal (Level B): Balanced for most applications, typically recommended for general-purpose self-centering.
Most (Level A): Larger pads for maximum solder joint strength, which can enhance self-centering but may sacrifice precision.
Least (Level C): Smaller pads for high-density designs, which may limit self-centering but improve placement accuracy.
For optical SMD components requiring high consistency, the Nominal (Level B) pad design is often a safe bet, with slight adjustments based on your specific component and process:
Pad Extension: Extend the pad ~0.2–0.3 mm beyond the component termination on each side (horizontal and vertical) to leverage surface tension effectively.
Toe/Heel/Side Fillets: Ensure the pad design accounts for proper solder fillet formation, which stabilizes the component during reflow.
Based on your goal of consistency in positioning:
Slightly larger pads (e.g., 0.1–0.3 mm longer/wider than the termination) are generally better for enhancing the self-centering effect during reflow. This allows the solder’s surface tension to dominate and pull the component into a repeatable position, assuming proper solder paste volume and stencil design.
However, avoid going too large—excessive pad size can introduce variability if solder pooling becomes uneven. Test your design with a few prototypes to confirm