Analog frontends for DMMs approaching 8.5 digits - Discussions

[Echo88]

Can you show us some photos of your prototype julian1?

[julian1]

Can you show us some photos of your prototype julian1?

Here is a pic of the current old board, which should give a sense of the layout/design.
The decoupling and digital control are mostly on the backside (not shown).

The license is open source gpl 3 or cc by-sa 4.
For any future revision I will add better creative attribution, and properly reference this eevblog thread as the source of community design ideas and discussion.

A note about the layout -
I couldn't decide what configuration I liked - a traditional-style DMM or datalogger, so it is kept open for extension.

The lhs ER digital/mcu section is enough to do stand-alone datalogging with usb-cdc for comms, SMA for ext-rigger/meas-complete, flash storage, and rtc for data time-stamping.
But this is optional, and the headers at the isolators, would support a UI control-panel board and features - buttons, lcd/vfd, buzzer etc.
A mcu/rasperry pi/beaglebone - anything with spi would also work if the code was ported.

[julian1]

A second input can make some sense. However for the 2nd input I see relatively little need for the extra MUX in front of the pre-charge circuit. There should already be plenty if input paths available.

Thanks, your comment prompted the realization that dcv-hi is common to all dcv/ohms AZ readings, as well as readings with a second hi (dcv-source, 4w-hi), so it makes sense to give it a dedicated pre-charge switch, and without the extra mux in front of it. the mux in front of the other pre-charge switch can handle other inputs.

In addition, removing this mux eliminates it as potential source of leakage, especially on the most critical input paths.
So it is a very good simplification.

I see a limited use for the divider between the 2 guard (buffer of the inputs) signals. The relay to link the the circuit star ground makes no sense as the amplifiers are from the same supply anyway and one would only load the amplifiers differently.

I need to go through the details, to properly understand how differential mode works.
It suspect there are enough moving parts already to test.

[Kleinstein]

The 2nd input allows to use some kind of differential mode, be measuring the difference between the 2 inputs. However under most conditions this does not come with an extended range. It depends on where the test circuit and meter circuit are connected with a more low impedance link.

To extend the input range one needs to shift the connection to have one signal positive and the other signal negative. The easiest way for this is to get back to the more normal case with only 2 links from the DUT to the meter and the low side shifted to the negative of the input instead of the classical fixed meter ground. Reading the low side does not need extra protection or precharge, as it is a low impedance signal driven from the meter side.

I see still 2 options for the driven low side.
1) Use the same COM terminal and switch between the driven low side (and the current input isolated) and classic COM=ground.
2) have the driven low side in addition to the COM and current terminals and than have additional protection (current limit to some 1 mA). This would allow to use the terminal also as a voltage output, e.g. for a reference voltage or high ohms test.

[julian1]

With less resources at hand for doing calibration like checks, there is justification to have an expanded set of self-tests to validate behavior.

For turnover tests - I expected to use a separate pcb board, having a true isolated voltage source, and relays to invert the voltage source to be applied to the dmm inputs.
But perhaps a simple on-board cap, switched by a DPDT relay could achieve the same thing.   
So the cap would first be connected to the gnd-referenced on-board dcv-source by the relay to get the reference voltage.
And then disconnected, and reconnected at the input - in both polarities for the readings.
My initial thought, is that a relay would be better than a mux/ltc1043, to completely avoid charge-injection offsets, during the connect/disconnect cycle, and because there is no demand for fast switching.
But depending on the cap size perhaps a mux would also work.


Similarly for quasi-INL adc tests - performed by sweeping the charge-voltage on a PP cap over the input range, while perturbing the adc runup parameters.
This was previously done with a separate pcb board - with relays and to mount the physically large (20uF) PP cap.
But perhaps the sweep could be managed with muxing on the 10nF accumulation cap (C410).
The previous leakage tests show that drift is probably low enough.
It just needs to be stable enough to take two consequitive adc measurements at each voltage point.

[julian1]

Scratch the idea using the 10nF accumulation cap as switched capacitor. I had units, uV and mV for leakage drift confused. But perhaps a board level 1uF PP cap might be physically manageable and could be added to the board.

Edit. actually 6.8uF PP is manageable.
for the turnover test, and to transfer the charge from dcv-source to the input, it might be necessary, to switch a few-times, to overcome the capacitance (protection, muxes) of the input section.

[Kleinstein]

For the INL test an external relay could be an option, but it could also help to have control over it, either directly or just a sync signal.

Instead of the simple turn over test, one could consider the more general sum of 2 voltages version. This needs 2 separate DT switches. 2 inputs could substitute 1 switch and 2 low side paths also the 2nd switch. Here especially the case with 1/2 the voltage is interesting as it is a bit easier too look at the result. As an additional advantage over the simple turn over test one also includes a check and compensation for the meters / switch offsets. The 2 extra readings allow a more accurate turn over test for the ADC than just a single relay for a polarity reversal.

The external part would need a low noise short time voltage reference for 2 connected voltages, ideally with several values to choose.
 A simple version could be a chain of batteries (e.g. 8 x 1.5 V) and connectors/switches to choose different points to connect. The external ref. part needs to be isolated and separately powered. So it could well be an external unit. To make the test work well it may need quite a few repeats (at least if the references are noisy) and automation can help with this and avoid thermal EMF from handling the cables.  A fixed speed also allows to compensate for drift better. With a low noise reference manual switching may still be an option for a first test. I don't see a need for very many test voltages and the choice of which voltage to use could still be manual.

Using a capacitor for the turn over test could be tricky and at least require a large capacitor, as parasitic capacitance can pump out some charge and effect the test. One may have to do the test with different capacitor sizes, e.g. 2 capacitors in parallel and options to disconnect on both ends (e.g. with jumpers). It may need quite some care and still the capacitance or manybe thermal EMF at the switches as a possible source of error.

For the slow drifting test voltage the 10 nF may be a bit on the small side. With 10 pA if leakage this would still be 1 mV per second or 3.6 V per hour.  For may tests I liked it usually a bit slower, more like 1 V per hour. Ideally one wants to look at the critical regions with even mode details / lower speed.  It may need a bit extra averaging and not just a single 1 PLC conversion to the the short range INL errors tested with this method. One is hoping for errors < 0.5 µV and this is about the RMS noise for a single 1 PLC conversion. So one should have more like 20-100 averages per point.

Another test that comes naturally is using the ACAL procedure with additional test voltages, like +1 V and -1 V for the 1 V range gain. Ideally the gain for the x10 gain step should be the same from both tests. The difference gives a hint on the liniearity of the ADC and gain stage combined. The extra test voltages make a relatively fast self test and via averaging also alow to average out some of the INL error to get a more accurate ACAL result for the gain steps.

[julian1]

A quick update,

One goal for a new board, is to change the copper features to improve the input switching parasitics, based on the previous experiments.
The design now features traditional ring guards wherever leakage needs to be controlled.
As well as a copper fill at BOOTIN potential, underneath the AZ mux, and surrounding the azmux node and amplifer jfets, to reduce capacitive loading.


Leakage
Input leakage can be tested by first charging 10n cap for 10sec, then turn off azmux and observe leakage by sampling boot.
leakage looks very controlled.

    > reset ; dcv-source 10; test05
        0.57mV 0.54mV

    > reset ; dcv-source 0; test05
        0.7mV 0.8mV

    > reset ; dcv-source -10; test05
        1.2mV 1.1mV.


Precharge switching,
Change injection is constant at different input bias voltages - as expected due to the switch bootstapping.
This can be improved/trimmed, by lowering the supply voltage on 4053, and trimming VEE relative to BOOT, with a bipolar current source.
But I haven't bothered for the moment.
Accumulated charge injection, nplc 1, on 10nF for 10s, using lv4053,

    > reset ; dcv-source 10; nplc 1; test14
      6mV. 6.4mV

    > reset ; dcv-source 0; nplc 1; test14
      7.2mV  7.2mV

    > reset ; dcv-source -10; nplc 1; test14
      7.8mV 7.6mV


Normal Az switching,
The copper fill at BOOTIN (copying the AZ input voltage), under the azmux works to suppress the capacitive loading of the switch-node output.

    > reset ; dcv-source 10; nplc 1; test15
      5.0mV 4.95mV

    > reset ; dcv-source 0; nplc 1; test15
      7.5mV 8.2mV

    > reset ; dcv-source -10; nplc 1; test15
      8.15mV.
 

Board has two distinct input channels, with separate pre-charge switches.
So four-cycle RM and AG (to compensate thermal walk of a high-gain amplifier) functions are possible,

ratio of ref-hi, 10nplc, sampled on two separate channels,
ratio, 3 of 4 meas 0.999,999,9 mean(10) 0.9999999V, stddev(10) 0.06uV,
ratio, 0 of 4 meas 0.999,999,9 mean(10) 0.9999999V, stddev(10) 0.06uV,
ratio, 1 of 4 meas 0.999,999,9 mean(10) 0.9999999V, stddev(10) 0.06uV,
ratio, 2 of 4 meas 1.000,000,1 mean(10) 0.9999999V, stddev(10) 0.07uV,
ratio, 3 of 4 meas 1.000,000,0 mean(10) 0.9999999V, stddev(10) 0.07uV,
ratio, 0 of 4 meas 1.000,000,0 mean(10) 0.9999999V, stddev(10) 0.07uV,

[julian1]

For sum-tests,
I spent quite some time trying to get an arrangement with two series 10u film caps to work.
This included a bunch of over-engineered muxing - for cap selection, and polarity, and to be able to charge to different spot voltages.
But I couldn't avoid a constant leakage of -2uV/s likely to the negative rail (probably due to 0.65" ssop dpdt mux package).
In the past I used relays, but that would be too cumbersome with multiple relays needed

To try the battery approach,
8x 1.2V enneloup batteries in a battery-holder with taps, switched manually
Method - is sample AB for 10 readings, 10nplc, then BC (bottom half) , then AC (series ), take the means, and calculate the diff/delta.
repeat 5 times.
eg. diff = 4.8V + 4.8V - 9.6V


After reducing resolution, change series rundown bias-resistor from 220R to 1k. and new cal.

> data cal show
Matrix: 3 by 1
row 0:     17.4986934
row 1:    -17.9358312
row 2:   -0.458200302
model_id    0
model_cols  3
stderr(V)   0.86uV  (nplc10)
res         0.115uV  digits      7.94 (nplc 10)

4.8
diff -3.50uV
diff -5.12uV
diff -4.66uV
diff -4.04uV
diff -1.76uV

2.4
diff -5.39uV
diff -4.11uV
diff -3.88uV
diff -0.94uV
diff -3.44uV

7.2
diff -5.95uV
diff -2.77uV
diff -3.09uV
diff -4.99uV
diff -2.00uV

3.6
diff -4.51uV
diff -6.62uV
diff -5.07uV
diff -4.34uV
diff -1.98uV


6.0
diff -8.43uV
diff -7.10uV
diff -3.93uV
diff -7.28uV
diff -2.49uV

6.0 repeat.
diff -8.09uV
diff -4.13uV
diff -3.95uV
diff -3.43uV
diff -4.59uV


1.2
diff -1.94uV
diff -2.22uV
diff 0.08uV
diff -2.07uV
diff -4.10uV

8.4
diff -3.94uV
diff -1.96uV
diff -2.35uV
diff -2.66uV
diff -2.43uV

I've only just got this working, and am not quite sure how to interpret the offset.
Probably it would be good to try the negative polarity, and I would like to experiment more with a two-variable weighting model for the adc reference currents.

The board includes footprints for 8, and 10pin mdacs, for creating +- spot voltage and these are working,
The idea here was to test inl in a sum-type ratio mode, through a polarity flip.
But I forgot to add a resistor divider, which would need to be bodged.
And I don't like the idea of lower-impedance source, as one cannot buffer the divider since the buffer Vos will not invert through the polarity mdac reference voltage flip.
The mdacs look to be reasonably low noise as far as I can tell - cannot see much above the reference noise.
So the mdacs may be better for drift like INL spot tests, where the adc runup parameters are perturbed.

[Kleinstein]

The input leakage and average current from charge injection looks really good. Also the input inpedance / conductance looks really good: some 2-3 pA of change in the input current when going from -10 V to 10 V would be an input resistance in the 10 Tohm range and this is even with 1 PLC mode. It is cool to have some kind of self test for the input leakage.


For the sum test it would also be good  to include a 4 th measurement (BB) for the offsets. The BB rading would be subtraced from the result.  This way one has the low side at A and B twice each and the high side at B and C twice each and int the resut each point once positive and once negative. This should give a quite good compensation of offsets (e.g. from the protection part).

For the sum of 2 voltages one needs the test voltages to be floating to have the ability to connect the center point to the low side (GND) for 2 of the readings. This makes is tricky to use the same reference nad DAC. One would need some charge pump floating capacitor system (like the 10 µF film caps) or similar system with current source and series of resistors. One than still has the problem that the error can be from the ADC or the charge-pump (or current source output resistance). With the capacitor the issues are leakage, switch charge injection and also parasitic capacitance that can pump out some charge.

The result from the sum test still show quite some scattering. Part of this may be from drift in the battery voltages. At least I see this as a weak point with batteries. The dift can give a systematic error and just simple averaging is not enough. One can compensate at least for the linear drift part, by interpolation to the same time from more readings in a row.
 
Depending of the voltage reference used (especially a LM399) there can also be an error from popcorn type jumps in the reference voltage. Here just averaging over enough reading could help.

With the scattering and possible error from drift of the battery voltages it is hard to say what the results mean.

[julian1]

Here's a sum-test plot in both polarities as baseline.
The measurement readings are interleaved somewhat to reduce the scattering.
BB is plotted as a control, but is not subtracted from the diff because the magnitude is too small to be consequential.
I thought I would try to deal with the simple case first - and the input test voltages are from a dedicated pin header into a mux, that bypasses protection.

There is a fairly distinctive shape, dependent on input voltage.
I still need to tidy/fix a few things - LC after the switch and before the integrator etc.
Ref currents are signal=50k, ref=40k,40k, so there's some opportunity for differential TC effects on the ref-current switch.
So probably a good test is to try and equalize to 50k,50k,50k or similar using jumpers.
I have a small test-pcb, with a floating/isolated mdac/divider, but it had a few issues, so the present focus is with batteries.

[Kleinstein]

The residual offset for the BB readings is small and as usual also relative constant. It may get larger and more temperature dependent if more protection is included and than the BB reading could correct most of the added error from the protection and switches.
The difference looks OK. The worst case is at some 3 µV or 0.3 ppm of the 10 V range.
For a smooth INL curve the difference is somewhat larger than the INL error, suggesting and INL error in the 0.2 ppm range.

From my last tests the differential TC part does not seem to be that bad, at least not with ORN resistors. At least it is a rather slow effect. So one can tell it apart from the slow response.
Changing to all 50 K would likely not help much with the INL, but it could help with the gain TC. From a crude estimate I would expect a slightly ( ~ 0.5 ppm/K) more positive gain TC when using all 50 K resistors. So the change is in the scattering range due to the resistor TC.

[julian1]

I was watching Fesz' youtube channel recently, where he demonstrates some interesting experiments looking at shielding techniques to suppress electrical and magnentic emi.
For electrical (versus magnetic) emi, the shield needs to be grounded to avoid coupling which can make the situation worse.



Furthermore, the experiments show a difference between a shielding plate that terminates to a single-point ground connection (7.54min), versus one that terminates along the full width of the edge (10.06min).
EMI suppression improves considerably for the "full ground connection all around" low-impedance gnd (at RF frequencies), versus the single point-connection.

The implication for pcb shielding cans, is that they should make an electrical connection along their edges to a pcb ground fill.
Or as a practical manufacturing compromise - make staggered connections along their edges.
One sees this kind of arrangement in sensitive RF designs.

Perhaps an interesting option here might be Harkin style clips, these are SMD components that can be soldered to the board.
They then grab and make electrical connection to the can.
The advantage, is that it is possible to quickly fit/remove the can, and without requiring a permanent soldered joint.

https://www.mouser.com/ProductDetail/Harwin/S1711-46R?qs=93uzuGORGqc8FyLhIh5ctw%3D%3D

Both 3458a, and k2002 have outside chassis enclosures, as well as a second inner shielding enclosure. For both top and bottom.
The 3458a has an additional (3rd plate) over the top of the adc.
It is hard to tell, but from watching teardown videos, it almost appears the k2002 black inner sheet-metal shield, may be floating/and not connected to chassis gnd.
So perhaps the shielding demands are not as high as supposed.

In terms of layout - it is possible to think of several options - one could have a shielding-can for the adc/refs, and another for the zero switch/muxing/amplifier.
Since the adc has some switching frequencies, a dedicated can/enclosure may make sense for emi egress.

Alternatively a single inner cover (like k2002) for all the analog parts of the pcb could be done, (eg. excluding digital/ hot regulators, and accessibility for fuses, input connections etc.) .

[Kleinstein]

Ideally one would have 3 layers of shielding, just like with the 3458.  The inner most is at the circuit-ground (ADC and amplifier). The next is connected to an external guard input or (via a switch) to the low side input. The outer shield is the case, e.g. connected to PE.  The guard part is normally considered mainly for the low frequency part (e.g. mains) - so here a single connection and not perfectly closed shield is OK. The switch between internal and external guard is already a single connecting point anyway.
Chances are the balck shild in the K2002 is more like the guard. It should be connected to something and not float. Otherwise it would only be for thermals. A shield will definitely also effect the thermal environment. The block color could be to get more radiative coupling.

Ideally at least one of the 3 layers would reject RF frequencies too. This would be difficult with the case. For the shield to be effective against RF all the wires / lines going in would need RF filtering. This is easy for mains / power and the data connection, but tricky with the measurement inputs. An inductor is easy, but one would not want capacitance to the case (e.g. PE) for the signal inputs.
A similar problem is with the guard, though a little capacitance could be OK. The guard part may not need to go to the PCB at all.
So the logical way would be to have the inner shield(s) RF tight.  Here I would ideally have it separate for the amplifier, ADC , the FPGA/µC and DCDC part. The linear voltage regulators may not need a shield. The inner shield should present only DC voltage towards the guard part. Otherwise AC voltage, e.g. from the DCDC converter part could couple to the guard. So there should be some inner shielding also at the DCDC converter part.

[julian1]

Thanks Kleinstein, that is extremely helpful.
The emi environment is much worse today, with all the switching supplies, than when the 3458a, k2002 were designed - so it makes sense to take care where feasible.

The guard part is normally considered mainly for the low frequency part (e.g. mains) - so here a single connection and not perfectly closed shield is OK. The switch between internal and external guard is already a single connecting point anyway.

To focus on just the Guard shield for a moment,

There is currently a provision for an external user-guard connection at the front/rear terminal gang-switch.
It is routed (with protection to PE) to the input power connector, for connection to the inner-shield of the power transformer (if available).
There is also the option to connect straight to internal star-ground.
The choice is currently static - and made with jumpers.

This guard net should be used for a guard potential shielding assembly over the pcb.

But I think a relay is needed to cover the cases to avoid leaving it floating -  Eg. a relay to switch between internal (eg. star-ground) or external user connection.
(I think I had a relay in a past schematic revision, mostly because I couldn't envision the measurement or validation scenarios where it might be useful).

[julian1]

Ideally at least one of the 3 layers would reject RF frequencies too. This would be difficult with the case. For the shield to be effective against RF all the wires / lines going in would need RF filtering. This is easy for mains / power and the data connection, but tricky with the measurement inputs. An inductor is easy, but one would not want capacitance to the case (e.g. PE) for the signal inputs.

Using an outer enclosure shield for RF appears to be the strategy of the 3458a. Eg. the signal input DCV gets filtering of 2x RC 5k/82p

Some things that might help reduce the parasitic capacitance to the outer enclosure could be -
- plastic housing for the input jacks/connectors. (issue of RF ingress, but maybe there is a compromise point)
- beads on input wiring.
- a shield sleeve around the inputs wires.

If pcb board cans were attempted for RF, then there is still the pcb gap between top and bottom can.  (although PTH copper slugs could help fill),
And there would appear to be many more inputs and outputs, depending on which circuits are chosen to be inside/outside the demarcation.

As a practical concern I suspect the ease/difficulty of sheet-steel manufacturability for custom cans versus full-enclosure is about the same.

[julian1]

Considering the approach of using sealed-cans at circuit ground potential for RF, I noticed that two-piece "frame and lid" style cans are available.

The advantage with the frame is that it can be soldered around the perimeter, but since the lid is detachable, one does not lose access to the board/components.
They would make a much better seal versus using retention clips.

The top and layer/bottom pcb layers could be flood filled, for the attachment pads.
And for soldering, perhaps mild-steel sheet can be pre-tinned with a hot iron.

What doesn't work though is the layout, since the TH filters for 4W, are some distance from the input muxing/amplifier.
Likewise the inductance/ optional capacitance for DCV input is placed with other TH protection parts / and HV pcb cutouts.
So these would be outside the cans.

But perhaps they would still be worthwhile as an additional measure.

[Kleinstein]

A few THT parts would not be that bad. The capacitor to ground would be grounded anyway. A few small solder joints on the outside are also not that effective an antenna to pic up much RF.
The bigger issue may be the clearance for high voltage at the very input. The protection part wants clearance and ideally also a thermal shield, which is a bit tricky combination.

The input protection may be OK outside. The MOSFETs, when turned on or off all the way should not be that susceptible to RF interference. The clamping part and fast turn off opto-coupler are howerver a bit tricky. This would add a few more lines going in /out of the cans.

[julian1]

I don't see a way to use RF cans around the HV section given clearance needs, or else forcing very large layout changes.
But maybe that is just the trade-off if a full Farraday like enclosure is not used.
Preserving the functional standalone module nature of the design, independent of enclosure choice would be nice.

I purchased some inexpensive electric and magnetic near-field probes and wide-band amp, for the scope in fft mode.
Not sure if they will help to draw conclusions about shielding strategies.
But it could be interesting to experiment, particularly for internal switching voltage and current sources - isolators, cmos xtal oscillator, adc, transformer.

[Kleinstein]

It is probably OK to have the protection part outside the cans. For the amplifier and ADC part a can could be nice. Here amplifiers may react to RF signals, though already the ground plane (even of at the back) can to quite a bit for shielding.  For me shielding is still a bit of RF magic, open to surprizes with things that may look good and still fail.

[dietert1]

Some days ago i had a look at the TI ADS125 delta-sigma ADC datasheet. In the recommended application schematic fig. 98 they already show four 47 Ohm damping resistors for the SPI lines. Nowadays that many MCUs chips produce sub-nanosecond risetime signals this may be a good thing to do in mixed signal designs. Also depends on the trace lengths.
Imagine EMI suppression as an attenuator made of a low impedance close to the receiver and a high impedance close to the emitter.

Regards, Dieter

[julian1]

I should add resistors for the the output of the isolators (it's a tradeoff with routing space). I think Imo made the same point.
They are modern low-voltage parts designed to switch as fast as possibe, since bandwidth is the usual criteria being looked for.

The nice points, are that one can choose either capacitve or magnetic parts.
And because they are fast, the adc counts are transferred quickly during pre-charge phase, or during a reset, when there is no measurement sampling.

I scanned the datasheets, but I am not sure if the internal data-encoding scheme means they are still switching/sending data continuosly across magnetic/isolation barrrier,
even if there are no changes to user-facing input/output state.

So I am a bit curious to find out if they are emi emitters.

[CurtisSeizert]

I apologize ahead of time for the long post. I am still getting caught up on this thread, but I have some observations on EMI mitigation strategies from my nanovoltmeter project that may be helpful. Because the power source is a battery, it was necessary to generate the primary rails fed to LDOs with two buck converters and a Cuk. These went in on a daughter board with an Orbel Lazerlok shield over most of the PCB.  The bottom of the daughter board sits about 8 mm above the plane of the top of the main board. The shields on the main board are Laird BMI-S-210 (for the input stage) and BMI-S-230 (for the ADC and associated signal conditioning block). Both of these shields have non-perforated covers, and that was important in this application to be able to use them to mitigate air movement around sensitive nodes. I have also used shields with perforated covers when the sizes don't work out otherwise and put tape over the holes, but that looks a little how ya doin' (as Dave would say). Both of the shields on the mainboards have identical shields on the bottom side because both sides of the main board are populated. Only one side of the SMPS board has components on it (except for the TH connector). The shields on the main board have vias on each land to ensure a low inductance connection to the ground net.

Regarding the shields themselves, the Orbel shields are definitely much higher quality and are cut from thicker sheet. With the Lazerlok shields, there could be issues because they make contact all the way around. You could in theory change the footprint to be able to route signals on the layer with the shield, but that is putting some trust in the solder mask integrity as an insulator. They also cost a lot more than the Laird shields - about 5x as much with both the frame and cover costing $10-15. The covers are also stiffer and take some work to pry off without flexing the board. Between the two Laird shields, the BMI-S-230 is nicer, and the lid is pretty easy to snap off, which is a helpful feature on prototypes.

The performance of the shields on the boards is quite good. I have used a sniffer probe made with five turns of magnet wire amplified 25x with two ADA4896 stages (about 30 MHz bandwidth) to get a qualititative feel for EMI around the board. I could not detect any peaks due to the SMPS in the spectra I took with the cover on the ADC portion (which required some bending to get the probe in). I determined which peaks were due to the SMPS by comparing spectra with the board powered with the SMPS with spectra where the board was powered by a bench supply. The probe was located above U34 in the middle of that shield. There is quite a bit of noise directly under the SMPS board (probe was close to C20 at the upper right corner of the ADC shield). I think this is due to pulsating ground current from the switching of the Buck converters, and some of this current was likely flowing on the bottom layer.

Mains hum is not completely suppressed in measurements, with the size of the peak being dependent on the measurement conditions. With an internal short (from one of the relays in the top left), the peak is about 20 nV/rtHz. For the front panel connector, I switched from Pomona low thermal EMF lugs to LEMO 0S circular connectors with a shielded twisted pair cable, and that helped both for reducing mains hum and low frequency noise, the latter likely from transient thermal EMFs. I had some issues with intermodulation products between the mains hum and the chopper switching frequency aliasing down to low frequency with a simple block averaging filter, but I haven't implemented the feature to synchronize with powerline cycles. I was able to fix this without synchronization by changing to a cascaded integrator comb filter, which only required another six lines of code and a few 64-bit accumulators.

I placed the op amp and current sink for the input differential pair composite amplifier outside the shield because they are the biggest power dissipators, and this doesn't seem to be too problematic. The inputs of the op amp are are fairly high impedance nodes (about 70k each), so they are susceptible to electrical field coupling, but the discrete stage of the composite amp operates at very high gain in this design and the impedance of the inputs is balanced, so it is not too big a deal. I do see some switching residue in the analog outputs of the input stage, mostly from the ~10kHz burst mode operation of one of the LT8608S switchers.

There is some EMI from the MCU, but those peaks are not visible under the shields. All the fast switching lines like the SPI busses and UART have 33R resistors and 50 ohm traces (based on guesses about the output impedance of the driver circuitry). The digital section is all 1V8 to reduce power consumption, reduce EMI, and avoid level shifters with the ADC IO. With the STM32U575 drivers, the edge rates are not particularly fast at this voltage even with the HSLV bit enabled. There is a clear difference in rise time between the AD4030/AUC glue logic outputs and the MCU outputs on a 100 MHz scope, with the former being faster. There a number of signals to mod/demod switches that operate regularly during conversion with 100R resistors and thinner (but not 100 Ohm) traces. I don't see these as big EMI risks because they all switch during dead times in the conversion, which is presumably the case for all the designs in this thread with similar switches for autozeroing.

For the stackup, I used a 6-layer 1.2 mm board with the JLC2116 stackup. This was a compromise between keeping layers close together for low susceptibility to EMI and keeping them far enough apart to minimize parasitic capacitance on some feedback traces. Top and bottom were signal with some ground pours for thermal reasons, and layer 3 (In2) was power. All the others were ground. The 1.2 mm stackup keeps layers 3 and 4 relatively close (about 0.22 mm). I used 1 oz copper on all the inner layers to reduce the impact of any uncompensated ground currents.

Overall, this works pretty well. I do see some issues that seem to be from thermal gradients across the relays, but these are single digit nV effects at their worst and subnanovolt effects when conditions are well controlled. I would probably use a similar strategy for EMI mitigation if I were pursuing an 8.5 digit design with the inclusion of a guard shield between the case and the board (as Kleinstein suggested). I did not have room to include that and still fit everything (including 4x21700 batteries) in a Hammond 100x160 mm extruded Al case for my design, but I have considered the idea of changing cases if I were going to make a revision. I would also be using a lot of antialiasing filtering, something like a six or eight order Bessel filter with fc of about 0.1x the Nyquist limit with an AD4030. I think that a strategy like this (or using an integrating ADC of some description) would help with EMI-related woes because the cross-section of the circuit where it could prove problematic is much smaller. Oh, and one weird effect I noticed was despite powering the circuit with batteries, I needed a CM choke on the input to avoid odd behavior when connected to various sources, including a change in the offset voltage when the inputs are shorted internally. The case for my design is tied to PE through the USB shield during normal operation, so it is possible that an inner guard shield would mitigate such an effect.

I have a couple other general comments about things I saw elsewhere in this discussion. I agree with Kleinstein on the point of multiple parallel or series buried Zener references at this stage in the design cycle. It seems wasteful. For expensive components, I would prioritize good gain setting resistors because those will be crucial for achieving good linearity unless one is implementing some sort of continuous gain calibration faster than the thermal TC of the gain setting resistors or another way of dealing with power coefficient nonlinearity effects. I saw a reference earlier earlier to a substantial noise voltage using the JFE2140 JFET pair at the input. I have used a lot of these, and from what I can tell they have (probably) the lowest 1/f noise corner of any discrete JFET. I have attached a spectrum I took and a schematic showing the measurement conditions. The -3dB bandwidth was 13 mHz to 10 Hz. RMS noise for the DUT (uncorrected) from 0.1-10 Hz was 7.62 nVRMS with a capture of 4M samples at 200 SPS. The noise for each individual FET would be a factor of sqrt(2) less. I have a spectrum somewhere with the -3dB down to 10 mHz, and I think the NSD was about 25 nV/rtHz at the low end there. I spent some time investigating this, and the datasheet measurement setup for capturing noise spectra is pretty bad for low frequencies as the current noise of the OPA210 makes the 1/f corner appear higher than it should. I believe the gain also rolls off before 100 mHz in the datasheet setup. I have taken long captures of three parts for the JFE2140 like this, and there was almost no detectable scatter between parts. The LNA used to take this measurement actually uses 16 of them in parallel and gives a consistent SNR down to below 100 mHz, where input AC coupling filter noise noise (and some other sources) start to come into play. The SNR is near the theoretical 12 dB, so the parts I measured don't appear to be standouts. Another nice thing about this part is the gate leakage current is quite low. I use a Vds of 1.4V for my LNA with 400 uA drain current per FET and get a total of 2.7 pA, so <200 fA per FET.

I realize a lot of this information is anecdotal and qualitative, but I hope it can be helpful nonetheless.

[julian1]

Hi Curtis, thank you very much for your detailed comments.

I wanted to ask, if you use COTS or custom RF cans and how you route the land vias, in the nanovolt thread, but didn't want to pollute the discussion with mundane detail.

In your research - did you find any makers of (fence and lid style) RF shields who can manage custom dimensions, in prototype quantities?
I should search on the manufacturers you list - Orbel, Lazerlok, Laird  to see if they offer custom services.

To improvise - I did a Freecad step/dxf model for 0.8mm mild-steel sheet, and had it fabricated to try to prove the concept.
This approach should be OK for the larger LF magnetic (and thermal) guard cover, but is the wrong thickness for a rf-can.
I found a source of pre-tinned (for solderability) mild-steel in 0.2mm and 0.3mm thickness, but need to find a (local) service who can cut and fold the thinner metal.
Being able to pop the lid for access is probably needed as you note.
At this point, there's a trade-off between money spent on custom fabrication, versus extra time routing the pcb to accomodate fixed dimensioned parts.
The simultaneous aspect of mechanical design is a challenge.

The performance of the shields on the boards is quite good. I have used a sniffer probe made with five turns of magnet wire amplified 25x with two ADA4896 stages (about 30 MHz bandwidth) to get a qualititative feel for EMI around the board.

Using EMI sniffer probes and then doing experiments, switching between a bench supply and DC/DC converter is a really good idea.
Perhaps small electric and/or magnetic probes could be made a permanent (pcb) feature, that remain under the RF cans?
So the probes would route and present to a DUT connection header outside of the shield can.
I purchased a set of near field probes to try to get a bit familiar with doing EMI tests, but there's no way to use them with the cans fitted.

For the stackup, I used a 6-layer 1.2 mm board with the JLC2116 stackup.

Are there advantages in using JLC2116 versus other stackups, or even a basic manufacturing stack-up?
It seems like a good thing, if everything is well defined from a manufacturing pov.
Perhaps routing the fast digital signals (spi, adc control) with controlled impedance might reduce radiated emi, even if there are no timing/reflection needs.
For the dmm board, there are inner and outer layer grounds to shield (capacitive, magnetic) mostly orthogonal traces.

For the amplifier there are soic-8 footprints for jfe2140, and lsk389.
There is also a footprint for if3602.
I noted your comments about the thermal wander of the if3602 from the DIY cascode jfet lna thread,
So there is a 4-cycle sample acquisition sequence, that can measure and compensate the amp gain, against a small reference-voltage.
But use of if3602 is more in view as an alternative configuration like HP 34420a, rather than a general DMM and is not a priority.
Following Kleinstein's suggestion, I did some Allan variance noise tests with the jfe2140, posted in this thread, but still need to do it for the other parts.

I don't remember the numbers, but in a separate LNA project that I modeled a lot after your initial discrete jfet LNA design, I found lsk389 to be lower noise than jfe2140, but higher leakage (to be expected).
But shielding really needs to be improved first to gain confidence.


For supplies - at least for a first pass - I want to see if the design can be managed without dc/dc converters - and AZ ops for that matter.

I believe Shahriar Shahramian uncovered issues with the DMM7510 - even with the super low-coupling transformer used in that design.
I suspect fast voltage transitions on the rectifiers are a problem.
Adding LC filtering after rectification re-introduces coupling capacitance on the inductors.
So power supply issues are pushed-out as separate scope.
As fallback, I have a simple open-loop fixed-freq. push-pull, and resonant llc with zcs to test on a board, but they are a bit basic.

So for a power supply at the moment - the board can run with a scavenged 34401a mains-transformer (power input headers are designed to match).
Although this transformer is inadequate - with higher than expected coupling-capacitance and lack of a proper screen guard.
I did an experiment stuffing a small sheet of copper, between the two bobbins of Bel signal transformer, as a makeshift guard.
And this already works to reduces coupling (3x reduction from memory) better than the 34401a transformer, so it may something to explore.

If EMI can be measured qualitatively following your approach - with some sniffer probes. then trying out different supplies should be more of an option.