7.5digit diy voltmeter?

[Andreas]

while i wouldnt worry about the common-mode-voltage since my input voltage is floating?

I fear it is not that easy.
the common mode range demands that the input voltages are forced between -0.3 V and VCC +0.3V
So there are no "floating" input voltages. (except if you isolate the whole ADC + supply).

Negative input voltage means: the positive input is more negative than the negative input. But both within 0 and VCC.

The datasheet picture on page 6 is valid if you tie the negative input to VREF/2.

with best regards

Andreas

[Echo88]

I plan to isolate the ADC supplywise and communicate via optocoupler, so the input voltage truly floats for voltages less than +-Uref. But i think if i were to amplify small floating voltages i would need to use a fully differential amp with Uref/2 as the common-voltage, so the common-mode-voltage does not change if i vary the small input-voltage and therefore my INL stays repeatably the same? Is that correct?
I know of the behaviour "Negative input voltage means: the positive input is more negative than the negative input. But both within 0 and VCC." from my LTC2508-32-Evalboard which confused me when i tested it a year ago.

[Andreas]

But i think if i were to amplify small floating voltages i would need to use a fully differential amp with Uref/2 as the common-voltage, so the common-mode-voltage does not change if i vary the small input-voltage and therefore my INL stays repeatably the same? Is that correct?

Yes in my opinion.

with best regards

Andreas

[Navarro]

I always had this question on my mind.

In this case, we're talking about the AD7172-2. If we have 4 AD sections with AD7172-2 in parallel reading the same voltage on the same VREF, can we get more digits/precision/stability out of this by doing the average of both four ADCs?

[Kleinstein]

The precision ADCs usually are only one ADC. Some like the AD7172-2 have an integrated multiplexer, so that they can choose between inputs, but one at a time. Internally they may actually have some thing like 2 ADCs to make it a differential input, but this is already included in the specs.

There are audio and metering ADCs with 2 or even 3 ADCs inside, but these are usually not accurate for a DC measurement, maybe for AC.

In principle multiple ADCs in parallel could be used to reduce the noise - it is the usual square root N factor (at best, if there is no common noise part). So 2 ADCs in parallel might be feasible, but hardly more. However identical DCs in parallel would not help much with INL.
The effect on stability is also very small as chances are high the ADCs would drift in a similar way.

There might be a use for 2/3 ADCs - not directly in parallel, but in a kind of interleaving mode so that one is measuring the input and the other zero or a reference. Here the advantage would be having less noise, not only from the ADC itself, but also from the signal source as the input measured all the time, with no breaks for the zero adjust.  A similar effect is possible with a single differential ADC and switching polarity instead of switching between zero and signal.

[David Hess]

In principle multiple ADCs in parallel could be used to reduce the noise - it is the usual square root N factor (at best, if there is no common noise part).

Unfortunately the reference noise is common mode.  But one could use more references in parallel ...

[niner_007]

I think you meant AD7172?

http://www.analog.com/media/en/technical-documentation/data-sheets/AD7172-2.pdf

24 noise free bits at 5 SPS

In theory it can reliable produce 16777216 counts or 7,5 digits, accuracy and linearity at that level are a entirely different thing.

Edit: Scullcom hobby's on youtube did a similar project, was going to link it here but youtube ain't co-operating. 

A 7.5 digits DMM does not imply 0.1ppm accuracy, and it is still useful if it doesn't, I know of no 7.5 DMM that has that accuracy, not even 8.5 DMMs do (1 year accuracy, heck even 24hrs is much worse)! For a 7.5 digits DMM, typical (1y) accuracy is around 10ppm, Agilent's new 34470A has an ADC with 0.5ppm linearity, but the accuracy is something like 16ppm, Keithley's DMM7510 has an ADC with 1ppm linearity, but the accuracy is 14ppm.

[Kleinstein]

The really good SD ADC chips can have noise levels good enough for a 7 digit DMM. However the linearity tends to be a little on the poor side, so more like what one expects from a 6 digit meter.  There is no need to get the INL to the 0.1 ppm level for a 7 digit meter, but reaching the 1 ppm level is about what is expected.

Accuracy is a 3rd possible issue - this is often more due to the reference and calibration stability. The ADC chips usually need a reference of some 2.5-5 V, while the LTZ1000 and LM399 references are 7 V.  Getting a really stable 2.5-5 V reference is another difficulty that can effect the accuracy / long term stability. The input voltage range is also more in the 2.5 - 5 V range, which may be inconvenient  as it does not allow to directly measure a high stability 7 V reference.

[iMo]

Inspired by TiN's ADS1262/63  (sigma delta) test I acquired a few chips. They claim 3ppm INL, however.

Then I acquired the TLC2500-32 chips (SAR), they claim +/-0.5ppm INL.

Still not decided with which one to start, however.

In meantime I posted an AFE simulation (+/-20V, >>100Meg input) which may fit 7digits after applying some math.

Is there any practical experience with such an ADC design?

Are there any better chips available?

[alex-sh]

Is there any practical experience with such an ADC design?

Yes, say, building a millivolt meter. Or milliohm meter etc

[Echo88]

Regarding LTC2500, please read the two posts by MisterDiodes: https://www.eevblog.com/forum/metrology/32-bit-adc-playground-for-precision-measurement-tasks/msg1237921/#msg1237921
Personally i really like the LTC2442, with its integrated buffer and MUX. The MUX is a necessary to enable Full Scale/Offset/Long Term-Reference (LTZ1000/LTC1043-divider for 4.8V)-Switching, while the ADC is supplied with a low noise Reference (LTC6655 or chinese low noise diode). Same concept as in the Keithley 2010/2001 for example.

[Luky_13]

Called AD to check if LT2500-32 can be used for absolute DC measurement and they said 'absolutely'. Sending a detailed email to them to confirm again. A project hangs in balance based on the choice of ADC I make. Need to be doubly sure if I can use 2500 for absolute DC application.

[Edwin G. Pettis]

A small word of caution here, the AD boys are not that familiar with LT chips (ask me how I know) and a fair number of the senior LT engineers retired after the merger unfortunately so the knowledge base has become a bit thinner on some of the sophisticated LT chips.  The LTC2500 might work in your app but I would definitely test/prototype it first before committing to a design and I would heed MisterDiode's advice before taking AD's opinion on this subject.

[Kleinstein]

The ready made ADC chips usually have a smaller full scale range, like +-2.5 V compared to the usual about +-10 to +-15 V for most multi chip multi-slope ADC solutions and modern good DMMs. This requires a different kind of circuit and reference. Often this means that the solutions would have different ranges and especially different native ranges where they work best.

One would anyway need to build a prototype first, to see the actual performance and find those little traps for young players. In the ppm range even small effects (e.g. ground return currents and thermal effects) can be annoying. So chances are the performance not only depends on the chip, but also on the board / layout and other parts used (e.g. reference, buffer, amplifier).

[iMo]

..So chances are the performance not only depends on the chip, but also on the board / layout and other parts used (e.g. reference, buffer, amplifier).

As a preparation to an LTC2500 exercise I've posted at least a  simulation of an AFE for a simple +/-20V capable input. Except a low noise high stability 5V Vref, low noise low drift precision opamp, perfect pcb routing, various floating voltage sources you have to get extremely low tempco 1/10 divider as an example. Based on my current understanding the 95% of the problems with even a simple +/-20V voltmeter is with components outside the LT2500.
When you read datasheets of various LTs SAR ADCs you might see the LTC2500-32 INL is the same as the INL of the LTC2380 (their best 24bit SAR). Also the other params are similar. It seems to me the 2500 is basically their standard 24bit SAR core with some DSP over it such they get 32bit as the result.

[julian1]

 Looking at the Keithley adcs (5.5 digit, and 2002) designs, they use discrete logic, 74hct02 (nor) with 175 (flipflop) to control the sd5400cy and other fet switches. It's unclear to me why in the design this logic was not just pushed into the Altera cpld.

One reason is that fast discrete logic might have a speed/ or resolution/ or jitter advantage. Datasheets for 74hct state around 10ns propagation. But the altera epm7160 cpld - in spite of its vintage does 100MHz. It's also 5V compliant for gate drive voltage/ same as the 74 stuff. 

The sd5400cy has a propagation time of 600ps, but presumably depends how fast one can charge/discharge the fet gate capacitance. So using 74 series as a buffer (20mA) makes sense, but not the other stuff.
 
Also, it's a clever revelation to convert the reference voltages for the integrator to current sources - so that RDS(on) flatness of the switches do not contribute bias.

But at least for reference positive and negative voltages RDS(on) should be constant for fixed VDS. Unless maybe it's to void TC effects on RDS(on).   

[David Hess]

Looking at the Keithley adcs (5.5 digit, and 2002) designs, they use discrete logic, 74hct02 (nor) with 175 (flipflop) to control the sd5400cy and other fet switches. It's unclear to me why in the design this logic was not just pushed into the Altera cpld.

One reason is that fast discrete logic might have a speed/ or resolution/ or jitter advantage. Datasheets for 74hct state around 10ns propagation. But the altera epm7160 cpld - in spite of its vintage does 100MHz. It's also 5V compliant for gate drive voltage/ same as the 74 stuff.

It is not the speed but being able to have stable ground and supply voltages because in singled ended CMOS logic, the switching threshold voltages are referenced to both.  Ground and Vcc bounce inside the CPLD, or any programmable logic, places limits on jitter performance unless special steps are taken like differential switching.

The sd5400cy has a propagation time of 600ps, but presumably depends how fast one can charge/discharge the fet gate capacitance. So using 74 series as a buffer (20mA) makes sense, but not the other stuff.

That is another reason to use discrete logic; it allows return currents to be directed exactly where the designer wants.

[julian1]

Edit. Thinking out loud, about jitter a bit more.

The cpld needs to know the count to know how much corrective current it has pushed into the integrator during runup. So at a transition from +ve to -ve reference current - it could set up the transition on the data pin of the latch. And then the main clock would clock in the actual transition. Thus the design takes advantage of cpld/mcu logic, but with the the better aligned clock boundary/edge provided by the discrete series logic.

[Kleinstein]

The HCT02 are also used because of there limited speed to create a short defined dead time. With the switch part there is also the point of keeping a setup that works, even if it is not the most cost efficient. There can be nasty hidden surprises - so better keep a working system. It is not so much about very fast switching, but about a stable timing and delay.  In the HP34401 they add a ferrite to the HC4053 negative supply pin - possibly to slow down the switching and avoid the very high frequencies with very steep transitions.  So better avoid the GHz frequency range if you can.

At least for the 5-7 digit range the jitter is not that critical. One starts to worry about jitter at 8 digts if the switches are operated really frequent like in the 3458 (some 330 kHz modulation). The Keithley meters use a relatively slow modulation (AFAIR some 50 kHz) and thus slightly less sensitive to jitter.
Inside the CPLD there can be interactions with the timing, e.g. from internal ground bounce and loading internal clocks. I don't know from a CPLD, but I have seen a similar effect in a µC: the ADC and UART clock modulate the timing on GPIO pins, though only at a low level (<< 1 ns). So the internal state and other processes can have side effects.

[dietert1]

With modern programmable logic the signal chain of a GPIO involves 10 gates or more behind the last clock-synchronous register, plus some MUX or 3-state logic. You just count the programmable options like pull-up, pull-down, 3-state, inversion, drive strength.. Of course an external synchronizer works much better. Still you need a clean clock signal, so better use an external oscillator instead of the on-chip circuit of the MCU.
From my own experience i can only recommend to start building something simple like a PWM-DAC and try to get the precision. Then you can study in detail the technology of precision time division. The LM399 thread with its lengthy discussion of precision PWM is a good start. That's the path i am taking myself. Hope to use the precision PWM DAC  as calibrator for linearity tests and also for a differential voltmeter. Want to combine the DAC with one of those high resolution ADCs like the ADS1256.

Regards, Dieter

[julian1]

Thank you all for the comments. I notice the 74xx175 already has complementary outputs. So it makes sense for the 74xx02 to implement a break-before-make type sequence, rather than adding additional control logic.

Thinking about it more, and at least for a cpld/fpga (but maybe not for a mcu gpio) I can imagine that the entire LUT/macrocell logic propagation delay is exposed directly at the cpld/fpga gpio outputs. (cpld/fpga designs are not strictly even dependent on a clk). So it makes sense to use the discrete series flipflop/latch to manage the output synchronization if using these control devices.

For circuit/logic simplifications -

For a multislope design, I suspect the switch to short the integrator cap is unnecessary.  One can just use the low current +-ve references to steer the integrator to a 0 cross, when the signal current would then be introduced to begin integration. Certainly not as fast to reset, but a lot less complexity around the sensitive integration loop.

Keeping the slow slope / low reference currents present at all times, also seems like a good simplification. I believe both K2002 and Kleinstein designs follow this approach.  A 100:1 ratio - say 1mA and 10uA would seem like a good starting point.

If one did want switchable slope currents (instead of an always present low-current +/- reference), there is the possibility to pause the integrator midway (switch all inputs off) for the duration of current changeover.

This would permit doing more complicated things - such as switch the fb of an op based current source , while allowing time for the op to settle. But I think this might be too much (control and circuit) complexity.

On the other hand using an op based current source/ instead of voltage-to-current resistors, is such an interesting idea - with its advantages in voiding RDS(on) switch bias. Perhaps even when all switches are lo-side/low voltage / using double-throw to divert current to agnd when off (34401/74hc4053 approaches).

[Kleinstein]

For a multi-slope ADC it is not absolutely needed to have a discharge switch, though this is the classical way. Start from a defined state and measure till back.  The assumption (and for a simple design this is usually true) is that the reset is more accurate than one can get the discharge from the reference slopes.

Directly assuming the cap was perfectly at zero at the end of the last conversions is only approximate. AFAIR the old LD120 chip set did this, though with only 4.5 digit resolution.

Using more complicated switch sequences in the run-up is not directly related to have a fixed small current always present. The small current does not effect the run-up much. It many adds a small offset.

Using constant current sources (like in the Keithley2002) instead of just resistors for the references is possible and it has a few pros and cons. On the positive side the voltage noise of the OP at the integrator gets less important, though there is additional current noise from the OP in the current sources. The main positive point and use in the K2002 is that the ground level for the input and reference are no longer linked. One could get a kind of limited differential input. The switch resistance is no longer important for the reference channels, so smaller switches could be used. However on the downside this also means the switch resistances could no longe be used for a simple compensation for the switch resistance in the input channel. So the switch in the input channel should than be very low resistance (or even with compensation).
Current sources are also quite some effort - not just more OPs, but also more precision resistors.

In my design I don't have the small slope always on.  The small slope is from the sum of the + and - references and can thus be turned off. This is used for a hold mode, so the slow µC internal ADC can measure the integrator voltage and no reset is needed or present. In my case this works better (lower noise) than most reset circuits.

For a simple circuit the 4053 type switches like in the 34401 (or fluke 8846) are a good option. The newer Ti 74LV4053 has lower R_on and works quite well.  Having 3 switches is convenient for the input and 2 main references to get a TC compensation.

[DeltaSigmaD]

Is it necessary to use a multiple slope technique to obtain more than 6 digits? I don't think so.

Just before the LTC2400 was anounced the first time (1997), I developed a Delta-Sigma ADC with >25 bits resolution (not accuracy), which was improved since that time. This production ADC has about 0.1ppm rms noise of full scale with 5/s rate and 1s settling time to <1ppm (reference noise eliminated by ratiometric m.). The current status is that you can achieve easily 25 ppm linearity with a single Delta-Sigma converter stage - this might sound disappointing. But the long term stability is within a few ppm of full scale, i.e. also the residual non-linearity is very stable and can be compensated. It was not necessary to compete with a HP3458A, and therefore this design was not driven to utmost precision. I'm sure, the Delta-Sigma technique has the ability to even higher precision.

A high precision Delta-Sigma ADC must rely on a precisely predictable current-time area nearly independent on the duty cycle and/or frequency (according to my experience). The weak point of CMOS switches are not the DC resistance (can be compensated), but the timing of switch transition. There are current tails in 50ppm range after switching with about microseconds relaxation time (no, this is not the simple RC effect of switch). Any dangling electronic part destroys precision, therefore double throw switches must be used. Now, the timing of the break-before-make action of the switch is the dominating limit for high precision. A further critical point is the current integrator, which must have a high bandwidth combined with low noise. If the bandwidth-gain product of the integrator OP is too low, you will get input spikes with a high voltage-time area, and f.i. voltage-dependent capacitances of any semiconductors can induce non-linearity. Only composite amplifiers can achieve the requirements. Up-to-date DVM designs frequently use power-hungry FGAs which generate high temperature gradients inside the case. The heat management is complicated, a fan is necessary. Hence, the Delta-Sigma engine should run on a microcontroller (~15mW), even 250 kHz DS update rate is possible without problems yielding 1000/s rate. The microcontroller can compensate the non-linearity in real-time.

It would be a very interesting project to try what accuracy can be obtained today. Are there some more people which are interested on such ADC? Please inform me.

[Andreas]

This production ADC has about 0.1ppm rms noise of full scale with 5/s rate and 1s settling time to <1ppm

Hello,

not bad for a sigma delta ADC.
What is full scale on this ADC?
Bipolar or unipolar?

I tried it the other way round using the LTC2400 together with a 5V reference.
But since the ADC has rather high noise (perhaps due to low power consumption) I need integration times of 1 minute to reach 1uVpp/5V noise.
INL can be easily calibrated out due to parabolic shape to within < 1 ppm.
And T.C. (of the voltage reference) can also be compensated to < 1 ppm.
Since the LTC2400 has self calibration of offset and full scale it is very stable over time and temperature after pre-ageing of the reference.
Together with a simple LTC1043 2:1 divider you get a 0 - 10V measurement system.

with best regards

Andreas

[DeltaSigmaD]

This ADC has an input range of +0.5V to -8V in order to avoid voltage range translation (--> resistor drift). The switches were f.i. MAX319, which is rather slow. The fastest ADC with this range, 1000/s, and up to 160 dB free dynamic range at 0 to 500 Hz applied the HC4053.

It is impressive what can be obtained with the LTC2400. The LTC2400 is a really good ADC, but also has weak points. The switched capacitor technique used here causes current spikes at the input, which can be cumbersome. For instance, I was not able to achieve the datasheet linearity with LTC2440 for 1000/s rate. The latter IC is very sensitive to the input capacitor arrangement, and filtering its supply and reference is complicated. X7R capacitors can cause non-linearity, but you need e.g. 1uF. Is there a good solution for this problem?

The DS-ADC ICs have one fundamental disadvantage: the offset is adjusted to zero as part of the switched capacitor technique. But in this case the correlation between succeeding measurement values is destroyed (kT/C noise). Each measurement is statistically independent from other measurements. If you use a sliding average filter, you get a reduction of noise proportional to 1/sqrt(N).

In contrast, a continuous time Delta-Sigma ADC, as mentioned above, maintains the correlation of succeeding measurements. Simply speaking, if one measurement value was too low, the next one will be too large to compensate this. With a sliding average filter you get a noise reduction proportional to 1/N. This is valid until the inherent 1/f-noise (and drift) destroys this correlation (in my case at about 20s averaging). For ratiometric measurements I measured once <0.03ppm rms noise, which value could be reduced even more today. Continuous time Delta-Sigma ADCs can be constructed so that they have very clean dynamic characteristics. The offset correction has be to established by a circuit or techniques independent on the basic Delta-Sigma activity.

Considering this, it can make sense to develop continuous time DS-ADCs even today. This is the reason why I ponder to start a new development using modern electronics, while there will be no commercial use of it.