7.5digit diy voltmeter?

[Andreas]

Is there a good solution for this problem?

Hello,

I can tell only for the LTC2400.
The reference (AD586/LT1236) is buffered by 10uF Ta + 100nF X7R.
(of course you need a reference which can handle those capacitive loads otherwise you will need a low pass filter)

The input is more critical since the spikes can heavily influence previous buffer Op-Amps creating offsets of up to -30uV.
Here I use a low pass filter with ~820 pF + 825R after the buffer OP-Amp which is a good compromise between influence on INL of the LTC2400 and the previous OP-Amp.

with best regards

Andreas

[Kleinstein]

A discrete build continuous time SD ADC is rather similar from the hardware to a multi-slope ADC.
I think one can consider the multi-slope3 ADC of the 34401 also as a kind of continuous time SD ADC.
HP calls the ADC in there newer 3446xx meters sometimes multi-slope4 and sometimes sigma-delta.

When needing an external auto zero cycle the settling time gets important. Here the classical multi-slope is usually quite good and the time needed for the rundown can also be used for settling of the input after switching. The SD needs to wait a comparable time for the ADC to settle - sometimes this is even longer.

[RandallMcRee]

. . .

Considering this, it can make sense to develop continuous time DS-ADCs even today. This is the reason why I ponder to start a new development using modern electronics, while there will be no commercial use of it.

Yes, I think it would be quite interesting to create an open source ADC of high performance. Let me know if I could be of any help? It would be a learning experience for me. I could, for example, help on creating and measuring a prototype for a circuit that you propose. Verifying characteristics like INL, DNL, etc would be a challenge, however. How have you done that in the past?

Randall

[Castorp]

We also have a CT 3rd order Sigma-Delta built of discrete parts. The development started in the 90s, there's a conference paper from '99 that describes it.
https://digital-library.theiet.org/content/conferences/10.1049/cp_19990460
It was recently improved. Unfortunately I can't release the schematics, but I can explain a few things if there's interest.

The switches are implemented in a rather unorthodox way, using LVC-family logic. It's all controlled by a super simple FSM that fits inside a small CPLD. In the end, the ADC has LF noise in the 0.02 ppm ballpark (defined by the LTZ1000 Vref), white noise is flat up to about 300 Hz where it intersects with the +60 dB/dec quantization noise slope of the 3rd order modulator. INL varies from unit to unit but it's always sub-ppm, and in some units it's down to 0.3 ppm (without corrections or anything). TC is under 0.2 ppm/K thanks to active temperature control Idle tones have always been present, but in the new improved version they are much lower thanks to a different dithering scheme.

It's been a highly educational experience to work on it. On the other hand, nowadays you can squeeze better performance out of an integrated SD ADC.

Edit: I realized the paper is behind a paywall, so I'm attaching a copy. It reports on an early version, it was improved after that and the devices were eventually installed in LHC before 2008. And then the new revision with 5-fold improvement in LF noise was more or less ready in 2019. It will be used for a partial upgrade of some dipole circuits, but not for all of them.

[branadic]

I followed the news and work public available on the ADC. Just to get it right, the 22 bit converter was used before 2008. What exactly was improved on it? Noise?
The new revision from 2019 with 5-fold improved LF noise means the AD7177 based HPM7177?

-branadic-

[Castorp]

So, the "22-bit" is what we call DS22. It's in use in LHC and will remain in use. The improved version is what we call DS24. It's backward-compatible with DS22 - same form factor, same output (raw bitstream with simple encoding). Some of the DS22s will get replaced with DS24, and this partial upgrade involves also one board within the DCCT. The ADC improvements are in the LF noise and idle tones (15-20 dB lower in DS24). The low-frequency noise determines the short-term stability (20 minutes) which is particularly important, but also the 12-hour stability is improved.

HPM7177 is a totally different and new development, and will be used only for some new converters in HL-LHC, particularly the 18 kA inner triplets, 14 kA short dipoles, and also some 2 kA correctors.

The thing about DS22 is that various design choices made it very difficult to improve it any further. There was also no motivation to start a new design from scratch, once we found an integrated ADC that does the job. Generally, the bottlenecks are in the 1-bit DAC (the switches), the first integrator, and the Vref section. We got the major LF noise improvement just by fixing the Vref.

[branadic]

Thanks for sharing. Searching the web I found one of your presentations which directed me to the desciption of the differences. Nice.

-branadic-

[Kleinstein]

For the switching DAC there are 2 options: one is switching before the resistor to the integrator and thus the voltage side. This way is used in the old Solartron meters, but als the newer KS3446x. The other option is switching behind the resistor and this more a current stirring, like in the 3458 or 34401 or Keithley 2000,  2002.  The voltage side switching has advantages from using the same resistor for the positive and negative side and also less sensitivity to charge injection. Reasons for using the votlage side switching can be fast modulation (because of charge injection) and long integration (using only 1 resistor).  However buffering the references is a new tricky point, that is not an issue in the current stirring way.

The other decision for the ADC is whether one wants very low LF noise and drift directly from the ADC. This requires some kind of AZ OP in the integrator and allows very long integration at a piece (like the old Solatron, the Datron 1281 and to some repect also many of the SD ADC chips). The other ways is an ADC with limited LF performance and drift and than an external auto zero cycle in the front end, like periodically switching between the input and zero or in some cases also reversing the polarity. This is done with DMMs like the 3458, 34401, K2000. Some high end ADC chips also offer this option in addtion to an already low drift ADC core. Switching relatively close to the input creates a kind of semi digital chopper and can suppress 1/f noise and DC drift also from the amplifier very effectively.
Az switching at the frontend wants relatively good settling for the ADC after switching - some SD ADCs are not very good at this.

The type of ADC thus also effects the front end. At least for 7 digits, there are several different ways to the target, with different weaknesses.

[julian1]

For dual/multi slope adc, the idea of using a high-side switch before the resistor - so that only one prec resistor is needed, and so that resistor 0.1-10Hz noise (current noise?) and TC is fed equally (and cancels) to both the +ve and -ve reference integrator currents is appealing.

My initial thought, was the tradeoff - that high-side switch/ops would have to handle full-range voltage transitions for +ve/-ve reference voltages and that would create transients.

But perhaps one could apply the same double-throw switch strategy as used by low-side (after the resistor) switch designs. So that the reference op buffers always see the same voltage potential and loads on their outputs.

ie. when feeding -ve to the integrator, then the +ve ref buffer voltage is diverted to a +ve sink in order to maintain the same sink current and voltage (as it would feeding the integrator) and vice-versa.

Maybe high-side switch designs already do this?

It is interesting how much attention is given to handling diverting currents.

The 34401a uses the inductors/ferrites on the diverting output currents as well as pin 7 gnd of the 4053.

K2002 *appears* to me to use inductor/suppression filter (BLM32A07 ) as well as a op buffering agnd (U808) to help sink current. presumably to keep switching noise affects off of signal agnd.

[Kleinstein]

The idea of using additional switches to keep the current for the reference constant is nothing really new. Some meters (e.g keithley 2001) already use this.
Besides the slow average current this also compensates some of the charge injection at the switches. Still the compensation of the charge injection is not perfect and with a delay to make sure to have breake before make the very high frequencies can be also worse. The reference buffers still have to deal with the very short pulses. So the buffer may see 2 opposite sign pulses with a some 10 ns delay. For such a short pulse a ferrite can be quite effective.
 
Besides the fast pulse, there is another weakness with high side switching: The compensation of the switch resistance is more difficult. With CMOS switches the resistance at the low side and high side can be different. Driving the input swich can be tricky to get a constant gate votlage. So high side switching tends to use lower resistance switches and rely less on compensation. Lower resistance and higher voltage rating leads to more charge-injection. Modern MOSFETs often have a limites gate voltage rating and this limites the possible reference voltage level.

The dual slope ADC can use 1 resistor for the integrator. The Multislope ADC usually still needs separate resistors for the input and the reference. There is the theoretical way of adding to the input voltage with a switched capacitor, but this way is rare (I know a multi-slope in a sinclar DMM and the SD ADC in the Prema DMMs). Low side switching with separate resistors for the positive and negative references has some additional offset-drift and possibly 1/f noise of the resistors (current noise). However one ususally still has the resistors in generating the negative reference. A relatively fast auto zero cycle can compensate much of the dift and 1/f noise. The effect on the ADC gain is the same for low and high side switching and the additional resistor is not a problem here. Good resistors with low 1/f noise are available, though some arrays (e.g. NOMCA) show significant noise.

[julian1]

I noted your comments on nomca resistors and noise in the past.  It seems surprising, and I would have naively assumed that thin-film would be broadly comparable as a technology (I also have a bunch of spare nomca soics).

For lt5400, the datasheet states  "Excess Current Noise Mil-Std-202 Method 308 <–55dB" . but I have no idea how to interpret that figure, or even if it is relevant. 

I have used vishay vtf series (Passivated nichrome) https://www.vishay.com/docs/60038/vtfstd.pdf, in a project. They have great TC tracking, but are less commonly available or well-known.

Is there anything that stands out, and what did you decide to use for your ADC board?

[Castorp]

I noted your comments on nomca resistors and noise in the past.  It seems surprising, and I would have naively assumed that thin-film would be broadly comparable as a technology (I also have a bunch of spare nomca soics).

For lt5400, the datasheet states  "Excess Current Noise Mil-Std-202 Method 308 <–55dB" . but I have no idea how to interpret that figure, or even if it is relevant. 

There's a big difference between different types. I did a study and the paper is more or less ready, waiting for green light to be submitted.

LT5400 is a rare exception in terms of specified Noise Index. Usually in the datasheets they give something like <30 dB or <40 dB for foil. Actually LT5400 has even less - it's better than -60 dB, but there are other thin film ones that are even quieter. I think with <60 dB you really don't have to care much - that's less than 1 nV rms/VDC/freq. decade. NOMCA and AORN are 2 orders of magnitude noisier, which is already significant in places where you aim for low 1/f.

[Kleinstein]

The Mil Std.202 noise specs are relative to 1 ppm resistance variations over 1 decade in the frequency. So a -40 dB noise index would be 0.1 ppm fluctuation in the resistance over 1 decade in the frequency (like 0.1 to 1 Hz). With some 10 V applied to the resistors, this would be some 1.4 µV_rms noise for the 0.1 to 10 Hz range and thus quite significant compared to a presion OP (often < 100 nV_rms (600 nV_pp) for the 0.1 -10 Hz band)
The noise specs for the resistors can often be just a test limit. It is not easy to measure the resistor noise to a low level (e.g. < -50 dB).
So chances are the < -55 dB for the LT5400 and other low numbers could be just the limit of the test system.

The NOMCA resistors show some noise, noticable, but also not dramatic. In my ADC they were still the dominant source of 1/f noise. My currently lowerst noise version has ORN type resistors (passivated NiCr on silicon like LT5400 - but available in 50 K and in a SO8 case). The ADC version with NOMCA resistors had about 1.5 to 2 times the noise, especially more 1/f noise. So the NOMCA resistors were the largest noise source, but it is still possible to get low noise (8 digit range) with the NOMCA reisistors with a fast (1PLC) auto zero cycle. With longer integration at a piece the resistor noise gets more important though. The resistor noise also gives fluctuations in the ADC gain. The NOMCA resistor would be only slightly worse than the noise from a LTZ1000 reference.

From the specs both NOMCA and ORN give < 30 dBi, but NOMCA are not much better than that number while the ORN resistor turned out much better - not as good as the LT5400 specs, but good enough. So far I get about 1 ppm/K TC for the ADC gain, which depends on 2 sets of resistors (reference amplification (5 K array) and the ADC itself (50 K array)). The number can scatter and this is just with 2 units.

For  the thin film resistors it still depends on the size and thickness of the film. Chances are a very thin film is worse than a thicker film and than a finer pattern. The area also matters - a 2S/2P combination gives half the noise (-6dB). There may be a tendency for TaN based resistors (like NOMCA) to use a rather thin film because etching can be more difficult (TaN can be quite innert - a reason it is good for resistors).
The same resistance can be acheived with a more uniform block and very thin film or a fine etched meander pattern and a thicker film.
Chances are the fine etched pattern is lower noise. The details on the surface may also make a difference.
There are also NiCr resistors with quite some noise. PTF56 (10 K) THT resistors did not perform much different from the NOMCA array. I tested (extra noise test, not in the ADC) Susumu RR (4 K, 0805 size) and I could not see much noise to about a -50 dbi test limit.

Chances are the VTF resistor arrays are likely OK, but not guarantied. The < -35 dbi noise specs could be just a measurement limit. They offer resistor arrays with a large ratio and thus must have reasonable capability for fine patterns.

The user CASTROP did show some noise measurements (upfront)  here in the forum. It includes NOMCA and ORN, but I don't think it includes VTF.

[julian1]

// Not sure if this is the right/best thread.
 
Here are some very preliminary experiments with a Kleinstein inspired design ('4053 switch and biased resistor ladder, for low-current rundown slope), with a fast comparator lt1016 10ns for crossing detect and rundown.

My main focus has been on the control side, to understand and get the 4 phase (2 fixed, 2 var) modulation scheme working.

For the simplest possible test - 4 phase switching of the +- ref currents, with no input signal, and using the same current (not slow) for final rundown, no initial integrator reset short, and slower waveform (around 2kHz) than desirable.
   

Each line represents an integration time of 5 seconds, with a 20MHz clock, so a 100 million count.
(the fixed pos phase was biased for test purposes, so count_up != count_down)


count_up 5137,   count_down 4864  rundown 6765
count_up 5137,   count_down 4864  rundown 6761
count_up 5137,   count_down 4864  rundown 6761
count_up 5137,   count_down 4864  rundown 6762
count_up 5137,   count_down 4864  rundown 6762
count_up 5137,   count_down 4864  rundown 6761
count_up 5137,   count_down 4864  rundown 6762 
count_up 5137,   count_down 4864  rundown 6761
count_up 5137,   count_down 4864  rundown 6762
count_up 5137,   count_down 4864  rundown 6761
count_up 5137,   count_down 4864  rundown 6760
count_up 5137,   count_down 4864  rundown 6761
count_up 5137,   count_down 4864  rundown 6763
count_up 5137,   count_down 4864  rundown 6763


The low variance of the final phase rundown count is an encouraging first step.


I suspect that with 5 sec integration, TC effects will dominate over 1/f noise, so it's a useful baseline, before trying to speed things up.

At cold board power on - there is a walk up of around 120-150 count over 5 minutes. which I suspect is a TC affect somewhere.
 
I tested the TC contribution of various circuit components - by dabbing a couple drops of cooling isopropyl on them.

The nexperia 74hc4053 appears most sensitive with a -50 count drop. followed by the 2x lt5400 for ladder divider and current sources, and then other resistors (ref, compound integrator, slope amp) which are hardly noticeable.


I want to try the TI SN74LV4053 as a prefered part to the nexperia (lower rds(on), faster switching) before making other changes.

I had previously ordered it, but got the tssop version by mistake, so need to reorder.

[Andreas]

Hello,

I would also try the MAX4053A (A-version) with specified low leakage current.

with best regards

Andreas

[Kleinstein]

With 5 second integration the 1/f noise can have quite some contribution. It depends on the OP used. For 5 s integration I would suggest an AZ OP for that part. So an integrator a little like the Solartron or Datran1281 DMMs.
Drift af the resistors can also be a major point. With 10 V at the resistors for the reference, 1 ppm change in the resistor would act like 10 µV change in the voltage, which is quite a bit.
The switch resistance has quite some temperature dependence and could be the even stronger effect even though the switch may be only 1/1000 if the resistance. At least there is usually quite good compensation. So it really helps to have the relevant switches on the same chip.

Leakage can be contribution too. There is huge range from the typical leakage (10 pA range) to the guaranteed values, especially with the cheap parts. The max4053 is mainly better with the test limits.

For the start a 4 step mode is Ok, epspeially with slow modulation and thus sufficient settling time. The 3 step mode has more switching but is less sensitive to settling, so it can get better INL, despite of using only half the time for the fixed pulses.

[julian1]

Swapping the nexperia for the TI 4053 part fixes the previous TC sensitivity of the switch.  I also have the Max part although I have not tested it yet.

Using the lt5400, for divider ladder and ref currents, shows a 0.2ppm-0.3ppm/C TC  (ie 20 count / C) count sensitivity.

Which by itself is quite good, and the numbers match/agree with lt5400 specs (0.2ppm/C matching TC).   

But over a longer 5 sec integration period - the thermal walk/variation means that 8 digit stability/resolution (ie disregarding hard stuff like accuracy/INL) is not quite achievable.  ref was also changed from lm399 to ltz1000 to rule out ref noise/tc.

The lt5400 footprint thermal pad has via stitching, and it measures within 1C of the board temp, as far as I can tell - so TC effects are dominated by board temperature, rather than die self-heating.

I can suck it up, and decrease the integration time to reduce thermal walk influence (and increase 1/f noise) - while adding software auto gain/offset calibration for each cycle (several comments in the forums suggest that is what the k2002 does).

And a better board layout can help - since there are several hot to92s for power supplies.

But I am also tempted to pay the money, and experiment with z foil smd placed next to each other - with the possibility that tracking TC is better than the lt5400.
 
It's crazy to think how good the U180/3458a resistors are, and considering the vintage of the design. I almost wonder if there is some additional trick going on - like multiplexing/swapping +ve ref resistor becomes -ve ref resistor for each cycle, to keep tc effects under control. 

[Kleinstein]

There are concepts / patents (AFAIR some phillips) on swapping resistors, but is not easy as it needs extra switches. The 3458 DMM does not include this. With switching at the voltage side (e.g. like in many of the Solartron meters) the same resistor is used for the positive and negative reference. This makes the resistor less critical. AFAIK the DA1281 uses a charge pump for the reference votlages and thus avoids critical resisors there.

Usually the resistor drift should not be so bad and the main effect would be some offset drift. The 3458 uses only 200 ms of integration at a piece and uses averaging for more. There is a point when longer integration does not really help anymore. I don't see a real need for 5 s integration if one has a rundown with slow slopes. Shorter integration and than averaging may be more effective.
With shorter integration the resistor drift is not that bad anymore. The offset shift has to compete with the ADC noise. The ADC gain part of the drift only has to compete with the reference and thus usually has less competition.

The LT5400 has quite good specs - not so sure the foil resistors are much better. At the high end I would consider the specs with a piece of grain - they can be effected by test limits. The specs on excess noise are often more a testlimit than actual telling things about the parts.
Specs on the long term drift are difficult by principle.

AFAIK the U180 resistors are quite large in area and the resistors interleaved  - this is a bit like having multiple parts combined. This can also improve matching and excess noise.  Gain TC of the 3458 is not that special. Something like 0.3 or 0.5 ppm/K seems to be about normal.  For my ADC versions with ORN networks I see comparable ADC gain drift values, even though the arrays only have a 2 ppm/K spec.

A point I noted is that the ORN networks also react to board bending / stress. So it is no only temperature. Humidity can also have some effect.

AFAIK the keithley 2002 does not use a gain calibration in every cycle. If at all they have it on a longer time scale.
The older meters like 2001 seem to use this and this K19x describe it in the service manual.

[julian1]

Just a quick update, maybe there is some discovered information that is useful to share with others.

I did a test board - to compare perofmance of lt5400 versus Vishay smnz matched foil resistors in soic-8. The smnz have slightly better specs on paper, so I felt it was worthwhile to compare.

In testing, I found TC perfomance of the smnz using the same currents was considerably worse - 2x to 3x compared with lt5400. This was a good result and it determines what part to focus on in future - especially given the higher price of the smnz versus lt5400.

With some more testing, I noiticed there was perhaps some self-heating/wandering issues using single lt5400s - with the packages measuring from 1C to 2C higher than the board temperature.  I am fairly convinced there is an issue here, since I can observe the correlated integrator rundown count with a thermocouple reading from the top of package - and this occurs after 10mins and the board is warm/thermally stable.

So I tried doubling-up the lt5400 resistors - from 10k to 20k, for the divider ladder and current sources. This should reduce die self-heating according to I2R, but increase 1/f noise.

In practice, the ref currents go from +- 1.4mA down to 0.75mA (which seems better intuitively), and self-heaing is spread across twice the die surface area, so it felt like it should be a win.

Result was inconclusive - measurement variance was higher - but I am not certain how much of this can be attributed to the exposed wire bodges that are susceptible to emi etc.

I really wanted to get lt5400 1k or MORN 500R, to substitute in the same footprint as the lt5400 10k - and make it easier to swap and experiment with ref currents without board revisions, or lots of extra footprints. But the supply chain issues are real and there are none available anywhere. Searching the web, I found one manufacturer of 0R jumpers in MSOP-8 which would be ideal, but they had non in inventory and would need to retool .

Also did a board, paying a lot more attention to star grounding, but also made some mistakes - and performance was worse than the original board.

Waiting on another board, before I get to do some more tests.

[Kleinstein]

Using 750 µA of reference current would be very much on the high side. There are 2 other problems besides self heating: the CMOS switches get nonlinear at high currents. So one would also need lower resistance switches. AFAIR the Ti LV4053 switches showed still noticable nonlinearity at 700 µA.
Another problem is the load to the op in the integrator. With a higher load current the may also get nonlinear, at least this effect is mentioned in some literature.

The divider ladder to amplify the reference voltage is not so critical. Here the voltage and thus the self heating is constant and thus kind of acts like resistor tolerance.

I don't see why a reduced current should increase the 1/f noise. The 1/f noise is usually from the OPs and maybe excess noise from some resistors (the LT5400 should be fine and hardly dedectable 1/f noise). With 2 resistors in series instead the resistor 1/f noise would be more like going down as 2 resistors are averaged. Similar less heat would more like reduce temperature variations and 1/f noise from this. A larger resistance would increase the white noise part. Still even 50 K  (as 3 x 50 K to the integrator input) can get you quite low in noise. The HP3458 uses 40 K and 50 K mixed, which is slightly worse than 3x50 K.
The obvious way to fight 1/f noise is using less integration at a time ( e.g. 40 ms instead of 200 ms) and averaging over multiple auto zero cycles instead. This increases the relevant frequency.

[julian1]

With 2 resistors in series instead the resistor 1/f noise would be more like going down as 2 resistors are averaged.

Thanks, that is a very helpful insight. I was thinking in terms of thermal noise increasing with resistance. But with two resistors - even in series, with twice the die area it should be much the same.

[Kleinstein]

With 2 resistors in series each resistor will see half the voltage and thus get 1/2 the 1/f noise voltage. The noise at the 2 resistors is not correlated and thus adds as squares. So the 1/f noise would be smaller by the factor square root 2 or a 3 dB improvement in the noise index.

The white noise goes up with a higher resitance, but it still not too high.

Another noise source that goes up with a higher resistance is the current noise of the OPs. The current noise of BJT based OPs like the OP07 often has quite some 1/f component. The 1/f cross over for the current noise is often higher than for the voltage.

[Andreas]

I don't see why a reduced current should increase the 1/f noise.

Hello,

do not forget the input current noise of the OP (which is multiplied with the Resistor value at the input).
So every OP-Amp has its sweet spot regarding input impedance.

with best regards

Andreas

[julian1]

It was good to persist with this issue. The ref currents were knocked down to 7.1Vref *2 / 4x10k = +-350uA (disregard bias).

The local TC wandering of lt5400 due to self heating is no longer evident above the TC effects of the general board with its higher thermal mass.

With a 5sec integration/100 million count (slow slope disabled) the rundown count final digit std dev is < 1. Previously with higher currents stddev was around 2-3 with identical parameters.

circuit details - ladder opa2277, compound integrator 2x opa140 10k/2k divider, slope amp ad847 1k/5k, lt1016 hystersis 200k/100R.

Code: [Select]

  count_up 5215,   count_down 4789  count_rundown 1973      stddev_rundown(5) 0.40
  count_up 5215,   count_down 4789  count_rundown 1974      stddev_rundown(5) 0.49
  count_up 5215,   count_down 4789  count_rundown 1975      stddev_rundown(5) 0.75
  count_up 5215,   count_down 4789  count_rundown 1974      stddev_rundown(5) 0.63
  count_up 5215,   count_down 4789  count_rundown 1973      stddev_rundown(5) 0.75
  count_up 5215,   count_down 4789  count_rundown 1974      stddev_rundown(5) 0.63
  count_up 5215,   count_down 4789  count_rundown 1974      stddev_rundown(5) 0.63
  count_up 5215,   count_down 4789  count_rundown 1975      stddev_rundown(5) 0.63
  count_up 5215,   count_down 4789  count_rundown 1975      stddev_rundown(5) 0.75
  count_up 5215,   count_down 4789  count_rundown 1976      stddev_rundown(5) 0.75
  count_up 5215,   count_down 4789  count_rundown 1975      stddev_rundown(5) 0.63
  count_up 5215,   count_down 4789  count_rundown 1975      stddev_rundown(5) 0.40
  count_up 5215,   count_down 4789  count_rundown 1977      stddev_rundown(5) 0.80
  count_up 5215,   count_down 4789  count_rundown 1976      stddev_rundown(5) 0.75
  count_up 5215,   count_down 4789  count_rundown 1976      stddev_rundown(5) 0.75
  count_up 5215,   count_down 4789  count_rundown 1978      stddev_rundown(5) 1.02
  count_up 5215,   count_down 4789  count_rundown 1978      stddev_rundown(5) 0.89
  count_up 5215,   count_down 4789  count_rundown 1976      stddev_rundown(5) 0.98
  count_up 5215,   count_down 4789  count_rundown 1977      stddev_rundown(5) 0.89
  count_up 5215,   count_down 4789  count_rundown 1977      stddev_rundown(5) 0.75
  count_up 5215,   count_down 4789  count_rundown 1978      stddev_rundown(5) 0.75
  count_up 5215,   count_down 4789  count_rundown 1978      stddev_rundown(5) 0.75
  count_up 5215,   count_down 4789  count_rundown 1979      stddev_rundown(5) 0.75
 
   
       
To move a bit from baseline tests in favor of a pragmatic design - and decrease the measurement interval from 5s to 1s;
 
This test addresses 1/f noise, by multi-sampling the uncorrelated output of several shorter integration periods.

Using 200ms/4PLC integration period. Mean of 5 samples, for a 1sec measurement interval. With the slow rundown (30uA) enabled, the stddev of each individual integration goes up. But the aggregated values are good. ( stddev(mean(n=5)) < 1 ).

Code: [Select]

  count_up/down 263 238, clk_count_rundown 54838, stddev_rundown(5) 1.47, mean (5) 54835.80, stddev_means(5) 0.27
  count_up/down 263 238, clk_count_rundown 54840, stddev_rundown(5) 2.14, mean (5) 54836.80, stddev_means(5) 0.50
  count_up/down 263 238, clk_count_rundown 54836, stddev_rundown(5) 2.15, mean (5) 54836.60, stddev_means(5) 0.56
  count_up/down 263 238, clk_count_rundown 54834, stddev_rundown(5) 2.15, mean (5) 54836.60, stddev_means(5) 0.48
  count_up/down 263 238, clk_count_rundown 54839, stddev_rundown(5) 2.15, mean (5) 54837.40, stddev_means(5) 0.51
  count_up/down 263 238, clk_count_rundown 54835, stddev_rundown(5) 2.32, mean (5) 54836.80, stddev_means(5) 0.29
  count_up/down 263 238, clk_count_rundown 54836, stddev_rundown(5) 1.67, mean (5) 54836.00, stddev_means(5) 0.45
  count_up/down 263 238, clk_count_rundown 54837, stddev_rundown(5) 1.72, mean (5) 54836.20, stddev_means(5) 0.49
  count_up/down 263 238, clk_count_rundown 54834, stddev_rundown(5) 1.72, mean (5) 54836.20, stddev_means(5) 0.52
  count_up/down 263 238, clk_count_rundown 54834, stddev_rundown(5) 1.17, mean (5) 54835.20, stddev_means(5) 0.52
  count_up/down 263 238, clk_count_rundown 54838, stddev_rundown(5) 1.60, mean (5) 54835.80, stddev_means(5) 0.37
  count_up/down 263 238, clk_count_rundown 54832, stddev_rundown(5) 2.19, mean (5) 54835.00, stddev_means(5) 0.50
  count_up/down 263 238, clk_count_rundown 54835, stddev_rundown(5) 1.96, mean (5) 54834.60, stddev_means(5) 0.57
  count_up/down 263 238, clk_count_rundown 54839, stddev_rundown(5) 2.58, mean (5) 54835.60, stddev_means(5) 0.43
  count_up/down 263 238, clk_count_rundown 54833, stddev_rundown(5) 2.73, mean (5) 54835.40, stddev_means(5) 0.43
  count_up/down 263 238, clk_count_rundown 54839, stddev_rundown(5) 2.94, mean (5) 54835.60, stddev_means(5) 0.39
  count_up/down 263 238, clk_count_rundown 54831, stddev_rundown(5) 3.20, mean (5) 54835.40, stddev_means(5) 0.37
 
   

The only problem is the lack of resolution in the runup counts, due to very slow modulation (around 1250Hz/ 10nF cap). 
   
So the next step will be to increase modulation speed (at least) an order of magnitude (12kHz). 

I will keep the rundown slope the same (by reducing ladder bias) - since the final digit of the rundown count appears to capture the variance and show where the noise level is.
 
Now waiting on an order of caps -  WIMA FKP3, PP, 1nF and smaller as well as some TDK C0G smd to experiment with.

[Kleinstein]

For the frequency of the modulation there are 5 effects to take into account:
1) The faster the modulation, the smaller the capacitor can be and thus more gain in the integrator. This reduces the noise for the final charge contribution, e.g. as noise from the slope amplifier. This is especially important with shorter integration times, like less than 1 PLC.
2) With lower modulation frequency more charge is stored in the capacitor and dielectric absorbtion gets more important.
3) With faster modulation mode time is lost to the minimal pulse length. They may need shorter minimal pulses or a reduced usefull conversion range.
4) With faster modulation the jitter gets more important (going up with the square root of the frequency).
5) faster modulation reduces the time for the worst case rundown.

1.25 kHz modulation is rather slow, a bit comparable to the Solartron DMMs.  Even 12 kHz is relatively slow and may need extra measures to reduce INL effects from DA.  AFAKI the used frequencies are some  5 kHz for the ADTV6581, 25 kHz in Keithley 2000,  ~ 330 kHz for 34401 and 3458.
Though not ideal, one can still increase the modulation frequency without reducing the capacitor size. One still gets reduced DA effect (reduced INL error), but not the reduced noise from a smaller cap.

The choice of AD847 for the slope amplifier is a bit odd, though it is used in other DMMs (e.g. K2002). The slope amplifier in most versions does not have to be very fast - one reason for the slope amplifier is to limit the bandwidth. So faster is not always better. This is a bit different from the simple dual slope ADC where a limited speed of the slope amplifier / comparator  leads to an error in the range around zero. With the MS ADC a delay from the slope amplifier only results in some offset and a bit more minimal time for the rundown steps.
The noise of the slope amplifier can be important for the residual charge measurement, so especially important with a large capacitor. The noise there is set by the integrator, the OP in the slope amplifier and the resistor(s) at the slope amplifier. A low resistance at the slope amplifier needs more current that may lead to nonlinear effects from loading the integrator - at least this is a possible INL source.