7.5digit diy voltmeter?

[julian1]

The ad847 (15nV/√Hz, 50MHz) is old school and copied from the k2002.  I initially had a lt1358 (25MHz, 8nV/√Hz ) and 10k/10k. as the only other fast op in my possession.

I am uncertain about the need for much slope gain, since the lt1016 already boasts GBW ~= 50GHz according to the datasheet. Maybe the next test will be ne5532 (5nV / 10MHz) and 5k/5k. Power and heating is low because of the limited voltage range +-0.7V, but with 1k/5k I did forget about the possibility of loading on the integrator.

With some term adjustment and a 2 variable regression model, and calibrating against the local ref at 7.1V, I now get measurements in the voltage domain!..

Code: [Select]

    clk_count_int_n   20000000
    period            1.000000s
    nplc              50.00
    clk_count_init_n  10000
    clk_count_fix_n   700
    clk_count_var_n   5500
    mod freq          909Hz
    use_slow_rundown  1
    himux_sel         1101 ref-hi

    sampling ref-hi
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26348, predict 7.099,998,9 stddev(5) 0.36uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26345, predict 7.099,999,3 stddev(5) 0.30uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26342, predict 7.099,999,6 stddev(5) 0.30uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26341, predict 7.099,999,7 stddev(5) 0.36uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26337, predict 7.100,000,2 stddev(5) 0.49uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26336, predict 7.100,000,3 stddev(5) 0.43uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26336, predict 7.100,000,3 stddev(5) 0.38uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26335, predict 7.100,000,4 stddev(5) 0.19uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26343, predict 7.099,999,5 stddev(5) 0.38uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26335, predict 7.100,000,4 stddev(5) 0.38uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26340, predict 7.099,999,8 stddev(5) 0.38uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26341, predict 7.099,999,7 stddev(5) 0.36uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26339, predict 7.100,000,0 stddev(5) 0.30uV,

    sampling ref-lo
    count_up/down 1696 1540, fix_up/down 1618 1618, clk_count_rundown 59344, predict -0.000,001,1 stddev(5) 0.46uV,
    count_up/down 1696 1540, fix_up/down 1618 1618, clk_count_rundown 59347, predict -0.000,001,5 stddev(5) 0.43uV,
    count_up/down 1696 1540, fix_up/down 1618 1618, clk_count_rundown 59344, predict -0.000,001,1 stddev(5) 0.24uV,
    count_up/down 1696 1540, fix_up/down 1618 1618, clk_count_rundown 59338, predict -0.000,000,4 stddev(5) 0.43uV,
    count_up/down 1696 1540, fix_up/down 1618 1618, clk_count_rundown 59348, predict -0.000,001,6 stddev(5) 0.40uV,
    count_up/down 1696 1540, fix_up/down 1618 1618, clk_count_rundown 59344, predict -0.000,001,1 stddev(5) 0.40uV,
    count_up/down 1696 1540, fix_up/down 1618 1618, clk_count_rundown 59339, predict -0.000,000,6 stddev(5) 0.42uV,
    count_up/down 1696 1540, fix_up/down 1618 1618, clk_count_rundown 59345, predict -0.000,001,3 stddev(5) 0.44uV,
    count_up/down 1696 1540, fix_up/down 1618 1618, clk_count_rundown 59338, predict -0.000,000,4 stddev(5) 0.44uV,
    count_up/down 1696 1540, fix_up/down 1618 1618, clk_count_rundown 59342, predict -0.000,000,9 stddev(5) 0.32uV,
   

I want a good record for baseline performance before playing with other circuit changes (speed, samples, slope amp etc).

INL looks tricky. My sig-gen wanders at the 4th and 5th digits for DC. And my 6.5meter doesn't show final digit uV on a +-10V range.

I experimented with perturbing the modulation frequency slightly, while holding the same cal coefficients. And I get around +-5uV delta sampling ref-in.

Other eevblog threads suggest a good proxy test is to sweep voltage - and plot different modulation parameters/ and swap input polarity (turnover test)

The options I am considering to generate these input voltages are,

Another ltz1000 ref (1.2uV p2p 0.1-10Hz) + bipolar dac (1uV RMS 0.1-10Hz) .

Alternatively a largish (buffered) capacitor and switching to be able to be able to charge/discharge it.

Both possibilities need another custom pcb, which will be slow with the new year.

The problem with the sweep techniques is that they won't reveal the true shape of non-linearity (which might also be corrected with non-linear terms) .

[chuckb]

It seems the Analog to Digital Converter researchers and the Frequency Stability researchers have a similar Functional stage, the low-noise, low-jitter comparator. I have not seen a good analysis or methodology for designing the comparator stage in the ADC. However there are several papers written about the comparator stage for the Frequency Stability analyzers.

http://www.ko4bb.com/getsimple/index.php?id=bruces-zero-crossing-detectors

There may be information or ideas here to apply to the design of the ADC.

[Kleinstein]

With the multi-slope ADC the slope amplifier is not so much about making the comparator to react faster also with a small slope. The slope amplifier also has the job of limiting the bandwidth for the final change measurement / trigger. So the speed is a compromise between the speed and noise.
The speed is somewhat critical in the simple dual slope ADC, when the rundown part can come from both sides. In the MS ADC the final rundown oart usually comes allways from 1 side and a fixed delay is thus not critical.
With the additional final charge measurement from the auxiliary ADC the slope amplifier is also part of the amplification for this signal. In this case the comparator is rather uncritical.


For the turn over test any stable external reference can do, one does not really need a special PCB for this. For the start a LM399 or 1N829 based ref should be good enough, though a bit more noisy. Ideally one would do the turn over test at multiple voltages, e.g. with a divider and buffer amplifier.
The circuit is still simple enough for raster prototype board.
The polatity change can be with 2 SPDT switches. So with the 2 switches one will have 4 readings: 2 offset readings and 2 voltage readings. The 2 offset readings can compensate of the offset of the ADC and also extra offsets / thermal emf from the switches.

The test with the slowly drifting voltage and different ADC modulation modes does not need a sofisticated layout or PCB - I used a breadboard for this part with no problem.

[julian1]

Here's a plot using two sets of modulation parameters - with 10NPLC/ 1nF TDK C0G/16kHz across a +-11V input source.

The overall plot shape/ and (lack of) tightness in the cluster observations is influenced by DA on the cap (10uF/X2 class MKP/PP) used to generate the source voltage, as well as settle time between measurements.  The switching and sweep is automated on the mcu side which is nice. But there's a compromise to be made in shortening the sweep time to get useable results in a reasonable period (1hr) .

Also tested faster modulation 330pF/45kHz with the expection of higher noise, but better INL. However INL appears a bit worse - perhaps due to clock jitter, or more charge injection variation.

Input short noise (at 16kHz) is around 350-400nV RMS at 10 NPLC, which is reasonable, and not really observably higher when sampling ref-hi due to the ltz1000.

But there are some quantitization issues. With a 100k ladder bias resistor (foil), the rundown count acheives a measurement resolution of around 500nV on a +-11V range (perhaps ok for 7.5 digit resolution).

To experiment with higher resolution, I increased the ladder bias resistor from 100k to 250k. 

But somewhat surprisingly this also increased the INL at both 16kHz and 45kHz modulation frequencies.

Initially I considered this might be due to extra DA non-linearity persent due to the longer rundown phase. But I think, there is another effect present as well.

After signal integration is stopped, the cycling of the ref currents is continued until the integrator output voltage lands above the zero-cross - in order to be able to start the rundown.  This continuation cycling completes in a predictable way and within a fixed max period due to the intrinsitc +-ref bias (k2002 background current source, or Kleinstein ladder bias resistor).   

However, the amount of cycling is variable - and so there is a phase that is unrepresented/uncaptured, during which signal mux off leakage might influence the measurement. So I want to try to instrument and test this.

Alternatively if it does prove to be DA non-linearity due to a longer rundown period - I think it might be able to be controlled for with fancy math.

In any case, it's easy to see why residial ADCs became popular in multislope designs. Or else the ability to approach rundown from either direction to avoid extra cycling (perhaps this is what the 3458a does).

[Kleinstein]

The difference curve looks quite good. Still a little noisy, but not not much nonlinearity visible. The slight overall slope is not that uncommon and would only be a slight change in gain with the run-up pattern, so not yet a INL contribution.

Jitter would not cause INL, but more noise with faster modulation. 45 kHz modulation is still not very fast and unless slow chips of a poor oscillator is used the noise contribution should not be so bad. Expect noise from jitter to be  jitter * 2 * ref. voltage * sqrt(modulation_frequency / integration_time).
So 10 ps of RMS jitter would result in some 140 nV of noise with 50 kHz modulation and 10 PLC integration. 10 ps of RMS jitter would be pretty poor. The data I have found are 4 ps for 74LS..., 2.2 ps for 74 HC... and 1 ps for 74AC.... So the overall jitter is more expected to be in the 2-5 ps range.
The charge injection variations should also not be so significant, unless the supply is really noisy.

More INL with a higher modulation frequency can come around from incomplete integrator settling, though the main expected effect is a small change in the gain. A smaller capacitor can here also make things more tricky as the step amplitude gets larger. So for tests one could as well increase the frequency, but keep the capacitor. A smaller capacitor alone does not help against DA. It helps with the noise in measuring the final charge. At 10 PLC integration the final charge noise should not be an issue, even with not so ideal comparator or slope amplifier bandwidth.

To get a predictable sign to start the rundown, one can just add another step to the rundown. AFAIK this is also done in the HP3456 and likely also other DMMs like K2000,K2002.  So the rundown starts with the reference of the same polarity as the small slope: either a little beyound zero corssing or a fixed time if allready the right sign. Then follows the normal fast run-down, slow run-down and maybe even slower or the auxiliary ADC.
This way there is always a fixed number of switching events and even in the same sequence.  Adding extra cylces would be a problem with a variable number of switch operations, not so much the variable delay.

350-400 nV of noise with 10 PLC is OK,  about on par with the KS3446x.

[julian1]

I was asked to give a few more details about my design.

The asymmetric current source with '4053 switch are borrowed from Kleinstein's innovative design. While the fpga for control + 74hc175 synchronization + rundown comparator are more Keithely part choices.

There are a few bodges/changes from the schematic; The 80k signal input is shorted to 40k (properly compensated, but badly distributed) and the current bias resistor is paralleled across only one of lower ladder resistors (shallower slope with less resistance).

The bootstrap circuit was tested independently with a sig-gen and is stable with RC set to 1/2 to 2/3 of the op GBW but has not been used yet. I think it has some issues;

Namely, the source/sink are set to fight each, so the bottom bjt q6 needs to be jumpered by a resistor.  also the 100R emitter degenerators defeat the purpose of bootstrapping by dropping a varying voltage, and should be 0R. I also want to replace the dual diode sot-23, with a more conventional two bjt current source.

At the moment I get a 20uV stderr trying to fit a 3 point (+7, 0, -7V) linear calibration, which I suspect is due to using the opa140 buffer standalone, and without the bootstrap.

I also did a board with Linear Systems dmos switches, and current sources, but it has not been tested.  Also a board with a standalone stm32, but I had trouble trying to juggle control using peripheral timers/interrupts

[julian1]

Then follows the normal fast run-down, slow run-down and maybe even slower or the auxiliary ADC.

Doing a 'fast rundown' phase is a great idea. I tried adding a bunch of short up-direction phases, until an up direction cross, before switching to slow rundown. But the goal was to figure out whether (stopping) extra-cycling was causing INL issues, and it didn't help, and was removed.
 
It turns out, there was still some unbalanced charge injection issues.

- I believed ref switch transitions were ok, because of code to count them. But these checks were forgotten around the rundown changeover sequence. At the conclusion of runup, to keep the switch transition counts the same, the on switch used in the last phase must first be turned off (so both switches are off). And then both switches can turned on for slow rundown. Instead, if the off switch is immediately turned on for slow rundown, there is a off-by-one error in switch counts /and charge injection balance.

Also, I suspect an error in the clk counts, based on how the state transitions is done. This was fixed by using raw clk count values, instead of counting (var,fix) phases and then multiplying by the constant clk duration of the phase. This approach is cleaner and simpler.

The higher frequency (330pF/45kHz) modulation chart now looks more behaved.

[Kleinstein]

An OPA140 as a buffer should not give that much error. The CMR is very good (140 dB typ) and the loop gain is also not that bad (126 dB). So I would expect more like < 5 µV of error from that buffer. One of the weakest points could be the cross-over distortion of the output stage.

The bootstrapped supply may still be a bit on the fast side. When combining amplifiers usually a factor of 6 to 10 in the BW is a good idea.

For the refrence switching there is no need to absolute balance the number of switching the positve and negative side. The important point is only to keep the number constant, independent of the signal. The subtraction of a zero readings takes care of any offset as long as it is constant.

The slope amplifier as shown still looks quite fast. It may help to slow it down a little, either with a capacitor in the FB or simply more gain.

Doing the control with an STM32 can be a bit tricky. I have it working that way, using PWM to control the reference outputs. Run-up with SW and interrupt and the rundown part with HW timing using the trigger function and toogle mode. It is still some hassel to set up the next step in time and causing some delays and not all of the STM32 support the internal comparator as trigger source.
When using just the comparator and slow slope, it would make sense to make the slow rather small. The Keitley2000 already uses 1/128 for the small slope.

The last curve for the linearity looks already quite good.

[macaba]

Confirmation of OPA140 CMRR (OPA140 configured as unity gain buffer. DMM measuring input-to-output. Measured CMRR = 142dB.)

[julian1]

The previous proxy INL chart was for 80k/40k for sig/ref input resistors.

When signal input resistance is cut from 80k to 40k, input-short noise is basically halved. Now around 250-350nV RMS 10NPLC.

But there is a bit of a cubic shape present. This is strongest on the positive side (affected more by bias). Ratio of up/down var phases here is something like 20:1 at >10V.

If 50k/40k sig/ref is used instead (incidently what the 3458a uses), the response is much flatter, albeit a slight non-linear shape is still detectable, The up/down var ratio is much less extreme at the Vinput bounds - something like 6 : 1.  But noise is also higher.

The input resolution is currently around 128nV.
Using a slope amp with 2k/20k.

I think I prefer the lower noise and matched TC, of 40k/40k for sig/ref versus 50k/40k. But it may need some software correction of non-linearity.