7.5digit diy voltmeter?

[Bootalito]

I was thinking of embarking on a voyage: constructing an open source DIY 7.5digit volt meter.  Now I know doing this is more than just buying highly speced parts and slapping them together, but it doesn't seem out of the realm of possibility to do the following:
1. Construct an xdev's LTZ1000 reference, and burn it in for 1000hours
2. divide the reference in half(or something) using a precision resistor network and feed this into a 24ENOB ADC like AD71772 (has built-in rail to rail op amps).  Its not like a can design my own custom multi-slope integrator....
4. Feed test voltage in through another precision resistor network (so only a single range volt meter), or not...make it like a 5V max volt meter or something...
5. Add some input protection: PTC, MOV, maybe a Zener in case someone feeds in to much voltage.
6. Use a linear power supply with a properly isolated digital ground and analog ground
7. Use some sort of uC, a decent size LCD, a couple of rotary encoders, a couple of pushbuttons
8. Bob's your uncle!

Of course I would expect a long process with experimentation, and many board revs, but with the right engineering a 7.5digit volt meter, or at the very worst a 6.5digit noiseless volt meter.  I couldn't find anywhere where someone has taken this on, or perhaps I'm wrong?

[The Soulman]

I think you meant AD7172?

http://www.analog.com/media/en/technical-documentation/data-sheets/AD7172-2.pdf

24 noise free bits at 5 SPS

In theory it can reliable produce 16777216 counts or 7,5 digits, accuracy and linearity at that level are a entirely different thing.

Edit: Scullcom hobby's on youtube did a similar project, was going to link it here but youtube ain't co-operating. 

[james_s]

It sounds like an interesting project if your primary goal is to stretch your engineering abilities and pull off a unique challenge. On the other hand if you're trying to reduce the cost of 7.5 digit meters I don't think that's going to happen, frankly I'd be surprised if you can get all the parts for less than what a good used commercial meter goes for.

[Bootalito]

@Soulman
I meant the AD7177-2 with the 24.7ENOB @ 5SPS http://www.analog.com/media/en/technical-documentation/data-sheets/AD7177-2.pdf
I've watched all of Scully's videos, and this project would kind of be an extension of that. It doesn't look like he ever attained the precision, accuracy, he was shooting for, nor did he complete any long term stability testing.  Greg Christienson improved upon the design here: https://www.barbouri.com/2016/05/26/millivolt-meter/#comment-523, however upon close inspection of his PCB layout I think he may have made a few errors like not including the vREF and ADC in AGND with a star ground at the ADC, not providing a direct current path back to ground for the VREF and ADC (which would probably be fixed if they were put in AGND), placing DGND under the VREF and ADC, using a common LM7805 instead of a low noise linear reg, placing the linear reg close to the ADC and VREF (heat) , placing a ground plane right next to power traces (capacitance), and placing some bypass caps down an "alley way" trace away from pins.

@james_s

Yes this project would be solely as a new challenge for myself.  It would force me to upgrade my equipment so I can take the appropriate measurements (my wife is going to kill me...), I'd have to develop all kinds of testings procedures to collect accurate repeatable data, etc.  I'm not even an electrical engineer (Chemical Eng by degree, Control Systems Eng / programmer by trade) or have any formal electronics training.  Even if I can only pull of a decent 5.5digit meter the experience would be invaluable.

[ez24]

Thanks for your info and links.  I am trying to determine if there was alien interference into the electronics field in the 1990's.  I had given up until I found a link to a link in your post.  So I am working with what I can find now.     There were power supplies that were very advance and in 20 years they have completely disappeared (the people).  There was a photo in the links that said it was them but it was a government building that has rocket shape designs on it.  I hope they find out about this message and invite me to their planet to stop me from exposing them because I need a vacation.

[Bootalito]

Thanks for your info and links.  I am trying to determine is there was alien interference into the electronics field in the 1990's.  I had given up until I found a link to a link in your post.  So I am working with what I can find now.     There were power supplies that were very advance and in 20 years they have completely disappeared.  There was a photo in the links that said it was them but it was a government building that has rocket shape designs on it.  I hope they find out about this message and invite me to their planet to stop me from exposing them.

I'm sorry...what now?

[David Hess]

The AD7172 by itself is not going to support high input impedance dividers so you are also going to require an impedance converter with 7.5 digit accuracy.  That likely means bootstrapping and input bias current cancellation if not some capability to do automatic zeroing.

[beanflying]

I have been rewatching the Bob Pease videos again. Well worth it if you haven't or even worth watching again. One on noise too.

[RandallMcRee]

Sounds interesting.
I would like to do something similar. My thinking is to use a 'standard' A/D evaluation board from either TI, AD or LT.  So for the 7177-2 you could use the http://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD7177-2.html
If your project goes with, say, the LT25000-32, then this
http://www.linear.com/solutions/7783 (but you would need to use one of their companion boards in addition)
http://cds.linear.com/docs/en/video/LTC2500-32_Thoren_v2.mp4

The purpose of deciding on an eval board is simply to leverage the ability to write software for the A/D side of things, as well as removing uncertainty around some of the precision analog engineering. Plenty left, of course. What are your thoughts on leveraging such an eval board?

At the end, I think you will still need a calibration step in order to meet your goals, btw.

[David Hess]

Neither of the evaluation boards are intended for something like a 7.5 digit (or better) DC voltmeter application.

[Vgkid]

I have been rewatching the Bob Pease videos again. Well worth it if you haven't or even worth watching again. One on noise too.

*snip*

I have long been looking for that in print(online) , but have never found it.

[beanflying]

I haven't seen it is print. Not sure how many of the old videos are available by % of what was ever done but lots to be gained from them especially now as a lot of 'doesn't matter we can fix it in firmware/software' seems to happen to often.

I do love the rats nest prototyping 

[branadic]

Hi,

looking at the datasheet of AD7177-2 I can see a typical INL with all input buffers disabled of typical ±1 ppm of FSR and max. ±3.5 ppm of FSR, with an unpredictable shape of error curve. It will be a challenge if not impossible to linearize the beast to perform as a comparing 7.5 digit instruments.

If you have a look on PRI 5610 26 bit ADC once made by PREMA you find:

PRI 5610 E:   typ. 0,05 ppm,   max. 0,08 ppm
PRI 5610 F:   typ. 0,1 ppm,   max. 0,2 ppm
PRI 5610 G:   typ. 0,2 ppm,   max. 0,5 ppm

unfortunely used in their 7.5 and 8.5 digit multimeters.

The good old LTC2400 datasheet quotes INL:

VREF = 2.5V:   typ. 2 ppm,   max. 10 ppm of VREF
VREF = 5V:   typ. 4ppm,   max. 15 ppm of VREF

with a predictable error curve that can be calibrated to <1ppm with only a few points. You can also have a look on this board:

OSHW - 24bit ADC measurement system for voltage references

There have been several attempts to build up a voltmeter in the past, so maybe you want to start reading the Open Source Hardware section first:

Open Source Multimeter

and don't forget what you are aiming for:

7.5 digit accuracy means 0.05ppm linearity while ±1ppm linearity error means something like 5.5 digit accuracy. The rest is for the dumpster.



-branadic-

[mycroft]

Is there a follow up (video or text) for this video? The circuit looks very interesting!

[BU508A]

This is the datasheet of the PRI 5610 ADC made by Prema.

[Kleinstein]

There usually is no need to get INL down all the way to the resolution limits. There is still quite some use of resolution better than the INL. Still a good meter should give you a good INL. For most of the part INL is more difficult than noise - thus it can still make sense to have a 7 digit resolution with an 1 ppm INL error.

Still the integrates ADCs tend to work on a small scale, like +-2.5 V or so. This is a little unconvenient with the better voltage refs at 7 V or 10 V. So if  would be good for a meter to have a well working (low INL and high impedance) range that includes 10 V. This get difficult with the integrated ADCs.

[Kleinstein]

Getting the noise down is not that difficult anymore with modern parts. One big advantage with noise is that one can pretty much calculate up front how much noise one can expect from a circuit. The noise specs on the integrated ADCs are somewhat limited, but some are rather good and would be sufficient for 7.5 digits.

With INL it is not that easy to do an upfront calculation, as at the PPM level there are tiny oddities like self heating, dynamic loading of the reference, nonlinearity of resistors and caps can come into play. Also supply "noise" can come into play - so something like power decoupling can come into play. Also OPs often only have CMRR specs in the 120 dB range (or less) - this could cause 1 ppm INL already, though its usually less. Another factor can be switches - those CMOS switches on resistance is not perfectly linear.  It is hard to tell how the contributions to INL will add up together as the specs of the parts are usually not that specific. INL is just more difficult to describe than noise. At best one gets typical curves, but who knows how typical they are. Testing the INL to sup ppm level is also rather difficult and slow.

Compensation for non-linearities is possible in some cases, if this is a kind of simple type, like a 3rd power contribution one might get from self heating. However it still needs a kind of reference and extra adjustment measurements - so this can usually only be done for a limited number of points and temperatures. Especially the lower noise SD ADC chips tend to have an INL that is more of the odd shape and thus essentially impossible to correct - this is because they kind of need to go beyond the simple 1 bit 2nd order SD concept.

If you kind of copy a multislope ADC design of lets say the Keithley 2000 or 2001 or HP34401, getting the noise lower that the original should be relatively easy with modern parts. The difficult part is getting it really linear - that is better than 10 ppm INL. That is the part where the magic is build in.  Most of those odd badges / changes and tweaks in the Datron 1281 are for linearity, not for noise reasons.

[Bootalito]

Amazing discussion so far. Thanks for everyone's insights. I really hadn't considered INL, as I only learned of this last night! I suppose this is why custom multislope adcs are used.
Since I don't have the equipment or the expertise yet, I think the only path that would get me even close would be to design and fully characterize successively better volt meters(3.5, then 4.5, 5.5,etc).  This of course will maximize the Learning/cost ratio and see how far down the rabbit hole I'm willing to tolerate. I mean... To even test a 7.5d meter I'd need an calibrated 8.5, and i can't justify buying one right now(to my better half.. I can justify anything to me, heh)

I do like the idea of using evaluate boards. At a minimum to get started and to see how things "should" be designed. And at most to be the backbone of a good 5.5d or even 6.5d design. Maybe?

I've also been thinking of starting a YouTube channel for the main purpose of sharing my industrial control knowledge with other Automation engineers(pid loops, difference between diff and se inputs, etc). A lot Automation engineers are operating under the "someone more senior told me to do it this way 10 years ago" and really don't know what they are doing. So I think I'd try to document every step of this journey in the fashion of Scullcoms channel (project based tutorials sprinkled with thoery/design explanations)

[Magnificent Bastard]

I don't think you are going to be able to buy an off-the-shelf ("we do it all for you") ADC chip that has 24-bit precision.  Note that accuracy != precision != resolution.  Your ADC is not going to be more accurate than the reference.  At best, this parameter is limited to somewhere around 1ppm/year.  The precision is the INL spec; this means that each bit has meaning, and is repeatable (and/or predictable).  You can have 1000 bits of resolution, but if those bits are not repeatable and/or predictable (and linear) from measurement to measurement, then they are a waste of time and money, and you are just fooling yourself.  Noise can only be filtered out if it is Gaussian. For 7.5-digits, what you are looking for is >= 25-bits of precision (which is the INL spec, even if you need "help" from the firmware to achieve that).

You *CAN* get the necessary precision for 7.5-digits (or even 8.5 digits, but that is difficult for a hobbyist), by using discrete parts (precision op-amps, low-noise dual FETs, high stability resistor ratio dividers, etc.)  Probably, the best architecture (these days) is "Delta-Sigma", but implemented with high performance parts, using multiple integrators and a multi-bit feedback DAC-- but not with a monolithic IC.

Probably, a good "first try" would be a 6.5-digit ADC (with < 1-LSB INL)-- if you can get to that point, then you will know what needs to be improved to get to 7.5-digits (with < 1-LSB INL).  Going from 6.5-digits to 7.5-digits will take at least an order of magnitude of effort, and maybe even an order of magnitude of cost.  8.5-digits (with <= 1-LSB INL) would (probably) require some custom parts as well as some highly selected parts in order for the last digit to have any meaning (other than as a marketing tool).  Going from 7.5-digits to 8.5-digits would require another order of magnitude of effort and BOM cost.  Also, at 8.5-digits, you are getting into the realm of Black Magic and Fairy Dust.  That's why I said that 8.5-digits is probably not something an average hobbyist can achieve.  I'm pretty good with designing analog electronics, but I don't think that even MY "Analog Fu" is powerful enough to pull off a good 8.5-digit ADC design all by myself.

There is a possibility of working on a "community designed" 8.5-digit ADC (with DMM front end)-- if the top talented engineers here on this forum would work together, then this might just be achievable.  It would certainly be a lofty goal to strive for.  I've noticed that there are a lot of knowledgeable engineers here, and that is a lot of "Engineering Fu" in one place-- maybe even more than someplace like Keysight or Fluke.  The problem is, getting 3-dozen (or so) highly-talented engineers (usually with big egos) to work together is a lot like "herding cats"; Good Luck with that!

[tszaboo]

2. divide the reference in half(or something) using a precision resistor network and feed this into a 24ENOB ADC like AD71772 (has built-in rail to rail op amps).  Its not like a can design my own custom multi-slope integrator....
4. Feed test voltage in through another precision resistor network (so only a single range volt meter), or not...make it like a 5V max volt meter or something...

You missed step 3. But I can help with that:
3. Realize that said resistor network doesn't exist.

[Andreas]

Hello,

I was thinking of embarking on a voyage: constructing an open source DIY 7.5digit volt meter.

That´s what I am trying (hard) since 2008.

4. Feed test voltage in through another precision resistor network

That what you need in precision so that it does not spoil the performance of your reference is not available on the hobby/industrial market. -> use better a LTC1043 instead. (ok it will increase perhaps some noise but not spoil the performance of your reference).

6. Use a linear power supply with a properly isolated digital ground and analog ground

do not forget a shield between primary and secondary side of the transformer windings.
and in any case you also need at least photocouplers between floating side and ground referenced side of the instrument.
(but even they have around 0.25pF each which can couple some noise into the ADC).

Of course I would expect a long process with experimentation, and many board revs,

so true words. At least you will learn much about parasitic behaviour of of the shelf components. Including humidity sensitivity by swelling of PCB material.

with best regards

Andreas

[Bootalito]

2. divide the reference in half(or something) using a precision resistor network and feed this into a 24ENOB ADC like AD71772 (has built-in rail to rail op amps).  Its not like a can design my own custom multi-slope integrator....
4. Feed test voltage in through another precision resistor network (so only a single range volt meter), or not...make it like a 5V max volt meter or something...

You missed step 3. But I can help with that:
3. Realize that said resistor network doesn't exist.

Oh... Well shoot. Wouldn't a 5ppm tolerance network with 0.5ppm TC be good enough with proper software calibration?

[Andreas]

3. Realize that said resistor network doesn't exist.

you were faster: but in reality the hope that it exists will never die. 
So that will be the last step.

With best regards

Andreas

[Bootalito]

Hello,

I was thinking of embarking on a voyage: constructing an open source DIY 7.5digit volt meter.

That´s what I am trying (hard) since 2008.

4. Feed test voltage in through another precision resistor network

That what you need in precision so that it does not spoil the performance of your reference is not available on the hobby/industrial market. -> use better a LTC1043 instead. (ok it will increase perhaps some noise but not spoil the performance of your reference).

6. Use a linear power supply with a properly isolated digital ground and analog ground

do not forget a shield between primary and secondary side of the transformer windings.
and in any case you also need at least photocouplers between floating side and ground referenced side of the instrument.
(but even they have around 0.25pF each which can couple some noise into the ADC).

Of course I would expect a long process with experimentation, and many board revs,

so true words. At least you will learn much about parasitic behaviour of of the shelf components. Including humidity sensitivity by swelling of PCB material.

with best regards

Andreas

Well thanks once again Andreas I've never even heard of a switched capacitor building block....

[Andreas]

Oh... Well shoot. Wouldn't a 5ppm tolerance network with 0.5ppm TC be good enough with proper software calibration?

How do you calibrate
- humidity sensitivity (very long time constant of several days)
- hysteresis of several ppms

in my resistor measurements I have found generally:
Resistors with a relative low T.C. have a relative large hysteresis.

with best regards

Andreas

[branadic]

you were faster: but in reality the hope that it exists will never die.

Hope dies last, but it dies

-branadic-

[Edwin G. Pettis]

Andreas,

Resistor TCR has absolutely no bearing on hysteresis, that is wholly a matter of construction and residual stress left after manufacture.  It is present to some degree in all resistors and tends to reduce with time even in resistors with higher hysteresis.  It all depends on how the resistor is made, what materials and what processing was used.  TCR is the inherent parameter of the wire when it is made, the process of making a resistor can certainly affect the 'apparent' TCR of the resistor but normal operating temperatures, even +125°C absolutely will not affect the inherent TCR of the alloy Evanohm.  Now if you're talking about Manganin, that is a very sensitive alloy, sensitive even to barometric pressure and usually takes quite some time to relax after manufacture.  All precision WW resistors will have at least a little bit of residual hysteresis after manufacture, while additional processing can remove more of it, there will always be some amount lingering for awhile, it will fully relax after some time.  Resistor standard grade resistors have not only gone through additional processing but they have also had additional time on the shelf to relax.  Yes, some resistors just might not to fully relax even after some time has passed, it happens.  Even film/foils have residuals that might not fully relax or go away with time, we're talking some pretty minute effects here.....patience is the best teller of quality, very good resistors will settle down to very small drift over time, others not so much.  Precision wire wound resistors are hand made after all and even the machine made Vishays aren't perfect either.

[Kleinstein]

When using a SD ADC chip which needs a reference voltage in the 2.5 to 5 V range, it might be easier to directly start with a reference chip that is made for this voltage range, e.g. LTC6655 or similar.  For long term checks one might include an extra LM399 that is than measured in the corresponding range if needed.

For a DMM quite a lot can depend on the quality of the resistors used.

There are difference limiting factors for a DMM. Usually noise sets the resolution,  INL, calibration and gain/reference drift set the accuracy and drift limits precision.  These limits can be at different levels, though with the commercial instruments they are often in a reasonable relation, though there are also differences. Some are good at low noise and other offer good INL despite of relatively high noise (e.g. Keithley 2001).

There is still some sense in having resolution much better than accuracy (e.g. due to calibration limits or higher INL). It is quite common that the INL and calibration / stability is not as good as the resolution. So INL is important, but no need to get INL to 1 ppm for a 6 digit resolution. Especially if you know about the limitations even a 10 ppm INL with 7 digits of resolution can be OK.

[tszaboo]

I have time to elaborate now. The best resistors networks will only give you 1-2ppm tracking. Even if they advertize 0.0x ppm tracking, those are typical values. Mean tracking, with +/-2ppm maximum values.
http://www.vishaypg.com/foil-resistors/voltage-dividers-networks/

This means, you can potentially select a resistor network which works for the application, but the selection is very difficult (you need to measure in the PPM region in the first place to select it) and costly. And you need to buffer this most of the time, adding extra noise and errors. And your end result is comparable in performance to a series bandgap voltage reference.

The reason it is not done is not because the lack of interest. If it would be so simple, as getting an LTZ1000 and dividing it by two, everyone would be doing that.

That being said, it is possible to improve a system with a heated buried zener reference, and bring it above the capabilities of the bandgap voltage reference.
Or it is useful to make systems, where resolution INL, DNL is higher than a 6.5 digit multimeter. Ratiometric measurements for example.

[Andreas]

the LT2400 which you and branadic used for TC measurement works, at this moment, approximately what average resolution could those produce now (with your improvements)? 5.5D ?

Hello,

that depends.
Mainly on the effort which you put into each single device.
And the comparison to any x.x digit device is difficult.
You should compare it more to a old Solartron or similar
with long integration times on high resolution
than with a modern multi-slope instrument.

If you just build it and do full scale adjustment it is actually something like a 5.5 digit instrument.
Noise for a single measurement is relatively high:
- 10uVpp or 1.8uV RMS in 0..5V range corresponding to 20uVpp 3.6 uV RMS in 0..10V range with a LTC1043 divider.
With averaging over one minute you go down to around 0.5uV RMS for a 7V stable reference
 in 10V range which is about factor 5 above a HP3458A.

What I am doing is the following:
Buy plenty of good voltage references (AD586LQ).
Select them for T.C. , hysteresis and popcorn noise.
So from 10 references you get (in average) around 2 which are suitable:
    (T.C. < 1 ppm/K (better 0.3 ppm/K), hyst < 1ppm, popcorn < 2uVpp)

Put the best of them onto ADCs which have a NTC for temperature correction.
Adjust them for T.C. (3rd order correction), INL, Gain.
The newer devices I also adjust for offset and offset drift (then paired with a LTC1043 divider cirquit).
Adjustment takes around 4-6 week-ends for each device.

Then you have simply to wait the run-in phase (switched on) until the AD586 has stabilized.
(typically 5000 hours)
You can shorten this phase partly by loading the AD586 with a 15 mA current cyclically.
(30 minutes on during  2 hours cycle).
After that you typicaly have to adjust the gain. (T.C. and INL normally only need to be checked).

What you get (typically):
- Noise 0.5uV eff @10V (1 minute integration time)
  (about factor 2 above a 1 minute average of a 6.5 digit DMM)
- INL < 1ppm (that what is specced on many 6.5 to 7.5 digit DMMs)
- Long term stability about 1-2 ppm/year (also comparable to well aged LM399 based instruments).
- Excellent temperature stability which is essential in my lab.
  (from 18-33 deg C max 1 ppm drift)
  That is why I cannot use a 6.5 DMM in 10V range for my T.C. measurements.
  The drift over one day is usual several PPMs on a K2000 or 34401A with my lab conditions.
- even better stability you get for ratiometric measurements.

But nothing comes for free.
A 6.5 DMM might be cheaper when counting all the gear you need to adjust a ADC.
And even then for exact absolute measurements there is no Auto-Zero implemented up to now.
So the 2-6uV offset you have to measure before/after each measurement.

But all in all with long integration times you have something like a 6.5 digit instrument with
some features (T.C.) being even much better.

With best regards

Andreas

[e61_phil]

- INL < 1ppm (that what is specced on many 6.5 to 7.5 digit DMMs)

I don't know the K2000, but the 34401A is normally way better than ~1ppm INL, even if it is specced worse.

As always, it is a question of the application. If you want to monitor some drift, then a high resolution may be more important than a very good INL. If you want to make decade transfers, than 1ppm isn't that great (10ppm error for 1:10).

[quarks]

many years ago I was interested to build a voltmeter from c't magazine (c't 02/2008, page 170).
It was part of a DIY project called "c't-lab".

Unfortunately it is in German but with schematics, parts list and details about design decissions.
Maybe this could be a helpfull starting point.

https://www.heise.de/ct/artikel/Messwerkeln-291398.html

[Andreas]

many years ago I was interested to build a voltmeter from c't magazine (c't 02/2008, page 170).
It was part of a DIY project called "c't-lab".

Unfortunately it is in German but with schematics, parts list and details about design decissions.
Maybe this could be a helpfull starting point.

https://www.heise.de/ct/artikel/Messwerkeln-291398.html

Hello,

a good starting point: yes. (it is a 5.5 digit design).
I got also some inspiration of the design (especially the R/C filter directly at the ADC).
But there are some mis-conceptions.

Input voltage divider built from standard 0.1% metal film resistors instead of a much better ready made divider.
2.5V band gap reference and +/- 2.5V measurement range, which increase linearity, but increase the relative noise by a factor 4.
A LM399 reference is option but uses a trim-pot and metal film resistors which spoil the good T.C.

with best regards

Andreas

[Andreas]

Hello,

here the reason why I prefer my ADCs in my unstable "lab" conditions over a 6.5 digit DMM:

During T.C. measurement of a (very stable) LTZ-device the room temperature changed somewhat.
The dips are due to a open window: perhaps I should not have done this but I would have a larger "end" temperature at the evening without that.

My ADCs (green + red) are noisy but very stable over room temperature.
ADC16 is more stable since it is additionally in a temperature controlled environment.

The DMMs show a relative large influence from room temperature.
The K2000 also seems to have a not sufficient warm up phase but is then more stable than the HP.

with best regards

Andreas

[ramon]

LTC2400 datasheet and every application note or pdf document I have read clearly states that it is intented for a 6-digit DVM application.

So only 5.5? what is needed to reach the 6 digit for LTC2400?

[e61_phil]

LTC2400 datasheet and every application note or pdf document I have read clearly states that it is intented for a 6-digit DVM application.

So only 5.5? what is needed to reach the 6 digit for LTC2400?

Linearity

[Kleinstein]

The INL of the LTC2400 is rather high to directly use it for a 6 digit DVM. However the INL curve seem to be rather predictable, and after correcting that predictable part the linearity should be good enough for a 6 digit DVM.  The noise of the LTC2400 is also relatively high - so it kind of makes it a slow 6 digit ADC.

Not all of the DVMs are equal in that respect - some are rather noisy too (e.g. HP3457, old Solartrons and Keithley 2001 - despite of claiming 7 digits).
 
Another point that make the use of the LTC2400 a little tricky is that the input range is positive only with only a minimal negative range. So real life the LTC2400 is more suitable for a 5 digit DMM or maybe a 5-6 digit display for a measurement that can be positive only (e.g. at a lab supply or maybe balance). The LTC2400 is already rather old and at it's time a real option for an DMM.  The Hameg 8012 used the LTC2400 for a 4 3/4 digit DMM, so even a little less than 5 digits. It is still a step forward from a more traditional ICL7135 4.5-digit dual slope converter.

[Andreas]

The LTC2400 is already rather old and at it's time a real option for an DMM.

Do you have a better modern ADC which has those features of the LTC2400?

- some mV overrange so that you can do full scale and zero adjustments without clipping?
- predictible INL or alternatively INL well below 1 ppm.
- the very low offset and full scale error
- the extremely low offset and full scale error drift (0.01 or 0.02 ppm/K)
- good hand solderability (so for me TSSOP is already difficult)
additionally on my wish list is of course a factor 10 lower noise and a +/-10V range input with some % over range.

but I fear with all those features the LTC2400 still has its market.

With best regards

Andreas

[ap]

Do you have a better modern ADC which has those features of the LTC2400?

e.g the LTC2508-32

[branadic]

e.g the LTC2508-32

Predictible INL or alternatively INL well below 1 ppm?

-branadic-

[Kleinstein]

At least the "typical" INL does not look that bad for the 2508. There seems to a small predictable part and a something like 0.5 ppm if more or less random variations.  The curve on the right seem to be the error including the common mode error, e.g. driving both the + and - input to different common mode voltages. So if you can avoid an uncontrolled common mode voltage, this does not look that bad.

For a DMM the unipolar range of the LTC2400 is kind of a problem and would need an added offset, or switching depending on the sign of the input voltage. This can easily degrade the drift specs or the INL or both.  For the more normal +-xx V range I would prefer an ADC with bipolar input, like the LTC2410 or ADS1234. The ADC1210 would be even available in a package suitable for easy hand soldering (SO18)  - though kind of expensive. The INL specs are not that bad if you only use 80% of the range and keep the rest for over range with degraded INL.
Some of the Ti converters work up to +-5 V and thus a useful +-4 V range with good INL.

For a DMM there is not that much gained from having a gain drift much better than reference voltage drift.

[Alex Nikitin]

For the more normal +-xx V range I would prefer an ADC with bipolar input, like the LTC2410 or ADS1234. The ADC1210 would be even available in a package suitable for easy hand soldering (SO18)  - though kind of expensive.

ADS1282 looks interesting for this kind of application (not cheap though).

Cheers

Alex

[Andreas]

  For the more normal +-xx V range I would prefer an ADC with bipolar input, like the LTC2410 or ADS1234.

They do not have bipolar inputs. The term is "differential". That means that you can measure negative differences within 0V and VCC.

The ADC1210 would be even available in a package suitable for easy hand soldering (SO18)  - though kind of expensive.

what do you want to do with a 12Bit converter?

Some of the Ti converters work up to +-5 V and thus a useful +-4 V range with good INL.

But I want to measure 10V at least. So 4 V is not a good option even with a precision 2:1 divider.

For a DMM there is not that much gained from having a gain drift much better than reference voltage drift.

I compensate the reference voltage drift to less than 1ppm/30 K = 0.03 ppm/K.
So a ADC gain drift of 0.02 ppm/K is not "much better".

Do you have a better modern ADC which has those features of the LTC2400?

e.g the LTC2508-32

could be worth a try with some tweaking like 50 Hz supression. The device seems to be optimized for 60 Hz line frequency.
I hope that the INL is more like in the first picture (under which conditions?)
But how do I solder such a device?

with best regards

Andreas

[branadic]

But how do I solder such a device?

Not a real problem. I solder such things with an iron with 0.2mm tip by hand, but you can also use a stencil and a hot air rework station. If you need help, let me know. If you have a stencil we could also use one of our reflow soldering ovens.

-branadic-

[try]

many years ago I was interested to build a voltmeter from c't magazine (c't 02/2008, page 170).
It was part of a DIY project called "c't-lab".

Unfortunately it is in German but with schematics, parts list and details about design decissions.
Maybe this could be a helpfull starting point.

https://www.heise.de/ct/artikel/Messwerkeln-291398.html

Hello,

a good starting point: yes. (it is a 5.5 digit design).
I got also some inspiration of the design (especially the R/C filter directly at the ADC).
But there are some mis-conceptions.

Input voltage divider built from standard 0.1% metal film resistors instead of a much better ready made divider.

This is true, but easy to fix. Remove the resistors that compose the discreet decade divider by an integrated one, like Vishay CNS471A5 or the equivalent made by Caddock (Caddock divider recommended to me by Edwin Pettis).

2.5V band gap reference and +/- 2.5V measurement range, which increase linearity, but increase the relative noise by a factor 4.

This is easy to overcome as well. Replace the LT1019 by a MAX6325 for instance.
There had been a design choice in favor of 2.5V. One reason was to avoid people being able to apply 1000V to the device.
With the base measurement range down to 2.5V the maximum allowed voltage is 250V.
Unfortunately that range choice requires operating the divider when measuring references of 7V oder 10V.
The linearity improvement applies for positive Volt figures only. The explanation follows down below.

A LM399 reference is option but uses a trim-pot and metal film resistors which spoil the good T.C.

You can replace the the trim-pot by a two resistors. The trim-pot is not required for an exact adjustment.
You can easily have your base range end slightly above 2.5V.
The exact adjustement ist done in software.

There are other more important issues.
When using a LM399 the design follows the 10V buffered reference as outlined at the beginning of the LT spec sheet.
The current supply for the LM399 relies on the stability of the standard 15V regulator.

One way to circumvent that issue would be to plug a self-referenced 2.5V source into the DIP socket which holds the MAX6325 in my case which can easily be constructed based upon the "portable calibrator" scheme.
I haven't tried that one out yet I have to admit.

The remaining issue is to include an auto zero function somehow.

The multimeter project within the c't-lab series extends the 2.5V range using an offset and a division by two to extend the measurement range from -2.5V to 2.5V. The side effect is that you eliminate simultaneously a big part of the predictable ADC linearity error when adjusting the zero point and the end of scale.

Follow the link and search for the graphic labeled "ADC.png".
https://www.mikrocontroller.net/topic/376240
The blue line shows the typical INL error in ppm.
The x-axis show the values of a fictitous 8 bit ADC, replace that by the 24 bits of the LTC2400.

By calibrating/adjusting zero and positive scale-end you arrive at the pink line.
Most of the INL error to the right of the 0V-point is gone, but it comes at a price when measuring negative volt figures to the left of the 0V-point.

Regards
try

[Andreas]

Replace the LT1019 by a MAX6325 for instance.

I have large ageing drifts with 2 MAX6350 (5V version of the MAX6325).
So probably a LT1019 in metal can is even better than a MAX6325.

with best regards

Andreas

[HalFET]

I've been working on my own 6.5 digit design for months, it ain't a trivial task! Especially if you're trying to design down to a cost like I am.

A few observations of mine:

• An off-the-shelf ADC doesn't do the job, unless you either sacrifice sample rate or your noise floor. I tried three from LT/AD, and another one from TI that seemed to be ok according to datasheet, but in the end they all messed up once you started looking at the temperature sensitivity and repeatability over time. I compared them to the values I got from a calibrated Keithley 2001 at the same time, the reference used was a weston cell I might add, the Keithley 2001 was measuring at the input of the ADC in each case. My conclusion was simple: don't try to push an easily available ADC beyond 5.5 digits, it typically will run into noise or stability issues and will only reach the theoretical 6.5 or 7.5 digits under very specific conditions which are near impossible to achieve in a real world multimeter circuit. I suppose this is the reason why many companies still seem to roll their own for these high resolutions.
• I found the LM399 to be the best choice due to availability, other references tend to have some supply issues at times. Additionally it fits nicely with the voltage range of a lot of the cheaper transformers.
• You're driving the LM399 completely wrong if that's your approach, never put a trimmer like that near a reference of that calibre. You can self-bias it much like you can do with the LTZ1000, the cheapest way to drive them I found is two LM317s in a servo configuration to increase PSSR and a variant on the calibrator circuit in the datasheet. It's best to go for a good quad opamp (e.g. AD704) in this arrangement since it tends to cut cost. You can then also use the remaining AD704s to buffer/fan-out the reference to your ohm's range current source etc.
• You can get away with using regular metal film array resistors to divide the reference to the correct values sometimes, some of them are thermally quite well connected to each other and make for a good enough divider. (I've had a fair amount of luck with components from Welwyn for this.) But you can also get some Caddock ceramic hybrids of Farnell if you desire, if you experience too much noise pick-up on those you can shield them by covering them in copper tape and soldering a wire to the tape and grounding the "shield" that way.
• Implementing the ADC as a discrete circuit using an FPGA seems to be the way to go, The main issue here is that you have to model the charge injection with the switches very well, that seems to be the main caveat for this design, if you need inspiration you can find the service manuals of some of the existing 6.5, 7.5, and 8.5 digit meters.
• The main importance here is that your timing is spot on repeatable, if it isn't you'll never get the timing correct.
• Do use a good ADC to monitor the integration capacitor.
• Never ever use trimmers, fix things in software.
• Go for a temperature stable circuit that ages well, try to achieve things with ratio's and use resistor arrays whenever possible and avoid trusting one "golden unicorn" component.

[Kleinstein]

  For the more normal +-xx V range I would prefer an ADC with bipolar input, like the LTC2410 or ADS1234.

They do not have bipolar inputs. The term is "differential". That means that you can measure negative differences within 0V and VCC.

The ADC1210 would be even available in a package suitable for easy hand soldering (SO18)  - though kind of expensive.

what do you want to do with a 12Bit converter?

Some of the Ti converters work up to +-5 V and thus a useful +-4 V range with good INL.

But I want to measure 10V at least. So 4 V is not a good option even with a precision 2:1 divider.

For a DMM there is not that much gained from having a gain drift much better than reference voltage drift.

I compensate the reference voltage drift to less than 1ppm/30 K = 0.03 ppm/K.
So a ADC gain drift of 0.02 ppm/K is not "much better".
....

If the reference drift is compensated to get a really low drift, one can include the gain drift of the ADC as well. The typical procedure for setting up the compensation will do that anyway.

Of one would not use the 12 bit ADC1210, but maybe a ADS1210.  Sorry for my error.

@HalFET:
For an integrating ADC, one can get away without modeling charge injection, if a PWM like mode is used. The only assumption needed is that charge injection like leakage will stay constant over short times. Unless one wants very high speed, a µC can be an alternative to an FPGA for controlling the integrating ADC. I totally agree that using an ADC to look at the integrator output is a good idea - depending on the mode used the requirements may no be that high - this might even be the cheap µC internal ADC.

[e61_phil]

For an integrating ADC, one can get away without modeling charge injection, if a PWM like mode is used. The only assumption needed is that charge injection like leakage will stay constant over short times. Unless one wants very high speed, a µC can be an alternative to an FPGA for controlling the integrating ADC. I totally agree that using an ADC to look at the integrator output is a good idea - depending on the mode used the requirements may no be that high - this might even be the cheap µC internal ADC.

@HalFET & Kleinstein:
Do you have experience in building such an ADC? Do you think it is possible to build an ultra-linear ADC (like the HP3458As one) with modern components without a special ASIC?
In my opinion the ADC (and its linearity) is still the key feature of the 3458A. Sometimes the speed of the 3458A-ADC is also nice, but even a low speed ultra-linear ADC would be a very nice transfer tool.

[HalFET]

For an integrating ADC, one can get away without modeling charge injection, if a PWM like mode is used. The only assumption needed is that charge injection like leakage will stay constant over short times. Unless one wants very high speed, a µC can be an alternative to an FPGA for controlling the integrating ADC. I totally agree that using an ADC to look at the integrator output is a good idea - depending on the mode used the requirements may no be that high - this might even be the cheap µC internal ADC.

@HalFET & Kleinstein:
Do you have experience in building such an ADC? Do you think it is possible to build an ultra-linear ADC (like the HP3458As one) with modern components without a special ASIC?
In my opinion the ADC (and its linearity) is still the key feature of the 3458A. Sometimes the speed of the 3458A-ADC is also nice, but even a low speed ultra-linear ADC would be a very nice transfer tool.

There's a reason I'm aiming for 6.5 I've noticed non-linearities in opamps already at this point. You really want to keep those supply rails far away from your signal and use a double sided supply,.

And yeah it is indeed theoretically possible to eliminate the charge injection by doing the switching right. I've just found it difficult to achieve in practice. I really need to sit down one day and redesign the sampling FSM. And personally I went for the FPGA because I want speed, additionally it was easier to sync the sampling clock with the grid that way for me, though I think I'll let that part of the circuit drop in the next itteration

[Kleinstein]

I have build an integrating ADC around an µC some time ago - though not very high performance.  I am currently actively thinking about a better way.

I don't see a principle problem it getting really good linearity without special ASCIs. Much about the special parts in the 3458 is about getting high speed. The one point I have a hard time to estimate so far is jitter and variations in charge injection with the switches. However these are more factors effecting noise and would hardly effect the linearity. The important factors for the good linearity of the 3458 are likely the good resistor(s) inside U180 (it is mainly one critical resistor), maybe the stable resistor ratio if no corrections are used and the high speed integrator, that allows the use of a small integrating cap. Long integration time can to a certain degree compensate for a larger cap.

I see a chance that one could get a comparable linearity and comparable (or even lower) noise at low speeds. Leaving out the high speed modes would make things a lot easier. However for conversion times of less than about 1 ms, there are attractive ready made ADC chips. There is no more need to use the same ADC for precision DC / low frequency and the high speed (e.g. true Volts).

The design I am currently planing is kind of similar to the 34401 hardware, but with still a classical rundown phase. If there is no layout caused trouble, I would expect a linearity similar to the 34401 (the first version would be limited by a cheap resistor though) and a considerably lower noise. As the HW is relatively simple it would be at least a good starting point for a few experiments. So far I have a crude layout (with still a few air-wires) and the software still needs debugging and the ASM coding for the adjustment measurements is still missing.

[HalFET]

Mine is currently living upside down on a piece of copper clad 

Mhh, if you sacrifice speed it's indeed doable, but at that point you could also start averaging with highspeed delta-sigma converters.

[Kleinstein]

In my design,  limitation due to the µCs speed are not that severe. It is mainly during the rundown phase, that using software limits the time resolution for the comparator to about 200-400 ns. This kind of adds a little (maybe 5-50 µs) to the length of the rundown phase, but the final step and thus the noise relevant part would be ADC. So chances are still to have a reasonable fast rundown - so far I plan for something in the 100µs range. It will still be possible to use a kind of dual slope mode with 50 µs integration and 100 µs rundown - but this already looses 2/3 of the time to the rundown phase and is thus less attractive.

For the run-up phase it is the integrator hardware that limits the speed, at least with a simple 2 or 3  pattern type feedback. It is only the more complicated feedback modes based on timing that might like to have a faster µc.

So far I use code speed for timing and I am thus limited to ASM programming - this kind of makes it unattractive to do more complicated calculations in the µC at the ADC. So much of the math of scaling the result would be done in the ground referenced part (the PC for the beginning).

Averaging with a higher speed sigma delta ADC does not help with the large range INL and would still keep the small voltage range. If used with some dithering it could help with some odd points, so more like an improvement in DNL.  I would consider the higher speed sigma-delta (or high resolution SAR) converters more like an alternative for the high speed range, like < 100 µs, where the integrating ADC is usually not that good. So I so need to implement a super fast mode for the multi-slope converter. For me the main target would be a 20 ms integration time - the slightly fast range is not that attractive anyway and longer times could use averaging.

[pigrew]

Related to the timing, you can usually use the micro's timer module. For example, I'm currently working on a project to measure timing of pulses, with a resolution of about 15ns (on 8 independent channels), using a Tiva C processor. Of coarse, the micro's internal PLL adds jitter. I think the motor PWM modules may also be advantageous due to their ability to change an output based on an input.

[Kleinstein]

I know one could also use the timer HW in the µC. The problem is however this will add to the response time - it is more like a problem of response time, not so much resolution. The important part is accuracy in the output timing - no high resolution is needed.
The main advantage of a more accurate response to the comparator during the run-down would be with the coarse slope. An error in ending the fast slope would result an an about 10 times (depending on the ratio of the slopes) longer extra time needed for the slow slope, thus an 1 µs error would give an extra 10 µs for the slow slope. The end of the slow slope might show uncertainty due to noise anyway - so the advantage of a faster comparator here is limited. The ADC can still resolve a little more, as the ADC operates at a lower bandwidth than the comparator.  This reduced bandwidth is an advantage of the extra ADC, that comes essentially for free with an µC.

Ignoring other noise sources, resolving 1 µs  (fast run-down) after 20 ms gives 4.5 digits of resolution. With a slope of 1/10 the speed this would be 5.5 digits and with an ADC that can resolve 10 or 100 times finer would be a resolution limit of 6.5 or 7.5 digits after 1 PLC. So this limit should not be a significant limit for a simple, more low cost ADC circuit. Ideally the rundown would need up to about 1.5 periods of the run-up modulation (e.g. 5-50µs) plus something like 10-20 µs for the slow slope and another 10 µs for the ADC sampling.  So chances are still there to have a rather fast rundown phase. A more accurate comparator and timing would really help with a slower slow slope, in case more than 7 digits are needed. For the time being I don't see a problem here.

I am current planing with an AVR (mega48 or similar) at something like a 16 MHz clock. Not having a PLL for the clock could mean I might get away without an extra flip-flop for synchronization. I still have not decided on the type of feedback during run-up. For the first test it will be the simple 2 pattern type because it is about the simplest solution.

[HalFET]

Since I don't really have the current version drawn out I'll just explain my current system. The integration capacitor is a through hole film capacitor standing over the opamp which is feeding it, there's a "low sample rate" flash ADC in parallel with it which feeds directly into the FPGA (Spartan 6 dev board), and two zero crossing detectors. The system clock is 10 MHz from an external Rubidium disciplined TXCO that I still had laying around. Reference is a LM399 feeding the "ADC" through a Caddock ceramic hybrid divider and is buffered/mirrored.

• "Auto-zero" at start of every conversion cycle. (ADC connected to ground) and a quick dual slope conversion
• Select charge resistor based on continuous input monitoring from a separate flash ADC.
  
• Integration for 100 clock cycles
• Based on charge collected (monitored using the flash ADC measuring the capacitor) switch to a known discharge current, goal is to achieve discharge in sub 40 clock cycles.
  
• On zero crossing detect switch to a charge current proportional to remaining charge (since there will be overshoot), and do a run up until next overshoot.
  
• Repeat until remaining charge is sufficiently low.
  

Even with the FPGA running the show and it's asynchronous response "hardware" you still have noticeable overshoot actually. Total conversion time is in the range of 50 microseconds at the moment (at the most), if I push it further I run into limitations with my current FETs for switching, I last stopped at attempting to measure the charge injection caused by different transistors at different voltages but I'll have to change tactic for that since my current results aren't reliable enough.

In short: I get 5.5 digits reliably with the current topology at its full sample rate, and 6.5 depending on the position of the moon and the sample rate.

[MisterDiodes]

...I would suggest you add this to your reading list to see how these projects were done over 37 yrs ago.  Written by Jim Williams for NSC in 1981 (long before NSC being taken over by TI) here's a prototype  inspiration app-note schematic for a discrete 20-bit ADC, dual slope converter that works surprisingly well - and without an FPGA (a slow CPU will still work).  You could probably push this to 21~23 bits with modern components and LTZ Vref.  Notice the tricks to make a fast precision comparator (at A2 and A3):

http://www.ti.com/litv/pdf/snoa597b

Just because it's old doesn't mean the methods don't work today.

Also take a look at Art of Electronics 3rd edition to see a comparison of how a 3456a and 3458a are designed (and how you can use a modest ADC to get great results), and look at what has to change going from 6.5 bits to 8.5 bits.  It is not trivial.

I think the mind-set stumbling block some designers face is only trying to use a single method or ADC chip for a good design solution - sometimes using discretes and multiple approaches is better than a thinking about a single chip (if you've got room).  The most common "gotcha": If you're talking about using diffused resistors on an IC die then the common limiting factor of being useful is the overall noise of the ADC or DAC - it's not the "bits resolution" when you're after long term stability and low noise.  "Real" stable resistors (PWW and some extent foil) will always be less noisy than any resistor on a die - at the expense of much more real estate required.

As far as constructing a DIY 7.5 digit meter:  As a learning tool it will be sort of fun to see how quickly it can become frustrating to find out how reality and noise work - but only as long as you're having a good time along the way.  In terms of just getting a -good- low cost meter you might as well get a used working 3456a for a few hundred $$, or if you can afford it a used working 3458a and be miles ahead in cost and time savings for a 8.5 digit meter.  If you include the cost of building the decent DMM front ends, at low-noise, accurate >>10Gohm input impedance (that itself is a project) - a useful, reliable meter that's accurate and stable at low PPM error won't ever be "dirt cheap".  But certainly it's a fun journey of discovery to find out "why" that is.

[Mickle T.]

This is a cheap and simple DIY 8.5 digit voltmeter I made for fun a few years ago (after the some 7.5 digit ones). Unfortunately, I can only show a draft/cuted version, but I think everything is clear.

[Kleinstein]

...I would suggest you add this to your reading list to see how these projects were done over 37 yrs ago.  Written by Jim Williams for NSC in 1981 (long before NSC being taken over by TI) here's a prototype  inspiration app-note schematic for a discrete 20-bit ADC, dual slope converter that works surprisingly well - and without an FPGA (a slow CPU will still work).  You could probably push this to 21~23 bits with modern components and LTZ Vref.  Notice the tricks to make a fast precision comparator (at A2 and A3):

http://www.ti.com/litv/pdf/snoa597b

Just because it's old doesn't mean the methods don't work today.
....

That old Design is completely different from modern high resolution ADCs in relying on a linear slope for a capacitor to charge at a constant current. So it is really limited by the quality of that cap, that in addition needs to be relatively large. In addition I would expect it to be kind of noise sensitive. AFAIK a similar design is considered in image sensors, using one good slope for simultaneous converting hundreds of signals. It is not even a classical dual slope, more like a variation a of single slope with extra cal cycles.

I totally agree that is will not be cheap to build a DMM - the ADC is just a rather small part, and one point that really needs the experience is to have it work reliable so you can trust the values. While semiconductors got rather cheap, the high quality resistors are still pretty expensive.  I don't think there is much to worry about excess noise from thin film resistors, even at a 8 digit level - especially with the more modern way with more like short integration at a time and averaging afterwards, it is not that sensitive to 1/f noise any more.

The SD chips usually don't use resistors, but switched capacitors. Still they have a limitations due to small charges moving around. This way they also get surprisingly energy efficient.

@HalFET
Getting a 5 digit resolution from a single rundown process is already quite good. An important factor for the high resolution in the multislope converters used in the DMMs is having the signal integration and the counteracting references to be active at the same time. This way they get something like an extra 3 digits before the final rundown.

[HalFET]

Of course it ain't trivial, if it was everyone would be doing it... Especially as hobbyist it's fairly difficult, they spent years working on some of these things with entire teams. For example that design you linked is fine, but if you actually try to implement it you'll see there's a lot more to getting the actual performance out of it. (I tried it myself actually.) Plus just copying someone else's circuit is boring if you're not being paid for it!

But indeed, the entire point of the analog design is getting the noise floor low enough and keeping everything stable, precision components aren't strictly required actually! The clearest example of this can be found in some of the older Keithley circuits, fairly common average components which are easy to source, but they were selected for characteristics that weren't necessarily listed on the datasheet. Additionally the 3458 in some ways is actually a clumsy design if you think about it, the converter ain't that intelligent, they went for specially binned components, ...

But why do people keep thinking they need the LTZ1000 for this? It's an overkill reference for many applications, especially for 6.5 and 7.5 digit meters. It increases your BOM cost while you won't really have any significant gain from it in most cases, since I seriously doubt I'd be able to design something that can do actual 8.5 digit conversions reliably on my own. And most people who think they can do it are probably over-confident (no offence intended to Mickle T. - his design might be able to do it).

@Kleinstein:
Thanks, I was quite proud when it worked! I wonder how those daft bastards at Keysight got it working with a C0G cap though. But the main performance increase actually came from improving the comparator, its what made the multi-slope conversion feasible.

[Echo88]

Very impressive Mickle T!

[Inverted18650]

Following. thank you to all the members contributing. I find myself becoming fascinated with *metrology

[MisterDiodes]

HalFET:  Careful now, don't get too over confident:  Those daft bastards at HP (decades before Keysight) that made that clumsy design - those are my people that I worked with helping build some of their chips.  And the end result is the single most successful and profitable  DMM ever produced.  So in that sense of making money:  they actually came up with a darned good product.  I don't see anything that good from Keysight recently, so you might have a point 

Kleinstein:  Yes that's an old design and I wasn't suggesting anyone rush out to build one - the idea was that those concepts can be improved with newer components, and the design concept serves as a learning tool.  And "yes" you can build one at > 20 bits (we did so for years) and "no" that integrator cap -value- isn't as important as you'd think...but it still must have low DA which is clearly pointed out in the text.  Teflon or Polystyrene will work...maybe polyprop in a pinch.  The design still relies on a low noise Vref.

Clarification: - when I was pointing out be careful resistors on chip scale ADC's and DAC's - I was not referring to those units with thin film (those will be larger resistors, maybe laser trimmed, and usually some sort of sputtered chrome-variant or similar).  I was talking about ADCs/DAC with diffused resistors on board (as in diffused / ion implant / epitax etc.) .  You'll usually find these on ADC's with differential input front ends with PGA and/or scaling resistors - watch out for much higher noise and higher TC than you might want.  Or high resolution DAC's that are fairly dismal for noise.  In those cases using real resistors will get you quite a bit lower noise - at the expense of real estate.  Look at the datasheets for TC / noise and you'll know.  For instance look at <10Hz noise on an AD5791.

It depends on what you're after for performance, and budget of course.  There is no correct answer that fits every need.

MickleT:  Thanks for posting the design concept.  With all due respect I might not call that an "8.5 digit meter" in the sense that I think the original poster might be referring to an actual DMM maybe (That might include an accurate high impedance front end range selection for maybe more useful input voltage measures, maybe a display, etc.) but we get the idea on the ADC section - just using discretes you demonstrated a reasonable  ADC solution!  Neat!

[David Hess]

...I would suggest you add this to your reading list to see how these projects were done over 37 yrs ago.  Written by Jim Williams for NSC in 1981 (long before NSC being taken over by TI) here's a prototype  inspiration app-note schematic for a discrete 20-bit ADC, dual slope converter that works surprisingly well - and without an FPGA (a slow CPU will still work).  You could probably push this to 21~23 bits with modern components and LTZ Vref.  Notice the tricks to make a fast precision comparator (at A2 and A3):

http://www.ti.com/litv/pdf/snoa597b

Just because it's old doesn't mean the methods don't work today.

This design has lessons to teach in what not to do for a precision ADC intended for real world measurements.  It is a single-slope instead of dual-slope converter meaning that it has the following fatal disadvantage:

4. Unlike a dual-slope, this converter has no inherent noise rejection capability. The EX input signal is directly coupled to the comparator input with no filtering. This is a decided disadvantage because most “real world” signals require some smoothing. If a filter was placed at the input substantial time lag due to settling requirements would occur. This is unacceptable because the converter relies on short time intervals between multiplexer states to effectively cancel drift. The solution is to use the microprocessor to filter the signal digitally, using averaging techniques.

Its input integration time is variable and depends on signal level so it has no normal mode rejection to remove power line interference.  This will limit its resolution to 5.5 to 6.5 digits or less (based on various modern meters operating under the same constraint) except in specialized instrumentation applications where power line interference is not a consideration.  I suspect National used it for automatic test equipment in a very controlled environment or maybe one of their customers did.

[David Hess]

I wonder how those daft bastards at Keysight got it working with a C0G cap though. But the main performance increase actually came from improving the comparator, its what made the multi-slope conversion feasible.

Some C0G/NP0 capacitors are pretty good as I discovered designing sample and holds.  I was surprised when I ran across old run-up dual-slope converter designs which used silver mica capacitors.  After that, I wondered why anybody was using dual-slope converters with picky capacitors at all.  Maybe nobody could understand how the run-up dual-slope converters worked because application notes from Siliconix were so poor; I am not convinced now that even they understood them.

[MisterDiodes]

... I suspect National used it for automatic test equipment in a very controlled environment or maybe one of their customers did.

Yup - Like when you have to measure 60Hz signals and -can't- filter out power line freq....because that's the signal.  That turned out to be a real application.  One customer being HP.... 

... and like I said app note is a teaching tool - -not- - a finished schematic.  Of course Dual Slope methods can result in lower noise - and how do you think you'd modify this concept circuit? A Dual slope strategy would be the next logical step in trimming down noise.

[David Hess]

... I suspect National used it for automatic test equipment in a very controlled environment or maybe one of their customers did.

Yup - Like when you have to measure 60Hz signals and -can't- filter out power line freq....because that's the signal.  That turned out to be a real application.  One customer being HP.... 

Then you either add a precision sampler or rectify the AC before measurement.  More recent multimeters going back to at least sometime in the 1990s are apparently using precision samplers for AC measurements which is nice because you get free AC RMS and AC+DC RMS with that.

But if normal mode rejection of power line interference was not a problem, then instrumentation ADCs would not routinely and deliberately include sin(x)/x response which notches power line interference out.  Nobody would use dual-slope ADCs if single-slope ADCs could be used instead.

... and like I said app note is a teaching tool - -not- - a finished schematic.  Of course Dual Slope methods can result in lower noise - and how do you think you'd modify this concept circuit? A Dual slope strategy would be the next logical step in trimming down noise.

I would modify the single-slope circuit by turning it into a run-up dual-slope circuit with an input integration time of a whole number of power line cycles.  From there it depends on how much complexity I would accept in the quest for performance but I would see how far a simple design can be taken with automatic calibration and precision linear parts before duplicated what HP did.

[Kleinstein]

I wonder how those daft bastards at Keysight got it working with a C0G cap though. But the main performance increase actually came from improving the comparator, its what made the multi-slope conversion feasible.

Some C0G/NP0 capacitors are pretty good as I discovered designing sample and holds.  I was surprised when I ran across old run-up dual-slope converter designs which used silver mica capacitors.  After that, I wondered why anybody was using dual-slope converters with picky capacitors at all.  Maybe nobody could understand how the run-up dual-slope converters worked because application notes from Siliconix were so poor; I am not convinced now that even they understood them.

C0G/NPO caps can be pretty good - about the quality of high quality film caps (e.g. PP or polystyrene), but much easier to solder in SMT. So they are an obvious choice today, if you don't need a very large cap, like in the slow dual slope designs (e.g. ICL7106).  In an dual slope converter DA of the cap will cause some INL and gain error (as DA can be temperature dependent this would include some drift). To a lesser extent in a multi-slope converter DA can also cause some INL errors - though considerably less as normally the cap is much smaller and the mean voltage at the cap is small.  My guess is that much of the INL of the ADCMT 7480T (see parallel thread)  and similar 6581 is due to DA in the rather large integration cap.

The plan shown by Mickle T. looks nice - like a more modern and improved version of the solartron design. I am just a little surprised it used extra HW counters instead of the input capture function of the µC - this could have simplified the digital HW a bit.  It is definitely a way to get high resolution, good INL with a moderate effort.

[David Hess]

To a lesser extent in a multi-slope converter DA can also cause some INL errors - though considerably less as normally the cap is much smaller and the mean voltage at the cap is small.  My guess is that much of the INL of the ADCMT 7480T (see parallel thread)  and similar 6581 is due to DA in the rather large integration cap.

The run-up dual-slope converter drives a lot more charge through the capacitor making it seem much larger than it really is.  So the error from dielectric absorption is distributed over a much larger amount of charge producing a smaller error.  Offsetting this is charge injection from all of the extra switching but if balanced out, then this produces an offset error which is calibrated out.

The plan shown by Mickle T. looks nice - like a more modern and improved version of the solartron design. I am just a little surprised it used extra HW counters instead of the input capture function of the µC - this could have simplified the digital HW a bit.  It is definitely a way to get high resolution, good INL with a moderate effort.

I would have to do the math to be sure but an external synchronizer might be necessary to limit measurement error due to jitter.

[Kleinstein]

The plan shown by Mickle T. looks nice - like a more modern and improved version of the solartron design. I am just a little surprised it used extra HW counters instead of the input capture function of the µC - this could have simplified the digital HW a bit.  It is definitely a way to get high resolution, good INL with a moderate effort.

I would have to do the math to be sure but an external synchronizer might be necessary to limit measurement error due to jitter.

There is a synchronizer (e.g. the 2 flip-flops U30A/B) behind the comparator.  Behind that it is in sync with the µC clock and could thus be sampled with the µc's ICP function, with no more extra jitter. One just needs to be sure the phase of the clock is not just at the wrong point.

For jitter reasons I would prefer a canned oscillator.

Besides the modernization of the HW, there could also be the option to modify the software side a little. AFAIK the solartron uses only sampling at the start and end of the integration time. With a little more processing power it is possible to look at a few more transitions at the beginning an end. Averaging could reduce noise a little, at the cost of a small change in frequency response (might even be better this way) and only slightly increased time (e.g. a few periods of the forcing signal). With averaging it might be attractive to use a slightly faster forcing signal.

The full ADC with a +-xx V range would need a FB from the positive reference too and will get quite sensitive to the ref. inversion (R4/R5). The solartron uses a very higher quality resistor at this position for a good reason. A capacitive ref. inversion might be an alternative.

[David Hess]

The plan shown by Mickle T. looks nice - like a more modern and improved version of the solartron design. I am just a little surprised it used extra HW counters instead of the input capture function of the µC - this could have simplified the digital HW a bit.  It is definitely a way to get high resolution, good INL with a moderate effort.

I would have to do the math to be sure but an external synchronizer might be necessary to limit measurement error due to jitter.

There is a synchronizer (e.g. the 2 flip-flops U30A/B) behind the comparator.  Behind that it is in sync with the µC clock and could thus be sampled with the µc's ICP function, with no more extra jitter. One just needs to be sure the phase of the clock is not just at the wrong point.

I am just pointing out why I might not rely on only the input capture function of the microcontroller or an FPGA for that matter.

For jitter reasons I would prefer a canned oscillator.

I would prefer a discrete oscillator.

The full ADC with a +-xx V range would need a FB from the positive reference too and will get quite sensitive to the ref. inversion (R4/R5). The solartron uses a very higher quality resistor at this position for a good reason. A capacitive ref. inversion might be an alternative.

I have been considering whether capacitive multiplication and division might also be good for linearity calibration.  Don't some of the Keithley meters do this?

[Theboel]

@ David Heiss
I would prefer a discrete oscillator.

could you more detail about this
Thank You
Anton

[Kleinstein]

Some meters use capacitive multiplication / dividers. I know of the Datron 1281, the Keithley 2002 (but not sure if used for ohms only) and a kind of odd way in the K2001. The reference part of the K2001 deserves a few  .

The main advantage of the charge pump type divider it that it is stable, but it does not give an absolute accurate 1:2 division due to parasitic capacitance and charge injection. So it can can not be used for INL cal by assuming it will produce exactly half or twice the voltage. However it could be a good solution to get a precise negative reference for the ADC. The other possible use would be to get a long time stable 1.75 V (7 V / 4)  to do an gain adjustment for a 2 V range.

For the integrating ADC with charge balancing, the negative reference needs to be precise, as drift in the reference would transfer to DC drift and gain drift. However it is usually possible to do a measurement for adjustment of the absolute value so that the negative reference does not need to be accurate or long term stable. So the charge pump type inversion would be definitely an option. This is especially true for the type of ADC Mickle showed, that is slow in doing an offset drift compensation.

[David Hess]

@ David Heiss
I would prefer a discrete oscillator.

could you more detail about this

I mean for reliability, cost, and performance reasons, I would rather use a discrete transistor crystal oscillator than a hybrid or integrated oscillator unless the application is not critical or the cost is not important.

[Kleinstein]

A discrete transistor crystal oscillator might get better ultimate performance, if made right and well shielded. However the canned crystal oscillators are relatively cheap (e.g. $1-2 range) and already shielded and seem to be sufficient - many DMMs use just such oscillators.

An important point can be a good supply decoupling with the oscillator, as the oscillator could react to supply variations and also can be a significant source for RF emissions. So an extra ferrite in the supply line is likely a good idea.

[MisterDiodes]

Another way:  if you're going to chase ppm, just go big and OWN it:  Throw on your Rubidium GPSDO and call that "pretty darn good" for clean, low drift timing.

Barring that, like Kleinstein noted: We use good quality shielded canned oscillators (a few $$ each unheated, or perhaps $30~$60 for OCXO, stability down to ppb) on thousands of industrial boards, and we've never had to replace one.  They can work very well, and we've never seen any reliability issue.  Handy tip:  Look at the low temp range and stick to the units -guaranteed- to start at -40°C.  Then test some samples to make sure they weren't making that part up.  The lesser quality units will have real trouble with a cold start.

[floobydust]

For the integrator switches, I see discrete JFETs or MOSFETS or CMOS switch IC's used.
Is this just a wild datasheet hunt for low charge injection with reasonable cost? I wasn't sure of each ones merits. In other applications, switch leakage current verses temperature was an issue I ran into.

74HC4053 (34401A)
VN0605T (K2000)
DG411 family

[Andreas]

Hello,

I throw in the MAX4053A for low charge injection, leakage current and flat on resistance over voltage.
But works only for +/-8V. (similar to the HC, but for the HC-device you will need level shifters).

See also comparison of INL (in mV) for a  0-5V PWM based calibrator.

with best regards

Andreas

[Kleinstein]

There are many options for the switching. Usually the more important switches are those for the reference current(s). So in the Keithley 2000 and 2002 these are SD5400 mosfets. The choice of the switch also depends on where you are switching:

The switch at the integrator side of the resistor is likely more sensitive to charge injection, but have the advantage of operating all at the same voltage level (near ground). The switches also only have to work at a low voltage (this is why the 74HC4053 is possible even with  a +-10 V reference.

The switches at the reference side should be less critical with charge injection, but have to work with a higher voltage (e.g. the full +- ref voltage), but the switches at the high and low side work at a different voltage level. This makes matching of the on resistance more difficult. So the tendency is to use lower resistance switches in this case.

Finding a good switch is more than just a datasheet hunt - there are additional parameters important usually not found in the datasheets. Another problem is that with parameters like leakage current the spread from typical parameters to tested limits is often very large.
An important parameter can be the speed of switching: the more often the switches are operated, the more important jitter gets. So variants with fast switching, like the 34401 need low jitter levels (preferably below 100 ps). Low jitter usually is easier with faster switches. Even the rather slow modulating Solatrons and the circuit shown by Mickle T below take quite some effort for fast switching of the gates.

In principle JFETs make very good switches with low leakage, but I have a slight problem in switching them fast. Also the choice of p channel Jfets is very limited and the on resistance is kind of high. So they are mainly an option for switching at the integrator level.

CMOS switches integrate MOSFET switches with gate drivers.  The extra P-MOSFET part may not be needed and add some extra charge injection, but could also do some compensation of the charge injection. Using separate MOSFETs like the Keithley meters (2000,2002) do might get slightly better parameters, but the extra circuit can also add capacitive coupling and supply noise.

The Keithley 2002 and what it looks like the ADvantest/Japanese T6481 use current sources instead of just resistors for the reference. This kind of eliminates the on-resistance (any might this way allow for very small switches) of the reference switch and thus needs a low on_resistance switch for the signal path, as there is no more compensation.

In the old times there where also meters that used diode current steering (HP3455) and just 4000 series CMOS gates powered by the reference.

My personal favorite for switching at the integrator side is the 74HC4053 or as a possible upgrade option the ADG633. They are very simple to use and low voltage MOSFETs do have a good value for the figure of merit R_on * C_gate. Despite there really low price they could be still good performance. The low price of the HC4053 comes at the price of less testing - so one might have to do extra leakage testing. The 34401 shows that those switches seem to work quite well, even in a scheme with very frequent switching, where charge injection and jitter might be critical.
Having 3 SPDT switches in one chip is also nice, as it helps with compensation of the on resistance.

[David Hess]

It is too bad that small signal 4 lead MOSFETs are not more common.  I wonder what the pricing and availability of the ones from Linear Systems are.  Their web site is horrible and the purchase links are broken.

FETs can often be paired up to cancel charge injection, leakage, and on resistance; I know some of the HP designs do this.

My first choice would be current switching using diodes (actually diode connected transistors) if feasible.  My last choice would be integrated analog switches.  Complex level shifting is something I would just accept in a high performance design.

[zhtoor]

It is too bad that small signal 4 lead MOSFETs are not more common.  I wonder what the pricing and availability of the ones from Linear Systems are.  Their web site is horrible and the purchase links are broken.

hello,

check here.

https://shop.micross.com/shop-default.aspx

-zia

[MisterDiodes]

It is too bad that small signal 4 lead MOSFETs are not more common.  I wonder what the pricing and availability of the ones from Linear Systems are.  Their web site is horrible and the purchase links are broken.

We always order direct from Linear Systems without any problem, and generally they have several hundred of each part number on hand.  If you need more than that the lead time is usually just a few weeks.  At least when we've ordered, they don't seem to have a problem selling just a few or a few hundred of any part number.  Order on Monday, parts in hand by Weds.  Great service and good tech support.

They supply parts in SMT all the way to shielded TH cans.  That's nice to have a choice. 

They don't offer much of a pricing discount to distributors so might as well go right to the source. There's not a lot of profit incentive for distributors to stock these parts, and most distributors haven't got a clue of what they're selling in the first place.

What a lot of people don't realize is that LS will also custom characterize parts for you (at added cost of course and MOQ) - that's a great service if you're running a critical project.

Their fet  switches work very well - and depending on what you're building you can control / compensate for charge injection on your matched switch pairs.  Also watch your dV/dt on your gate signals, and don't over-drive the gates!.

[Inverted18650]

FETs can often be paired up to cancel charge injection, leakage, and on resistance; I know some of the HP designs do this.

David,

Can you recommend app note or other resource on charge injection?

thank you

[HalFET]

FETs can often be paired up to cancel charge injection, leakage, and on resistance; I know some of the HP designs do this.

David,

Can you recommend app note or other resource on charge injection?

thank you

If you have "The Art of Electronics" it's mentioned in there a few times, though I wouldn't really know where to find much about it in detail in one spot. Most of what I've learned about measuring it comes from academic papers on IEEEXplorer.

[David Hess]

FETs can often be paired up to cancel charge injection, leakage, and on resistance; I know some of the HP designs do this.

David,

Can you recommend app note or other resource on charge injection?

thank you

Usually I see the subject of charge injection come up with sample and hold circuits, even diode based ones, which have various ways to counteract it but I do not have any references which are more generic than that.

[MisterDiodes]

...Can you recommend app note or other resource on charge injection?

Besides Art of Electronics, other relevant books you might find helpful are Circuit Designer's Companion, and Designing with Analog Switches (Older but still applies).  Take a look at how MUX508 / 509 parts work from TI (and AD508G from ADI, etc.).  Then take a look at the DMOS switches from Linear Systems.  LS makes a lot of of the excellent parts from Intersil, Siliconix, etc. (when those companies got dissolved or bought out, LS took over the fet and some of the BJT parts) , and then LS made new and improved parts along the way.  A lot of designers don't even realize the value of these parts anymore, but they can be extremely useful in precision analog designs:

http://linearsystems.com/lsdata/others/DMOSAnalogSwitchIntroduction.pdf

If you aren't aware, the founder of Linear Integrated Systems was John Hall - who was also a co-founder of Intersil.  He knew what he was doing when it came to building performance FETs.

Notice that if you're looking at datasheets or app notes from Vishay or ON Semi, they are probably warmed over versions from the 70's thru 90's from Siliconix, Fairchild and sometimes Motorola sheets will pop up.  Etc.  These were the big players.

After that, look at older test equipment designs, and then by all means get your hands dirty testing your own circuits and make some discoveries - best way to learn.

Here's some inspiration on how to measure charge injection for yourself - see figure 4:

http://www.vishay.com/docs/70606/70606.pdf

HINT: You can't get rid of charge injection completely, but you can do a good job canceling (at least some of) the effects out if you're careful. 




 

[HalFET]

I'd say http://www.analog.com/en/analog-dialogue/articles/ask-the-applications-engineer-26.html explains it slightly better.

[floobydust]

That Analog Devices note left me a bit sceptical. Their approach is to add dummy capacitance to match the NMOS to PMOS parasitics. Only works if the source is grounded.

ADG1211,1212,1213 datasheet claiming "0pC" charge injection. The "iCMOS" is industrial HV 33V process.

I do like the DMOS parts such as SD5400. I haven't seen anything with such low capacitance and high speed. Price is reasonable, compared to quad JFETs.

[HalFET]

That Analog Devices note left me a bit sceptical. Their approach is to add dummy capacitance to match the NMOS to PMOS parasitics. Only works if the source is grounded.

ADG1211,1212,1213 datasheet claiming "0pC" charge injection. The "iCMOS" is industrial HV 33V process.

I do like the DMOS parts such as SD5400. I haven't seen anything with such low capacitance and high speed. Price is reasonable, compared to quad JFETs.

It makes sense though, I wouldn't be amazed if half the "proprietary charge injection reduction" techniques are actually just adding that capacitor there.

[zhtoor]

how about using H11F1 style opto-mos switches to avoid charge injection?

like the one with attached datasheet.

regards.

-zia

[David Hess]

how about using H11F1 style opto-mos switches to avoid charge injection?

Some designs use them but they are expensive and slow.

[Kleinstein]

The switches for switching the reference currents need to be low jitter which usually means they have to be relatively fast. The opto-mos are rather slow, so it would get difficult to get them to below ns jitter.  The direct effect of charge injection is an added offset that would not be a real problem. It is only the variations in charge injection (with temperature, time or voltage) that causes trouble.

There are D-MOS chips with integrated driver available, like DG613. They could be a good candidate too (for switching at the integrator).

The HP34401 shows that even the cheap 74HC4053 works reasonably well, even with frequent switching. Frequent switching makes the ADC more sensitive to the switch properties. It is used to allow good performance for short integration times too - it's less important for long integration time. The overall ADC construction in the 34401 is not made for low noise: It starts with dividing the input signal by 3  , and the second limiting point is that the limited resolution ADC in the µC is used on the fly with a rather steep ramp. A third weak point is the rather high current noise of the OP27.  So I don't think the performance of the 34401 is limited by the switches. Reducing the switching frequency could reduce the importance of the switches if needed - at the cost of slightly limited performance at very short integration time (e.g. < 5 ms).

[pigrew]

This discussion about using an ADC has made me wonder if the comparator could be completely removed, and if that would be a good idea. My idea is to use an ADC to measure the integrator output, and set the run up/down time based on the integrator output voltage to slightly overshoot zero. This should reduce jitter from the comparator/edge time capture circuits.

Thoughts? Or is this a standard technique?

[lukier]

This discussion about using an ADC has made me wonder if the comparator could be completely removed, and if that would be a good idea. My idea is to use an ADC to measure the integrator output, and set the run up/down time based on the integrator output voltage to slightly overshoot zero. This should reduce jitter from the comparator/edge time capture circuits.

Thoughts? Or is this a standard technique?

34410/34411A and descendants (34465A etc) use this architecture. High res ADC for the residual, low-res high speed ADC (80 MSPS AFAIR) instead of a comparator.

Also, it has some PWM based DAC feeding of the reference currents that I don't fully understand.

More details here:
https://www.google.co.uk/patents/US7176819
https://www.google.ch/patents/US6876241

[RandallMcRee]

OK, back to trying to build a, ahem, modern 7.5 digit voltmeter.

My idea (not claiming originality, just not sure who else to blame) is to use a precision dac to come close to the unknown input voltage and then use a 24 or 32 bit ADC to measure the residual. The DAC vref input would be a precision 10V source like a KX/Px/Rx/ LTZ1000. This vref would also, in 5v form, used for the ADC.

I see that our own TiN has investigated the ADS1262 here:
https://xdevs.com/review/ti_ads1262_p1/

In particular, he measured the zero voltage for ADS1262 and came up with this table (attached png), which I found encouraging. It seems that an ADC like the ADS1262 (or AD7177-2?) would be good for the task mentioned above--measuring the differential between the DAC and input voltage.

If the DAC is 10 bits and the ADC ENOB is, say, 22 bits then it would seem that we could get to 7.5 digit precision. There are a lot of details, of course, that need to be correct.

Using the LTC2400 for the ADC would require one of the circuits here in AN78 http://cds.linear.com/docs/en/application-note/an78fs.pdf

Thoughts on this approach?

[David Hess]

Where are you going to get a 10 bit DAC which is linear to 24 bits?

[RandallMcRee]

Where are you going to get a 10 bit DAC which is linear to 24 bits?

Uh, I'm going to make one?

But really--10 bits is only 1024 points. I think we could, as a calibration step, input the known voltages for each and every one measured using a 3458a. (It's modern so a microcontroller is obviously tying things together). Then linearity would not be an issue, right? Temperature dependence would be the big variable, I guess.

I am actually constructing a 10bit dac using S102K resistors, to see what issues arise. Its like a hamon divider, but binary.

[e61_phil]

I build some something like that (AD5791BRUZ with LTZ1000A + LTC2410 with LTC6655) for High Voltage drift measurements. It works really nice and stable. The INL is limited by the AD5791 of course, but still very good. If you build your own DAC it could be very interesting.

[Magnificent Bastard]

Where are you going to get a 10 bit DAC which is linear to 24 bits?

The only way that I have been able to do it in the past is a PWM DAC-- made very similar to the Keysight patent above ^^^^ , but not with the high-speed op-amps.  I used a different scheme to remove the switch resistance variation.  I've been able to get 1ns edges, with very small TC (0.007ppm/K).  0.1ppm to 0.02ppm INL is possible in practice, depending on how much money you want to spend on it.  I had no idea that Keysight patented this idea-- I was using it years before they filed; and I thought that it would not have passed the new "non-obviousness" rules...

[Kleinstein]

Super high precision resistors and PWM are not the only options to get a very stable DAC. Another option would be an AC divider with a special precision transformers and synchronous rectification. However high quality PWM is a kind of obvious way.

Depending on the quality of the ADC chip used, one might not even need 10 Bits for the voltage to subtract. There may be also the possibility to use the ADC chip to check the linearity of the coarse DAC. So even if the DAC is not that linear, one could in principle use a numerical correction, as long as the DAC is stable.

For just 7.5 digits of resolution one does not really need super fast OPs in the integrator like in the HP3458. The Keithley 2000,2001 and HP34401 and also the R6581 use rather normal speed OPs (e.g. 4-8 MHz) GBW for the integrators.
For a DIY solution one would not go the way of the 3446x with two auxiliary ADCs - this is mainly used to get good performance at fast sampling rates (e.g. 10000 SPS). This can be important for use in automated test  systems, but of not much use for reading from the display. When it comes to fast readings at moderate resolutions there are ready made chips as an option - though some are expensive.

[DarkLight]

If the DAC is 10 bits and the ADC ENOB is, say, 22 bits then it would seem that we could get to 7.5 digit precision. There are a lot of details, of course, that need to be correct.

I worked with LTC2400 years ago but never get ENOB above 19.5 bits. 

What has happened to this post?

[RandallMcRee]

If the DAC is 10 bits and the ADC ENOB is, say, 22 bits then it would seem that we could get to 7.5 digit precision. There are a lot of details, of course, that need to be correct.

I worked with LTC2400 for couple of months but never get ENOB above 19.5 bits. 

What has happened to this post?

Nothing! Hey you are reviving it. Although I'm not the OP here I *am* still working on this idea. I feel like a different person posted the stuff above--is there some other Randall McRee? No, I think it more likely that is just a feeling.

So, what I *think* I have learned so far, in no particular order:

Yes, a linear PWM is do-able and I built one that I think will do the job (another thread for that, also moribund)
This is called a differential voltmeter, e.g. Fluke 895, but modernized,
An adc with high linearity and ENOB of 19 bits ought to get you in the 7.5 digit ballpark (overall bits ~ 10+19 = 29)
The devil is in the details; all of those ppm error sources add up so...the devil.

What I am working on now is a 10volt source based on several PX ref LTZ1000 boards.

I acquired a calibrated Keithley 2001 to test all this out. So, yeah, still coming along for me....

Anyone else make any progress? How did you achieve the 19.5 ENOB? How did you verify that?

Irony note: not lost on me that I bought a 7.5 digit meter on the way to making a 7.5 digit meter. Make of that what you will. I try not to judge.

Randall

[TiN]

(overall bits ~ 10+19 = 29)

Somebody got dreaming and carried away, sorry. 32-bit SD ADCs provide ~22-23 ENOB, nothing like "29".
Even if you get magical ADC or DAC with that level of linearity, total system would be limited by lot of other errors to much lower value.

Anyone else make any progress? How did you achieve the 19.5 ENOB? How did you verify that?

You need more linear source, like ramp generator or slow high fidelity sine, or another much better ADC  Or best commercial "DAC" in the world, like Fluke 720A.

Irony note: not lost on me that I bought a 7.5 digit meter on the way to making a 7.5 digit meter. Make of that what you will. I try not to judge.

Mhm, its all downhill since. I wanted to build DIY calibrator, and now I essentially ended up of buying one (second one actually). 

[RandallMcRee]

TiN says

Somebody got dreaming and carried away, sorry. 32-bit SD ADCs provide ~22-23 ENOB, nothing like "29".
Even if you get magical ADC or DAC with that level of linearity, total system would be limited by lot of other errors to much lower value.

Where would we be without our dreams?!
Linear Technology seems to share part of my dream....according to Circuit 1 in AN-78 we have the following table (below).

The nonlinearity is listed as 1+4 = 5 ppm. That is a non-correctable error. So a lower level. If we can control other errors I bet that we will be in the >24 bit range. (Proposal is that Circuit 1 takes the output from the PWM Dac and subtracts the unknown voltage, and presents it to the LTC2400).

AN-78 does not give much detail about how they measured that nonlinearity. It might be the case that those numbers are only true with small common-mode voltages. But I think its worth a shot.

[TiN]

And how exactly did you determine 5ppm INL is ">24 bit range" ? This part does not align with me well

AN86 Appendix C does give enough details on ppm-level INL measurement. Somebody here at EEVBlog bought that very same LTZ reference from the appnote.

[David Hess]

The nonlinearity is listed as 1+4 = 5 ppm. That is a non-correctable error.

The repeatable parabolic INL curve of the LTC2400 can be partially cancelled digitally.

[try]

Hi Tin,

And how exactly did you determine 5ppm INL is ">24 bit range" ? This part does not align with me well

AN86 Appendix C does give enough details on ppm-level INL measurement. Somebody here at EEVBlog bought that very same LTZ reference from the appnote.

That was branadic.

Here is a project that deals with setting up  a measuring and controling system:

https://www.heise.de/ct/projekte/machmit/ctlab/wiki

One of the instruments involved is a DMM that measures voltage and current in DC and AC:

https://www.heise.de/ct/artikel/Messwerkeln-291398.html

This is a project where Andreas got some ideas from.

There are a lot of easy improvements possible to make the device more stable.
I built two of them.

Stop talking and start trying.

Regards
try

[Kleinstein]

Testing the INL is indeed tricky. The AN86 way is nice, but takes quite some instruments - so not a real option for many of us. A full test at all codes is not realistic in the 24 Bit range anyway - it's just not enough time for 10s of millions of test points. There are a few simpler spot tests. Still INL testing is a topic on it's own.

The SD ADCs are not that bad, but they still have a few limitations:
One is that INL is limited to a few ppm's. The LTC2400 is rather good in this respect, but limited to a one polarity. Such an ADC might still be good for an extra test though.
The other limitation is the voltage range, that usually is rather small, so more like +-2 V and +-5 V at best (some Ti converters).
This also applies to the reference - so the 7 V zener reference would need a divider. This makes the long term stability task a little more tricky.
The noise may not be the largest problem. The LTC2400 is not that good here, but something like the LTC2440 is already low noise - though higher INL. The lower noise ADCs tend to use some tricks to lower the noise at the costs of higher INL. Also input buffering can be tricky. Ready made ADC chips are used in the 5 digit and a few (often more lower end) 6 digit meters for a reason.

I am still looking at a more classical multi-slope ADC. Just got some delays. In addition I hoped to learn more from the 6581T "repair" thread  - though there was not that much success, but still some hints and useful thoughts.
So far noise seems to be the least problem . Under good conditions (short and thus no reference noise) I get up to 24 ENOB (500 nV Allan deviation at 20 ms in a +-5 V range), with still some potential to improve on it (higher voltage range, better OP). The difficulty is more like getting a good INL (and test it) and to get good stability (e.g. low drift). It starts with the point that a simple buffer with an OP27 might not be linear enough.

Another point is finding a suitable input stage: the simple 1 stage amplifier and switching used in the HP meters like 3456, 3458 might have quite some input bias if used with a 1 PLC AZ mode - at least it gets challenging to make the input low bias. One point learned from the 6581T is that switching the input is not that easy. So I currently favor a 2 stage design like in the Keithley 200x.
For a SD-ADC based DVM, I would consider is different input configuration that takes advantage of usually having a differential input. 

[Andreas]

INL adjustment on a LTC2400 is rather easy.
All you need is
- a stable reference (LM399#3 in the cardbox in the background)
- a (short time) temperature stable resistor string (right) (here with 0.1% 25 ppm/K resistors amplified up to 10V)
- a (high impedant) buffer amplifier (in the middle)
- a LTC2400 (left)
- a plastic pincer (blue) (to avoid thermal voltages when changeing the resistor taps)

you simply have to rely on the fact that the lower part and the upper part of the resistor string give the total resistor string voltage.
And at the LTC2400 you can model a parabolic curve for the INL which makes it even more easy.

For measuring of voltages larger than 5V I use additionally a LTC1043 precision divider.
So usually I make 2 measurements for the INL: one with LTC1043 (buffered on both sides) and one without LTC1043.

with best regards

Andreas

[hwj-d]

Stop talking and start trying.

Certainly, that's not to TiN ...   
(edit, he always tries everything)

[DarkLight]

Anyone else make any progress? How did you achieve the 19.5 ENOB? How did you verify that?

I achieved the 19.5 by using LT1236A, separated battery power supply  and a lot of try and error and verify it using Arduino and some equations to calculate ENOB . Here I attached the schematic.
I have also uploaded a video on youtube, but the video was recorded when I got 18.5 Enob.  https://goo.gl/6C9bWf

[Gyro]

INL adjustment on a LTC2400 is rather easy.
All you need is
- a stable reference (LM399#3 in the cardbox in the background)
- a (short time) temperature stable resistor string (right) (here with 0.1% 25 ppm/K resistors amplified up to 10V)
- a (high impedant) buffer amplifier (in the middle)
- a LTC2400 (left)
- a plastic pincer (blue) (to avoid thermal voltages when changeing the resistor taps)

you simply have to rely on the fact that the lower part and the upper part of the resistor string give the total resistor string voltage.
And at the LTC2400 you can model a parabolic curve for the INL which makes it even more easy.

For measuring of voltages larger than 5V I use additionally a LTC1043 precision divider.
So usually I make 2 measurements for the INL: one with LTC1043 (buffered on both sides) and one without LTC1043.

with best regards

Andreas

Just for my curiosity, but why would you implement an LTC2400 setup with single ground pin shared by input, reference, supply current and digital interface returns, when you could use an LTC2410 with differential input and reference, multiple ground pins etc.

The LTC2410 is actually cheaper than the 2400 (~£7.60 vs £9.70) from RS in the UK, not sure about other places. In fact why did LT bother to make the LTC2400? It just seems way too much of a compromise to squeeze a 24 bit ADC into such a low pin count SO8 package.

As I say, really just for my curiosity, not a criticism.

[hwj-d]

Then I would probably prefer an ADS1256.

[David Hess]

It starts with the point that a simple buffer with an OP27 might not be linear enough.

This is probably nothing new to you Kleinstein but I will post for others who might not be as familiar with precision design.  There are various things which should be done or at least avoided to improve the linearity of a precision operational amplifier:

1. Watch out for the temperature coefficient of resistance of the feedback network.  When configured for gain, the difference in heating of the input and feedback resistors can change the gain enough to matter at different output voltages.  This conflicts with point 3 below if a high impedance divider is used.

2. Unload the operational amplifier's output to prevent self heating.  Thermal feedback from the output transistors to the input transistors limits open loop gain among other things.

3. Watch out for non-linear changes in input bias current with common mode voltage. This is especially bad with some FET input operational amplifiers.  This conflicts with point 1 above if a low impedance feedback divider is used.

4. Errors due to limited common mode rejection can be lowered by using chopper stabilization or bootstrapping.  Both are common in the best bench voltmeters.

Weren't early OP-07s (and OP-05s?) known for low open loop gain yielding poor linearity?

There are some test circuits which can be used to measure and display the non-linearity of an operational amplifier for evaluation:

http://www.ti.com/lit/an/snaa047a/snaa047a.pdf
http://www.introni.it/pdf/Bob%20Pease%20Lab%20Notes%20Part%207.pdf
http://application-notes.digchip.com/006/6-8872.pdf
http://www.ti.com/lit/an/snoa737/snoa737.pdf

[Andreas]

As I say, really just for my curiosity, not a criticism.

The answer is already here:

https://www.eevblog.com/forum/metrology/7-5digit-diy-voltmeter/msg1395104/#msg1395104

The main advantages are the overrange (how do you adjust zero and full scale with a ADC that clips hard the values at zero or full scale), the very low T.C. and a predictable INL.

with best regards

Andreas

[Gyro]

Many thanks Andreas,

I hadn't spotted the extended underrange / overrange conversion capability on the LTC2400. Without going through the datasheets in detail, I had assumed that the 2400 and 2410 might be different bond-out versions of the same die, obviously not. It's a shame they didn't include it on the 2410 for ground referred input and reference inputs.

Thanks,

Chris

[e61_phil]

The 2410 is a "real" differential ADC. The -IN shouldn't be tied to ground. Therefore, the 2410 has even more "underrange" than the 2400 and you can easily measure zero.

For example: In a 5V system you can tie -IN to 2.5V. The +IN can now move from 0V (-Vref/2) to 5V (+Vref/2).

The INL specification from the 2410 is better than the spec of the 2400. But I don't know what that mean in practice.

[Kleinstein]

For the differential SD ADCs the INL and other specs tend to be for a true differential signal: the negative input being close the to inverted version of the positive input. So having one input tied to a fixed voltage can increase the INL error. In addition it might limit the range (can be relevant with the ADC1256). For a DVM circuit measuring an isolated voltage it is possible to get this by having the common terminal not tied to ground or a fixed level, but to the negative ADC input and drive this to the inverted positive input.

The LTC2400 INL is mainly a simple square contribution that could be compensated for, at least to a large part. So there is a reasonable way to reduce the INL.  For the LTC2410 the shape is more complicated and thus compensation more difficult.

[Andreas]

Hello Phil,

yes of course.

But you have to pay attention that the 2.5V are
- stable (so not to spoil the ADC specs for offset and full scale drift).
- slightly higher than 2.5V (otherwise you cannot reach the 0V and the 5V end values)

Unfortunately a LTC1043 divider delivers usually slightly lower than 2:1 ratio.

with best regards

Andreas

[Echo88]

Since this is a fitting thread for some questions, i ask them here:

Are there any reliable/proven infos on the long term stability (at least capacitors age) of the LTC1043 if used as a voltage divider/multiplier, for example to generate  7.2V / 3 * 2 = 4.8V as reference for a LTC2400?
Are there any very low INL and >= 24Bit-ADC-modules like the Thaler ADC180 or the PREMA 5610E which can be bought at the moment from normal persons? Maybe some guy already rolled their own Multi-Slope-ADC as Open Source and i didnt find it?
Can the INL of every ADC reliable be corrected (suppose ADC is in oven, temperature variation not relevant) or does it drift with time?

[Kleinstein]

The error of the LTC1043 or similar charge pump divider is rather small and constant over time. It does not depend very much on the drift of the capacitors it is more like parasitic capacitance and charge injection that give a small error. So this would not be the largest point to worry about.

There are a few ADC chips with low noise (e.g. LTC2440, LTC2368-24 ) - for some there are evaluation board available. With sufficient averaging one can get >24 bits ENOB for rates reasonable for a DMM.

Correction of the INL is difficult in general. It can be possible / practical for a smooth function type like with the LTC2400, where there is an extra x² or x³ contribution, but not very practical with a more complicated function like with many of the faster SD ADCs. It may also need quite some effort to measure it to correct it - this gets much easier if one knows it is predominantly a certain simple function and thus a simple test is enough to estimate 1 or 2 parameters.

I am currently on a DIY multi-slope converter (HW somewhat in between the HP34401 and Keithley 2000/2010), and a plan to release it open source. So far it looks very good for the noise (good enough for 7 digits), but no really stringent INL test so far, as its breadboard only so far.

[EmmanuelFaure]

Are there any very low INL and >= 24Bit-ADC-modules like the Thaler ADC180 or the PREMA 5610E which can be bought at the moment from normal persons?

Another one : AD1175K, 22 bits, made by AD in the 80's but obsolete now.
Clic : http://www.analog.com/media/en/technical-documentation/obsolete-data-sheets/1787587AD1175.pdf

[hwj-d]

Btw, is somewhere described how dc-acal of the 3458a works in detail?

[Kleinstein]

There is likely some description on ACAL work in the manual and also in the HP Journal article on the 3458.

For the ADT 6581, there is quite a detailed analysis on the ACAl operation. A different meter, but similar in respect to ACAL for DC.
The ACAL part is for most parts quite straight forward, though there might be still some small tricky points with waiting times and maybe self heating for the shunts (ACAL tends to use the shunt at a higher current than normal operation).

The difficult part of ACAL is more like the AC part.

[Echo88]

Thanks Kleinstein! Im sure there would be many people interested in testing your OSHW-ADC.
Regarding the proposed LTC2440: If i were to connect a floating voltage to the input, which is variable between +-Vref/2, then the INL should behave like the "Integral Nonlinearity fOUT = 6.875Hz" on page 6 of the datasheet, while i wouldnt worry about the common-mode-voltage since my input voltage is floating?

http://www.analog.com/media/en/technical-documentation/data-sheets/2440fe.pdf

I still have my LTC2508-32-Evalboard, which should still work and should have a little less noise compared to the mentioned LTC2368-24. I will order the LTC2440-Evalboard and also a LTC6655 to solder it on the board (since the LTC2508-32-Board also uses one).
Throw both boards in an temp-regulated-oven (borrowing knowledge from the oven-thread  ), power it with quit supplies and log the data with Python. 

[Andreas]

while i wouldnt worry about the common-mode-voltage since my input voltage is floating?

I fear it is not that easy.
the common mode range demands that the input voltages are forced between -0.3 V and VCC +0.3V
So there are no "floating" input voltages. (except if you isolate the whole ADC + supply).

Negative input voltage means: the positive input is more negative than the negative input. But both within 0 and VCC.

The datasheet picture on page 6 is valid if you tie the negative input to VREF/2.

with best regards

Andreas

[Echo88]

I plan to isolate the ADC supplywise and communicate via optocoupler, so the input voltage truly floats for voltages less than +-Uref. But i think if i were to amplify small floating voltages i would need to use a fully differential amp with Uref/2 as the common-voltage, so the common-mode-voltage does not change if i vary the small input-voltage and therefore my INL stays repeatably the same? Is that correct?
I know of the behaviour "Negative input voltage means: the positive input is more negative than the negative input. But both within 0 and VCC." from my LTC2508-32-Evalboard which confused me when i tested it a year ago.

[Andreas]

But i think if i were to amplify small floating voltages i would need to use a fully differential amp with Uref/2 as the common-voltage, so the common-mode-voltage does not change if i vary the small input-voltage and therefore my INL stays repeatably the same? Is that correct?

Yes in my opinion.

with best regards

Andreas

[Navarro]

I always had this question on my mind.

In this case, we're talking about the AD7172-2. If we have 4 AD sections with AD7172-2 in parallel reading the same voltage on the same VREF, can we get more digits/precision/stability out of this by doing the average of both four ADCs?

[Kleinstein]

The precision ADCs usually are only one ADC. Some like the AD7172-2 have an integrated multiplexer, so that they can choose between inputs, but one at a time. Internally they may actually have some thing like 2 ADCs to make it a differential input, but this is already included in the specs.

There are audio and metering ADCs with 2 or even 3 ADCs inside, but these are usually not accurate for a DC measurement, maybe for AC.

In principle multiple ADCs in parallel could be used to reduce the noise - it is the usual square root N factor (at best, if there is no common noise part). So 2 ADCs in parallel might be feasible, but hardly more. However identical DCs in parallel would not help much with INL.
The effect on stability is also very small as chances are high the ADCs would drift in a similar way.

There might be a use for 2/3 ADCs - not directly in parallel, but in a kind of interleaving mode so that one is measuring the input and the other zero or a reference. Here the advantage would be having less noise, not only from the ADC itself, but also from the signal source as the input measured all the time, with no breaks for the zero adjust.  A similar effect is possible with a single differential ADC and switching polarity instead of switching between zero and signal.

[David Hess]

In principle multiple ADCs in parallel could be used to reduce the noise - it is the usual square root N factor (at best, if there is no common noise part).

Unfortunately the reference noise is common mode.  But one could use more references in parallel ...

[niner_007]

I think you meant AD7172?

http://www.analog.com/media/en/technical-documentation/data-sheets/AD7172-2.pdf

24 noise free bits at 5 SPS

In theory it can reliable produce 16777216 counts or 7,5 digits, accuracy and linearity at that level are a entirely different thing.

Edit: Scullcom hobby's on youtube did a similar project, was going to link it here but youtube ain't co-operating. 

A 7.5 digits DMM does not imply 0.1ppm accuracy, and it is still useful if it doesn't, I know of no 7.5 DMM that has that accuracy, not even 8.5 DMMs do (1 year accuracy, heck even 24hrs is much worse)! For a 7.5 digits DMM, typical (1y) accuracy is around 10ppm, Agilent's new 34470A has an ADC with 0.5ppm linearity, but the accuracy is something like 16ppm, Keithley's DMM7510 has an ADC with 1ppm linearity, but the accuracy is 14ppm.

[Kleinstein]

The really good SD ADC chips can have noise levels good enough for a 7 digit DMM. However the linearity tends to be a little on the poor side, so more like what one expects from a 6 digit meter.  There is no need to get the INL to the 0.1 ppm level for a 7 digit meter, but reaching the 1 ppm level is about what is expected.

Accuracy is a 3rd possible issue - this is often more due to the reference and calibration stability. The ADC chips usually need a reference of some 2.5-5 V, while the LTZ1000 and LM399 references are 7 V.  Getting a really stable 2.5-5 V reference is another difficulty that can effect the accuracy / long term stability. The input voltage range is also more in the 2.5 - 5 V range, which may be inconvenient  as it does not allow to directly measure a high stability 7 V reference.

[iMo]

Inspired by TiN's ADS1262/63  (sigma delta) test I acquired a few chips. They claim 3ppm INL, however.

Then I acquired the TLC2500-32 chips (SAR), they claim +/-0.5ppm INL.

Still not decided with which one to start, however.

In meantime I posted an AFE simulation (+/-20V, >>100Meg input) which may fit 7digits after applying some math.

Is there any practical experience with such an ADC design?

Are there any better chips available?

[alex-sh]

Is there any practical experience with such an ADC design?

Yes, say, building a millivolt meter. Or milliohm meter etc

[Echo88]

Regarding LTC2500, please read the two posts by MisterDiodes: https://www.eevblog.com/forum/metrology/32-bit-adc-playground-for-precision-measurement-tasks/msg1237921/#msg1237921
Personally i really like the LTC2442, with its integrated buffer and MUX. The MUX is a necessary to enable Full Scale/Offset/Long Term-Reference (LTZ1000/LTC1043-divider for 4.8V)-Switching, while the ADC is supplied with a low noise Reference (LTC6655 or chinese low noise diode). Same concept as in the Keithley 2010/2001 for example.

[Luky_13]

Called AD to check if LT2500-32 can be used for absolute DC measurement and they said 'absolutely'. Sending a detailed email to them to confirm again. A project hangs in balance based on the choice of ADC I make. Need to be doubly sure if I can use 2500 for absolute DC application.

[Edwin G. Pettis]

A small word of caution here, the AD boys are not that familiar with LT chips (ask me how I know) and a fair number of the senior LT engineers retired after the merger unfortunately so the knowledge base has become a bit thinner on some of the sophisticated LT chips.  The LTC2500 might work in your app but I would definitely test/prototype it first before committing to a design and I would heed MisterDiode's advice before taking AD's opinion on this subject.

[Kleinstein]

The ready made ADC chips usually have a smaller full scale range, like +-2.5 V compared to the usual about +-10 to +-15 V for most multi chip multi-slope ADC solutions and modern good DMMs. This requires a different kind of circuit and reference. Often this means that the solutions would have different ranges and especially different native ranges where they work best.

One would anyway need to build a prototype first, to see the actual performance and find those little traps for young players. In the ppm range even small effects (e.g. ground return currents and thermal effects) can be annoying. So chances are the performance not only depends on the chip, but also on the board / layout and other parts used (e.g. reference, buffer, amplifier).

[iMo]

..So chances are the performance not only depends on the chip, but also on the board / layout and other parts used (e.g. reference, buffer, amplifier).

As a preparation to an LTC2500 exercise I've posted at least a  simulation of an AFE for a simple +/-20V capable input. Except a low noise high stability 5V Vref, low noise low drift precision opamp, perfect pcb routing, various floating voltage sources you have to get extremely low tempco 1/10 divider as an example. Based on my current understanding the 95% of the problems with even a simple +/-20V voltmeter is with components outside the LT2500.
When you read datasheets of various LTs SAR ADCs you might see the LTC2500-32 INL is the same as the INL of the LTC2380 (their best 24bit SAR). Also the other params are similar. It seems to me the 2500 is basically their standard 24bit SAR core with some DSP over it such they get 32bit as the result.

[julian1]

 Looking at the Keithley adcs (5.5 digit, and 2002) designs, they use discrete logic, 74hct02 (nor) with 175 (flipflop) to control the sd5400cy and other fet switches. It's unclear to me why in the design this logic was not just pushed into the Altera cpld.

One reason is that fast discrete logic might have a speed/ or resolution/ or jitter advantage. Datasheets for 74hct state around 10ns propagation. But the altera epm7160 cpld - in spite of its vintage does 100MHz. It's also 5V compliant for gate drive voltage/ same as the 74 stuff. 

The sd5400cy has a propagation time of 600ps, but presumably depends how fast one can charge/discharge the fet gate capacitance. So using 74 series as a buffer (20mA) makes sense, but not the other stuff.
 
Also, it's a clever revelation to convert the reference voltages for the integrator to current sources - so that RDS(on) flatness of the switches do not contribute bias.

But at least for reference positive and negative voltages RDS(on) should be constant for fixed VDS. Unless maybe it's to void TC effects on RDS(on).   

[David Hess]

Looking at the Keithley adcs (5.5 digit, and 2002) designs, they use discrete logic, 74hct02 (nor) with 175 (flipflop) to control the sd5400cy and other fet switches. It's unclear to me why in the design this logic was not just pushed into the Altera cpld.

One reason is that fast discrete logic might have a speed/ or resolution/ or jitter advantage. Datasheets for 74hct state around 10ns propagation. But the altera epm7160 cpld - in spite of its vintage does 100MHz. It's also 5V compliant for gate drive voltage/ same as the 74 stuff.

It is not the speed but being able to have stable ground and supply voltages because in singled ended CMOS logic, the switching threshold voltages are referenced to both.  Ground and Vcc bounce inside the CPLD, or any programmable logic, places limits on jitter performance unless special steps are taken like differential switching.

The sd5400cy has a propagation time of 600ps, but presumably depends how fast one can charge/discharge the fet gate capacitance. So using 74 series as a buffer (20mA) makes sense, but not the other stuff.

That is another reason to use discrete logic; it allows return currents to be directed exactly where the designer wants.

[julian1]

Edit. Thinking out loud, about jitter a bit more.

The cpld needs to know the count to know how much corrective current it has pushed into the integrator during runup. So at a transition from +ve to -ve reference current - it could set up the transition on the data pin of the latch. And then the main clock would clock in the actual transition. Thus the design takes advantage of cpld/mcu logic, but with the the better aligned clock boundary/edge provided by the discrete series logic.

[Kleinstein]

The HCT02 are also used because of there limited speed to create a short defined dead time. With the switch part there is also the point of keeping a setup that works, even if it is not the most cost efficient. There can be nasty hidden surprises - so better keep a working system. It is not so much about very fast switching, but about a stable timing and delay.  In the HP34401 they add a ferrite to the HC4053 negative supply pin - possibly to slow down the switching and avoid the very high frequencies with very steep transitions.  So better avoid the GHz frequency range if you can.

At least for the 5-7 digit range the jitter is not that critical. One starts to worry about jitter at 8 digts if the switches are operated really frequent like in the 3458 (some 330 kHz modulation). The Keithley meters use a relatively slow modulation (AFAIR some 50 kHz) and thus slightly less sensitive to jitter.
Inside the CPLD there can be interactions with the timing, e.g. from internal ground bounce and loading internal clocks. I don't know from a CPLD, but I have seen a similar effect in a µC: the ADC and UART clock modulate the timing on GPIO pins, though only at a low level (<< 1 ns). So the internal state and other processes can have side effects.

[dietert1]

With modern programmable logic the signal chain of a GPIO involves 10 gates or more behind the last clock-synchronous register, plus some MUX or 3-state logic. You just count the programmable options like pull-up, pull-down, 3-state, inversion, drive strength.. Of course an external synchronizer works much better. Still you need a clean clock signal, so better use an external oscillator instead of the on-chip circuit of the MCU.
From my own experience i can only recommend to start building something simple like a PWM-DAC and try to get the precision. Then you can study in detail the technology of precision time division. The LM399 thread with its lengthy discussion of precision PWM is a good start. That's the path i am taking myself. Hope to use the precision PWM DAC  as calibrator for linearity tests and also for a differential voltmeter. Want to combine the DAC with one of those high resolution ADCs like the ADS1256.

Regards, Dieter

[julian1]

Thank you all for the comments. I notice the 74xx175 already has complementary outputs. So it makes sense for the 74xx02 to implement a break-before-make type sequence, rather than adding additional control logic.

Thinking about it more, and at least for a cpld/fpga (but maybe not for a mcu gpio) I can imagine that the entire LUT/macrocell logic propagation delay is exposed directly at the cpld/fpga gpio outputs. (cpld/fpga designs are not strictly even dependent on a clk). So it makes sense to use the discrete series flipflop/latch to manage the output synchronization if using these control devices.

For circuit/logic simplifications -

For a multislope design, I suspect the switch to short the integrator cap is unnecessary.  One can just use the low current +-ve references to steer the integrator to a 0 cross, when the signal current would then be introduced to begin integration. Certainly not as fast to reset, but a lot less complexity around the sensitive integration loop.

Keeping the slow slope / low reference currents present at all times, also seems like a good simplification. I believe both K2002 and Kleinstein designs follow this approach.  A 100:1 ratio - say 1mA and 10uA would seem like a good starting point.

If one did want switchable slope currents (instead of an always present low-current +/- reference), there is the possibility to pause the integrator midway (switch all inputs off) for the duration of current changeover.

This would permit doing more complicated things - such as switch the fb of an op based current source , while allowing time for the op to settle. But I think this might be too much (control and circuit) complexity.

On the other hand using an op based current source/ instead of voltage-to-current resistors, is such an interesting idea - with its advantages in voiding RDS(on) switch bias. Perhaps even when all switches are lo-side/low voltage / using double-throw to divert current to agnd when off (34401/74hc4053 approaches).

[Kleinstein]

For a multi-slope ADC it is not absolutely needed to have a discharge switch, though this is the classical way. Start from a defined state and measure till back.  The assumption (and for a simple design this is usually true) is that the reset is more accurate than one can get the discharge from the reference slopes.

Directly assuming the cap was perfectly at zero at the end of the last conversions is only approximate. AFAIR the old LD120 chip set did this, though with only 4.5 digit resolution.

Using more complicated switch sequences in the run-up is not directly related to have a fixed small current always present. The small current does not effect the run-up much. It many adds a small offset.

Using constant current sources (like in the Keithley2002) instead of just resistors for the references is possible and it has a few pros and cons. On the positive side the voltage noise of the OP at the integrator gets less important, though there is additional current noise from the OP in the current sources. The main positive point and use in the K2002 is that the ground level for the input and reference are no longer linked. One could get a kind of limited differential input. The switch resistance is no longer important for the reference channels, so smaller switches could be used. However on the downside this also means the switch resistances could no longe be used for a simple compensation for the switch resistance in the input channel. So the switch in the input channel should than be very low resistance (or even with compensation).
Current sources are also quite some effort - not just more OPs, but also more precision resistors.

In my design I don't have the small slope always on.  The small slope is from the sum of the + and - references and can thus be turned off. This is used for a hold mode, so the slow µC internal ADC can measure the integrator voltage and no reset is needed or present. In my case this works better (lower noise) than most reset circuits.

For a simple circuit the 4053 type switches like in the 34401 (or fluke 8846) are a good option. The newer Ti 74LV4053 has lower R_on and works quite well.  Having 3 switches is convenient for the input and 2 main references to get a TC compensation.

[DeltaSigmaD]

Is it necessary to use a multiple slope technique to obtain more than 6 digits? I don't think so.

Just before the LTC2400 was anounced the first time (1997), I developed a Delta-Sigma ADC with >25 bits resolution (not accuracy), which was improved since that time. This production ADC has about 0.1ppm rms noise of full scale with 5/s rate and 1s settling time to <1ppm (reference noise eliminated by ratiometric m.). The current status is that you can achieve easily 25 ppm linearity with a single Delta-Sigma converter stage - this might sound disappointing. But the long term stability is within a few ppm of full scale, i.e. also the residual non-linearity is very stable and can be compensated. It was not necessary to compete with a HP3458A, and therefore this design was not driven to utmost precision. I'm sure, the Delta-Sigma technique has the ability to even higher precision.

A high precision Delta-Sigma ADC must rely on a precisely predictable current-time area nearly independent on the duty cycle and/or frequency (according to my experience). The weak point of CMOS switches are not the DC resistance (can be compensated), but the timing of switch transition. There are current tails in 50ppm range after switching with about microseconds relaxation time (no, this is not the simple RC effect of switch). Any dangling electronic part destroys precision, therefore double throw switches must be used. Now, the timing of the break-before-make action of the switch is the dominating limit for high precision. A further critical point is the current integrator, which must have a high bandwidth combined with low noise. If the bandwidth-gain product of the integrator OP is too low, you will get input spikes with a high voltage-time area, and f.i. voltage-dependent capacitances of any semiconductors can induce non-linearity. Only composite amplifiers can achieve the requirements. Up-to-date DVM designs frequently use power-hungry FGAs which generate high temperature gradients inside the case. The heat management is complicated, a fan is necessary. Hence, the Delta-Sigma engine should run on a microcontroller (~15mW), even 250 kHz DS update rate is possible without problems yielding 1000/s rate. The microcontroller can compensate the non-linearity in real-time.

It would be a very interesting project to try what accuracy can be obtained today. Are there some more people which are interested on such ADC? Please inform me.

[Andreas]

This production ADC has about 0.1ppm rms noise of full scale with 5/s rate and 1s settling time to <1ppm

Hello,

not bad for a sigma delta ADC.
What is full scale on this ADC?
Bipolar or unipolar?

I tried it the other way round using the LTC2400 together with a 5V reference.
But since the ADC has rather high noise (perhaps due to low power consumption) I need integration times of 1 minute to reach 1uVpp/5V noise.
INL can be easily calibrated out due to parabolic shape to within < 1 ppm.
And T.C. (of the voltage reference) can also be compensated to < 1 ppm.
Since the LTC2400 has self calibration of offset and full scale it is very stable over time and temperature after pre-ageing of the reference.
Together with a simple LTC1043 2:1 divider you get a 0 - 10V measurement system.

with best regards

Andreas

[DeltaSigmaD]

This ADC has an input range of +0.5V to -8V in order to avoid voltage range translation (--> resistor drift). The switches were f.i. MAX319, which is rather slow. The fastest ADC with this range, 1000/s, and up to 160 dB free dynamic range at 0 to 500 Hz applied the HC4053.

It is impressive what can be obtained with the LTC2400. The LTC2400 is a really good ADC, but also has weak points. The switched capacitor technique used here causes current spikes at the input, which can be cumbersome. For instance, I was not able to achieve the datasheet linearity with LTC2440 for 1000/s rate. The latter IC is very sensitive to the input capacitor arrangement, and filtering its supply and reference is complicated. X7R capacitors can cause non-linearity, but you need e.g. 1uF. Is there a good solution for this problem?

The DS-ADC ICs have one fundamental disadvantage: the offset is adjusted to zero as part of the switched capacitor technique. But in this case the correlation between succeeding measurement values is destroyed (kT/C noise). Each measurement is statistically independent from other measurements. If you use a sliding average filter, you get a reduction of noise proportional to 1/sqrt(N).

In contrast, a continuous time Delta-Sigma ADC, as mentioned above, maintains the correlation of succeeding measurements. Simply speaking, if one measurement value was too low, the next one will be too large to compensate this. With a sliding average filter you get a noise reduction proportional to 1/N. This is valid until the inherent 1/f-noise (and drift) destroys this correlation (in my case at about 20s averaging). For ratiometric measurements I measured once <0.03ppm rms noise, which value could be reduced even more today. Continuous time Delta-Sigma ADCs can be constructed so that they have very clean dynamic characteristics. The offset correction has be to established by a circuit or techniques independent on the basic Delta-Sigma activity.

Considering this, it can make sense to develop continuous time DS-ADCs even today. This is the reason why I ponder to start a new development using modern electronics, while there will be no commercial use of it.

[Andreas]

Is there a good solution for this problem?

Hello,

I can tell only for the LTC2400.
The reference (AD586/LT1236) is buffered by 10uF Ta + 100nF X7R.
(of course you need a reference which can handle those capacitive loads otherwise you will need a low pass filter)

The input is more critical since the spikes can heavily influence previous buffer Op-Amps creating offsets of up to -30uV.
Here I use a low pass filter with ~820 pF + 825R after the buffer OP-Amp which is a good compromise between influence on INL of the LTC2400 and the previous OP-Amp.

with best regards

Andreas

[Kleinstein]

A discrete build continuous time SD ADC is rather similar from the hardware to a multi-slope ADC.
I think one can consider the multi-slope3 ADC of the 34401 also as a kind of continuous time SD ADC.
HP calls the ADC in there newer 3446xx meters sometimes multi-slope4 and sometimes sigma-delta.

When needing an external auto zero cycle the settling time gets important. Here the classical multi-slope is usually quite good and the time needed for the rundown can also be used for settling of the input after switching. The SD needs to wait a comparable time for the ADC to settle - sometimes this is even longer.

[RandallMcRee]

. . .

Considering this, it can make sense to develop continuous time DS-ADCs even today. This is the reason why I ponder to start a new development using modern electronics, while there will be no commercial use of it.

Yes, I think it would be quite interesting to create an open source ADC of high performance. Let me know if I could be of any help? It would be a learning experience for me. I could, for example, help on creating and measuring a prototype for a circuit that you propose. Verifying characteristics like INL, DNL, etc would be a challenge, however. How have you done that in the past?

Randall

[Castorp]

We also have a CT 3rd order Sigma-Delta built of discrete parts. The development started in the 90s, there's a conference paper from '99 that describes it.
https://digital-library.theiet.org/content/conferences/10.1049/cp_19990460
It was recently improved. Unfortunately I can't release the schematics, but I can explain a few things if there's interest.

The switches are implemented in a rather unorthodox way, using LVC-family logic. It's all controlled by a super simple FSM that fits inside a small CPLD. In the end, the ADC has LF noise in the 0.02 ppm ballpark (defined by the LTZ1000 Vref), white noise is flat up to about 300 Hz where it intersects with the +60 dB/dec quantization noise slope of the 3rd order modulator. INL varies from unit to unit but it's always sub-ppm, and in some units it's down to 0.3 ppm (without corrections or anything). TC is under 0.2 ppm/K thanks to active temperature control Idle tones have always been present, but in the new improved version they are much lower thanks to a different dithering scheme.

It's been a highly educational experience to work on it. On the other hand, nowadays you can squeeze better performance out of an integrated SD ADC.

Edit: I realized the paper is behind a paywall, so I'm attaching a copy. It reports on an early version, it was improved after that and the devices were eventually installed in LHC before 2008. And then the new revision with 5-fold improvement in LF noise was more or less ready in 2019. It will be used for a partial upgrade of some dipole circuits, but not for all of them.

[branadic]

I followed the news and work public available on the ADC. Just to get it right, the 22 bit converter was used before 2008. What exactly was improved on it? Noise?
The new revision from 2019 with 5-fold improved LF noise means the AD7177 based HPM7177?

-branadic-

[Castorp]

So, the "22-bit" is what we call DS22. It's in use in LHC and will remain in use. The improved version is what we call DS24. It's backward-compatible with DS22 - same form factor, same output (raw bitstream with simple encoding). Some of the DS22s will get replaced with DS24, and this partial upgrade involves also one board within the DCCT. The ADC improvements are in the LF noise and idle tones (15-20 dB lower in DS24). The low-frequency noise determines the short-term stability (20 minutes) which is particularly important, but also the 12-hour stability is improved.

HPM7177 is a totally different and new development, and will be used only for some new converters in HL-LHC, particularly the 18 kA inner triplets, 14 kA short dipoles, and also some 2 kA correctors.

The thing about DS22 is that various design choices made it very difficult to improve it any further. There was also no motivation to start a new design from scratch, once we found an integrated ADC that does the job. Generally, the bottlenecks are in the 1-bit DAC (the switches), the first integrator, and the Vref section. We got the major LF noise improvement just by fixing the Vref.

[branadic]

Thanks for sharing. Searching the web I found one of your presentations which directed me to the desciption of the differences. Nice.

-branadic-

[Kleinstein]

For the switching DAC there are 2 options: one is switching before the resistor to the integrator and thus the voltage side. This way is used in the old Solartron meters, but als the newer KS3446x. The other option is switching behind the resistor and this more a current stirring, like in the 3458 or 34401 or Keithley 2000,  2002.  The voltage side switching has advantages from using the same resistor for the positive and negative side and also less sensitivity to charge injection. Reasons for using the votlage side switching can be fast modulation (because of charge injection) and long integration (using only 1 resistor).  However buffering the references is a new tricky point, that is not an issue in the current stirring way.

The other decision for the ADC is whether one wants very low LF noise and drift directly from the ADC. This requires some kind of AZ OP in the integrator and allows very long integration at a piece (like the old Solatron, the Datron 1281 and to some repect also many of the SD ADC chips). The other ways is an ADC with limited LF performance and drift and than an external auto zero cycle in the front end, like periodically switching between the input and zero or in some cases also reversing the polarity. This is done with DMMs like the 3458, 34401, K2000. Some high end ADC chips also offer this option in addtion to an already low drift ADC core. Switching relatively close to the input creates a kind of semi digital chopper and can suppress 1/f noise and DC drift also from the amplifier very effectively.
Az switching at the frontend wants relatively good settling for the ADC after switching - some SD ADCs are not very good at this.

The type of ADC thus also effects the front end. At least for 7 digits, there are several different ways to the target, with different weaknesses.

[julian1]

For dual/multi slope adc, the idea of using a high-side switch before the resistor - so that only one prec resistor is needed, and so that resistor 0.1-10Hz noise (current noise?) and TC is fed equally (and cancels) to both the +ve and -ve reference integrator currents is appealing.

My initial thought, was the tradeoff - that high-side switch/ops would have to handle full-range voltage transitions for +ve/-ve reference voltages and that would create transients.

But perhaps one could apply the same double-throw switch strategy as used by low-side (after the resistor) switch designs. So that the reference op buffers always see the same voltage potential and loads on their outputs.

ie. when feeding -ve to the integrator, then the +ve ref buffer voltage is diverted to a +ve sink in order to maintain the same sink current and voltage (as it would feeding the integrator) and vice-versa.

Maybe high-side switch designs already do this?

It is interesting how much attention is given to handling diverting currents.

The 34401a uses the inductors/ferrites on the diverting output currents as well as pin 7 gnd of the 4053.

K2002 *appears* to me to use inductor/suppression filter (BLM32A07 ) as well as a op buffering agnd (U808) to help sink current. presumably to keep switching noise affects off of signal agnd.

[Kleinstein]

The idea of using additional switches to keep the current for the reference constant is nothing really new. Some meters (e.g keithley 2001) already use this.
Besides the slow average current this also compensates some of the charge injection at the switches. Still the compensation of the charge injection is not perfect and with a delay to make sure to have breake before make the very high frequencies can be also worse. The reference buffers still have to deal with the very short pulses. So the buffer may see 2 opposite sign pulses with a some 10 ns delay. For such a short pulse a ferrite can be quite effective.
 
Besides the fast pulse, there is another weakness with high side switching: The compensation of the switch resistance is more difficult. With CMOS switches the resistance at the low side and high side can be different. Driving the input swich can be tricky to get a constant gate votlage. So high side switching tends to use lower resistance switches and rely less on compensation. Lower resistance and higher voltage rating leads to more charge-injection. Modern MOSFETs often have a limites gate voltage rating and this limites the possible reference voltage level.

The dual slope ADC can use 1 resistor for the integrator. The Multislope ADC usually still needs separate resistors for the input and the reference. There is the theoretical way of adding to the input voltage with a switched capacitor, but this way is rare (I know a multi-slope in a sinclar DMM and the SD ADC in the Prema DMMs). Low side switching with separate resistors for the positive and negative references has some additional offset-drift and possibly 1/f noise of the resistors (current noise). However one ususally still has the resistors in generating the negative reference. A relatively fast auto zero cycle can compensate much of the dift and 1/f noise. The effect on the ADC gain is the same for low and high side switching and the additional resistor is not a problem here. Good resistors with low 1/f noise are available, though some arrays (e.g. NOMCA) show significant noise.

[julian1]

I noted your comments on nomca resistors and noise in the past.  It seems surprising, and I would have naively assumed that thin-film would be broadly comparable as a technology (I also have a bunch of spare nomca soics).

For lt5400, the datasheet states  "Excess Current Noise Mil-Std-202 Method 308 <–55dB" . but I have no idea how to interpret that figure, or even if it is relevant. 

I have used vishay vtf series (Passivated nichrome) https://www.vishay.com/docs/60038/vtfstd.pdf, in a project. They have great TC tracking, but are less commonly available or well-known.

Is there anything that stands out, and what did you decide to use for your ADC board?

[Castorp]

I noted your comments on nomca resistors and noise in the past.  It seems surprising, and I would have naively assumed that thin-film would be broadly comparable as a technology (I also have a bunch of spare nomca soics).

For lt5400, the datasheet states  "Excess Current Noise Mil-Std-202 Method 308 <–55dB" . but I have no idea how to interpret that figure, or even if it is relevant. 

There's a big difference between different types. I did a study and the paper is more or less ready, waiting for green light to be submitted.

LT5400 is a rare exception in terms of specified Noise Index. Usually in the datasheets they give something like <30 dB or <40 dB for foil. Actually LT5400 has even less - it's better than -60 dB, but there are other thin film ones that are even quieter. I think with <60 dB you really don't have to care much - that's less than 1 nV rms/VDC/freq. decade. NOMCA and AORN are 2 orders of magnitude noisier, which is already significant in places where you aim for low 1/f.

[Kleinstein]

The Mil Std.202 noise specs are relative to 1 ppm resistance variations over 1 decade in the frequency. So a -40 dB noise index would be 0.1 ppm fluctuation in the resistance over 1 decade in the frequency (like 0.1 to 1 Hz). With some 10 V applied to the resistors, this would be some 1.4 µV_rms noise for the 0.1 to 10 Hz range and thus quite significant compared to a presion OP (often < 100 nV_rms (600 nV_pp) for the 0.1 -10 Hz band)
The noise specs for the resistors can often be just a test limit. It is not easy to measure the resistor noise to a low level (e.g. < -50 dB).
So chances are the < -55 dB for the LT5400 and other low numbers could be just the limit of the test system.

The NOMCA resistors show some noise, noticable, but also not dramatic. In my ADC they were still the dominant source of 1/f noise. My currently lowerst noise version has ORN type resistors (passivated NiCr on silicon like LT5400 - but available in 50 K and in a SO8 case). The ADC version with NOMCA resistors had about 1.5 to 2 times the noise, especially more 1/f noise. So the NOMCA resistors were the largest noise source, but it is still possible to get low noise (8 digit range) with the NOMCA reisistors with a fast (1PLC) auto zero cycle. With longer integration at a piece the resistor noise gets more important though. The resistor noise also gives fluctuations in the ADC gain. The NOMCA resistor would be only slightly worse than the noise from a LTZ1000 reference.

From the specs both NOMCA and ORN give < 30 dBi, but NOMCA are not much better than that number while the ORN resistor turned out much better - not as good as the LT5400 specs, but good enough. So far I get about 1 ppm/K TC for the ADC gain, which depends on 2 sets of resistors (reference amplification (5 K array) and the ADC itself (50 K array)). The number can scatter and this is just with 2 units.

For  the thin film resistors it still depends on the size and thickness of the film. Chances are a very thin film is worse than a thicker film and than a finer pattern. The area also matters - a 2S/2P combination gives half the noise (-6dB). There may be a tendency for TaN based resistors (like NOMCA) to use a rather thin film because etching can be more difficult (TaN can be quite innert - a reason it is good for resistors).
The same resistance can be acheived with a more uniform block and very thin film or a fine etched meander pattern and a thicker film.
Chances are the fine etched pattern is lower noise. The details on the surface may also make a difference.
There are also NiCr resistors with quite some noise. PTF56 (10 K) THT resistors did not perform much different from the NOMCA array. I tested (extra noise test, not in the ADC) Susumu RR (4 K, 0805 size) and I could not see much noise to about a -50 dbi test limit.

Chances are the VTF resistor arrays are likely OK, but not guarantied. The < -35 dbi noise specs could be just a measurement limit. They offer resistor arrays with a large ratio and thus must have reasonable capability for fine patterns.

The user CASTROP did show some noise measurements (upfront)  here in the forum. It includes NOMCA and ORN, but I don't think it includes VTF.

[julian1]

// Not sure if this is the right/best thread.
 
Here are some very preliminary experiments with a Kleinstein inspired design ('4053 switch and biased resistor ladder, for low-current rundown slope), with a fast comparator lt1016 10ns for crossing detect and rundown.

My main focus has been on the control side, to understand and get the 4 phase (2 fixed, 2 var) modulation scheme working.

For the simplest possible test - 4 phase switching of the +- ref currents, with no input signal, and using the same current (not slow) for final rundown, no initial integrator reset short, and slower waveform (around 2kHz) than desirable.
   

Each line represents an integration time of 5 seconds, with a 20MHz clock, so a 100 million count.
(the fixed pos phase was biased for test purposes, so count_up != count_down)


count_up 5137,   count_down 4864  rundown 6765
count_up 5137,   count_down 4864  rundown 6761
count_up 5137,   count_down 4864  rundown 6761
count_up 5137,   count_down 4864  rundown 6762
count_up 5137,   count_down 4864  rundown 6762
count_up 5137,   count_down 4864  rundown 6761
count_up 5137,   count_down 4864  rundown 6762 
count_up 5137,   count_down 4864  rundown 6761
count_up 5137,   count_down 4864  rundown 6762
count_up 5137,   count_down 4864  rundown 6761
count_up 5137,   count_down 4864  rundown 6760
count_up 5137,   count_down 4864  rundown 6761
count_up 5137,   count_down 4864  rundown 6763
count_up 5137,   count_down 4864  rundown 6763


The low variance of the final phase rundown count is an encouraging first step.


I suspect that with 5 sec integration, TC effects will dominate over 1/f noise, so it's a useful baseline, before trying to speed things up.

At cold board power on - there is a walk up of around 120-150 count over 5 minutes. which I suspect is a TC affect somewhere.
 
I tested the TC contribution of various circuit components - by dabbing a couple drops of cooling isopropyl on them.

The nexperia 74hc4053 appears most sensitive with a -50 count drop. followed by the 2x lt5400 for ladder divider and current sources, and then other resistors (ref, compound integrator, slope amp) which are hardly noticeable.


I want to try the TI SN74LV4053 as a prefered part to the nexperia (lower rds(on), faster switching) before making other changes.

I had previously ordered it, but got the tssop version by mistake, so need to reorder.

[Andreas]

Hello,

I would also try the MAX4053A (A-version) with specified low leakage current.

with best regards

Andreas

[Kleinstein]

With 5 second integration the 1/f noise can have quite some contribution. It depends on the OP used. For 5 s integration I would suggest an AZ OP for that part. So an integrator a little like the Solartron or Datran1281 DMMs.
Drift af the resistors can also be a major point. With 10 V at the resistors for the reference, 1 ppm change in the resistor would act like 10 µV change in the voltage, which is quite a bit.
The switch resistance has quite some temperature dependence and could be the even stronger effect even though the switch may be only 1/1000 if the resistance. At least there is usually quite good compensation. So it really helps to have the relevant switches on the same chip.

Leakage can be contribution too. There is huge range from the typical leakage (10 pA range) to the guaranteed values, especially with the cheap parts. The max4053 is mainly better with the test limits.

For the start a 4 step mode is Ok, epspeially with slow modulation and thus sufficient settling time. The 3 step mode has more switching but is less sensitive to settling, so it can get better INL, despite of using only half the time for the fixed pulses.

[julian1]

Swapping the nexperia for the TI 4053 part fixes the previous TC sensitivity of the switch.  I also have the Max part although I have not tested it yet.

Using the lt5400, for divider ladder and ref currents, shows a 0.2ppm-0.3ppm/C TC  (ie 20 count / C) count sensitivity.

Which by itself is quite good, and the numbers match/agree with lt5400 specs (0.2ppm/C matching TC).   

But over a longer 5 sec integration period - the thermal walk/variation means that 8 digit stability/resolution (ie disregarding hard stuff like accuracy/INL) is not quite achievable.  ref was also changed from lm399 to ltz1000 to rule out ref noise/tc.

The lt5400 footprint thermal pad has via stitching, and it measures within 1C of the board temp, as far as I can tell - so TC effects are dominated by board temperature, rather than die self-heating.

I can suck it up, and decrease the integration time to reduce thermal walk influence (and increase 1/f noise) - while adding software auto gain/offset calibration for each cycle (several comments in the forums suggest that is what the k2002 does).

And a better board layout can help - since there are several hot to92s for power supplies.

But I am also tempted to pay the money, and experiment with z foil smd placed next to each other - with the possibility that tracking TC is better than the lt5400.
 
It's crazy to think how good the U180/3458a resistors are, and considering the vintage of the design. I almost wonder if there is some additional trick going on - like multiplexing/swapping +ve ref resistor becomes -ve ref resistor for each cycle, to keep tc effects under control. 

[Kleinstein]

There are concepts / patents (AFAIR some phillips) on swapping resistors, but is not easy as it needs extra switches. The 3458 DMM does not include this. With switching at the voltage side (e.g. like in many of the Solartron meters) the same resistor is used for the positive and negative reference. This makes the resistor less critical. AFAIK the DA1281 uses a charge pump for the reference votlages and thus avoids critical resisors there.

Usually the resistor drift should not be so bad and the main effect would be some offset drift. The 3458 uses only 200 ms of integration at a piece and uses averaging for more. There is a point when longer integration does not really help anymore. I don't see a real need for 5 s integration if one has a rundown with slow slopes. Shorter integration and than averaging may be more effective.
With shorter integration the resistor drift is not that bad anymore. The offset shift has to compete with the ADC noise. The ADC gain part of the drift only has to compete with the reference and thus usually has less competition.

The LT5400 has quite good specs - not so sure the foil resistors are much better. At the high end I would consider the specs with a piece of grain - they can be effected by test limits. The specs on excess noise are often more a testlimit than actual telling things about the parts.
Specs on the long term drift are difficult by principle.

AFAIK the U180 resistors are quite large in area and the resistors interleaved  - this is a bit like having multiple parts combined. This can also improve matching and excess noise.  Gain TC of the 3458 is not that special. Something like 0.3 or 0.5 ppm/K seems to be about normal.  For my ADC versions with ORN networks I see comparable ADC gain drift values, even though the arrays only have a 2 ppm/K spec.

A point I noted is that the ORN networks also react to board bending / stress. So it is no only temperature. Humidity can also have some effect.

AFAIK the keithley 2002 does not use a gain calibration in every cycle. If at all they have it on a longer time scale.
The older meters like 2001 seem to use this and this K19x describe it in the service manual.

[julian1]

Just a quick update, maybe there is some discovered information that is useful to share with others.

I did a test board - to compare perofmance of lt5400 versus Vishay smnz matched foil resistors in soic-8. The smnz have slightly better specs on paper, so I felt it was worthwhile to compare.

In testing, I found TC perfomance of the smnz using the same currents was considerably worse - 2x to 3x compared with lt5400. This was a good result and it determines what part to focus on in future - especially given the higher price of the smnz versus lt5400.

With some more testing, I noiticed there was perhaps some self-heating/wandering issues using single lt5400s - with the packages measuring from 1C to 2C higher than the board temperature.  I am fairly convinced there is an issue here, since I can observe the correlated integrator rundown count with a thermocouple reading from the top of package - and this occurs after 10mins and the board is warm/thermally stable.

So I tried doubling-up the lt5400 resistors - from 10k to 20k, for the divider ladder and current sources. This should reduce die self-heating according to I2R, but increase 1/f noise.

In practice, the ref currents go from +- 1.4mA down to 0.75mA (which seems better intuitively), and self-heaing is spread across twice the die surface area, so it felt like it should be a win.

Result was inconclusive - measurement variance was higher - but I am not certain how much of this can be attributed to the exposed wire bodges that are susceptible to emi etc.

I really wanted to get lt5400 1k or MORN 500R, to substitute in the same footprint as the lt5400 10k - and make it easier to swap and experiment with ref currents without board revisions, or lots of extra footprints. But the supply chain issues are real and there are none available anywhere. Searching the web, I found one manufacturer of 0R jumpers in MSOP-8 which would be ideal, but they had non in inventory and would need to retool .

Also did a board, paying a lot more attention to star grounding, but also made some mistakes - and performance was worse than the original board.

Waiting on another board, before I get to do some more tests.

[Kleinstein]

Using 750 µA of reference current would be very much on the high side. There are 2 other problems besides self heating: the CMOS switches get nonlinear at high currents. So one would also need lower resistance switches. AFAIR the Ti LV4053 switches showed still noticable nonlinearity at 700 µA.
Another problem is the load to the op in the integrator. With a higher load current the may also get nonlinear, at least this effect is mentioned in some literature.

The divider ladder to amplify the reference voltage is not so critical. Here the voltage and thus the self heating is constant and thus kind of acts like resistor tolerance.

I don't see why a reduced current should increase the 1/f noise. The 1/f noise is usually from the OPs and maybe excess noise from some resistors (the LT5400 should be fine and hardly dedectable 1/f noise). With 2 resistors in series instead the resistor 1/f noise would be more like going down as 2 resistors are averaged. Similar less heat would more like reduce temperature variations and 1/f noise from this. A larger resistance would increase the white noise part. Still even 50 K  (as 3 x 50 K to the integrator input) can get you quite low in noise. The HP3458 uses 40 K and 50 K mixed, which is slightly worse than 3x50 K.
The obvious way to fight 1/f noise is using less integration at a time ( e.g. 40 ms instead of 200 ms) and averaging over multiple auto zero cycles instead. This increases the relevant frequency.

[julian1]

With 2 resistors in series instead the resistor 1/f noise would be more like going down as 2 resistors are averaged.

Thanks, that is a very helpful insight. I was thinking in terms of thermal noise increasing with resistance. But with two resistors - even in series, with twice the die area it should be much the same.

[Kleinstein]

With 2 resistors in series each resistor will see half the voltage and thus get 1/2 the 1/f noise voltage. The noise at the 2 resistors is not correlated and thus adds as squares. So the 1/f noise would be smaller by the factor square root 2 or a 3 dB improvement in the noise index.

The white noise goes up with a higher resitance, but it still not too high.

Another noise source that goes up with a higher resistance is the current noise of the OPs. The current noise of BJT based OPs like the OP07 often has quite some 1/f component. The 1/f cross over for the current noise is often higher than for the voltage.

[Andreas]

I don't see why a reduced current should increase the 1/f noise.

Hello,

do not forget the input current noise of the OP (which is multiplied with the Resistor value at the input).
So every OP-Amp has its sweet spot regarding input impedance.

with best regards

Andreas

[julian1]

It was good to persist with this issue. The ref currents were knocked down to 7.1Vref *2 / 4x10k = +-350uA (disregard bias).

The local TC wandering of lt5400 due to self heating is no longer evident above the TC effects of the general board with its higher thermal mass.

With a 5sec integration/100 million count (slow slope disabled) the rundown count final digit std dev is < 1. Previously with higher currents stddev was around 2-3 with identical parameters.

circuit details - ladder opa2277, compound integrator 2x opa140 10k/2k divider, slope amp ad847 1k/5k, lt1016 hystersis 200k/100R.

Code: [Select]

  count_up 5215,   count_down 4789  count_rundown 1973      stddev_rundown(5) 0.40
  count_up 5215,   count_down 4789  count_rundown 1974      stddev_rundown(5) 0.49
  count_up 5215,   count_down 4789  count_rundown 1975      stddev_rundown(5) 0.75
  count_up 5215,   count_down 4789  count_rundown 1974      stddev_rundown(5) 0.63
  count_up 5215,   count_down 4789  count_rundown 1973      stddev_rundown(5) 0.75
  count_up 5215,   count_down 4789  count_rundown 1974      stddev_rundown(5) 0.63
  count_up 5215,   count_down 4789  count_rundown 1974      stddev_rundown(5) 0.63
  count_up 5215,   count_down 4789  count_rundown 1975      stddev_rundown(5) 0.63
  count_up 5215,   count_down 4789  count_rundown 1975      stddev_rundown(5) 0.75
  count_up 5215,   count_down 4789  count_rundown 1976      stddev_rundown(5) 0.75
  count_up 5215,   count_down 4789  count_rundown 1975      stddev_rundown(5) 0.63
  count_up 5215,   count_down 4789  count_rundown 1975      stddev_rundown(5) 0.40
  count_up 5215,   count_down 4789  count_rundown 1977      stddev_rundown(5) 0.80
  count_up 5215,   count_down 4789  count_rundown 1976      stddev_rundown(5) 0.75
  count_up 5215,   count_down 4789  count_rundown 1976      stddev_rundown(5) 0.75
  count_up 5215,   count_down 4789  count_rundown 1978      stddev_rundown(5) 1.02
  count_up 5215,   count_down 4789  count_rundown 1978      stddev_rundown(5) 0.89
  count_up 5215,   count_down 4789  count_rundown 1976      stddev_rundown(5) 0.98
  count_up 5215,   count_down 4789  count_rundown 1977      stddev_rundown(5) 0.89
  count_up 5215,   count_down 4789  count_rundown 1977      stddev_rundown(5) 0.75
  count_up 5215,   count_down 4789  count_rundown 1978      stddev_rundown(5) 0.75
  count_up 5215,   count_down 4789  count_rundown 1978      stddev_rundown(5) 0.75
  count_up 5215,   count_down 4789  count_rundown 1979      stddev_rundown(5) 0.75
 
   
       
To move a bit from baseline tests in favor of a pragmatic design - and decrease the measurement interval from 5s to 1s;
 
This test addresses 1/f noise, by multi-sampling the uncorrelated output of several shorter integration periods.

Using 200ms/4PLC integration period. Mean of 5 samples, for a 1sec measurement interval. With the slow rundown (30uA) enabled, the stddev of each individual integration goes up. But the aggregated values are good. ( stddev(mean(n=5)) < 1 ).

Code: [Select]

  count_up/down 263 238, clk_count_rundown 54838, stddev_rundown(5) 1.47, mean (5) 54835.80, stddev_means(5) 0.27
  count_up/down 263 238, clk_count_rundown 54840, stddev_rundown(5) 2.14, mean (5) 54836.80, stddev_means(5) 0.50
  count_up/down 263 238, clk_count_rundown 54836, stddev_rundown(5) 2.15, mean (5) 54836.60, stddev_means(5) 0.56
  count_up/down 263 238, clk_count_rundown 54834, stddev_rundown(5) 2.15, mean (5) 54836.60, stddev_means(5) 0.48
  count_up/down 263 238, clk_count_rundown 54839, stddev_rundown(5) 2.15, mean (5) 54837.40, stddev_means(5) 0.51
  count_up/down 263 238, clk_count_rundown 54835, stddev_rundown(5) 2.32, mean (5) 54836.80, stddev_means(5) 0.29
  count_up/down 263 238, clk_count_rundown 54836, stddev_rundown(5) 1.67, mean (5) 54836.00, stddev_means(5) 0.45
  count_up/down 263 238, clk_count_rundown 54837, stddev_rundown(5) 1.72, mean (5) 54836.20, stddev_means(5) 0.49
  count_up/down 263 238, clk_count_rundown 54834, stddev_rundown(5) 1.72, mean (5) 54836.20, stddev_means(5) 0.52
  count_up/down 263 238, clk_count_rundown 54834, stddev_rundown(5) 1.17, mean (5) 54835.20, stddev_means(5) 0.52
  count_up/down 263 238, clk_count_rundown 54838, stddev_rundown(5) 1.60, mean (5) 54835.80, stddev_means(5) 0.37
  count_up/down 263 238, clk_count_rundown 54832, stddev_rundown(5) 2.19, mean (5) 54835.00, stddev_means(5) 0.50
  count_up/down 263 238, clk_count_rundown 54835, stddev_rundown(5) 1.96, mean (5) 54834.60, stddev_means(5) 0.57
  count_up/down 263 238, clk_count_rundown 54839, stddev_rundown(5) 2.58, mean (5) 54835.60, stddev_means(5) 0.43
  count_up/down 263 238, clk_count_rundown 54833, stddev_rundown(5) 2.73, mean (5) 54835.40, stddev_means(5) 0.43
  count_up/down 263 238, clk_count_rundown 54839, stddev_rundown(5) 2.94, mean (5) 54835.60, stddev_means(5) 0.39
  count_up/down 263 238, clk_count_rundown 54831, stddev_rundown(5) 3.20, mean (5) 54835.40, stddev_means(5) 0.37
 
   

The only problem is the lack of resolution in the runup counts, due to very slow modulation (around 1250Hz/ 10nF cap). 
   
So the next step will be to increase modulation speed (at least) an order of magnitude (12kHz). 

I will keep the rundown slope the same (by reducing ladder bias) - since the final digit of the rundown count appears to capture the variance and show where the noise level is.
 
Now waiting on an order of caps -  WIMA FKP3, PP, 1nF and smaller as well as some TDK C0G smd to experiment with.

[Kleinstein]

For the frequency of the modulation there are 5 effects to take into account:
1) The faster the modulation, the smaller the capacitor can be and thus more gain in the integrator. This reduces the noise for the final charge contribution, e.g. as noise from the slope amplifier. This is especially important with shorter integration times, like less than 1 PLC.
2) With lower modulation frequency more charge is stored in the capacitor and dielectric absorbtion gets more important.
3) With faster modulation mode time is lost to the minimal pulse length. They may need shorter minimal pulses or a reduced usefull conversion range.
4) With faster modulation the jitter gets more important (going up with the square root of the frequency).
5) faster modulation reduces the time for the worst case rundown.

1.25 kHz modulation is rather slow, a bit comparable to the Solartron DMMs.  Even 12 kHz is relatively slow and may need extra measures to reduce INL effects from DA.  AFAKI the used frequencies are some  5 kHz for the ADTV6581, 25 kHz in Keithley 2000,  ~ 330 kHz for 34401 and 3458.
Though not ideal, one can still increase the modulation frequency without reducing the capacitor size. One still gets reduced DA effect (reduced INL error), but not the reduced noise from a smaller cap.

The choice of AD847 for the slope amplifier is a bit odd, though it is used in other DMMs (e.g. K2002). The slope amplifier in most versions does not have to be very fast - one reason for the slope amplifier is to limit the bandwidth. So faster is not always better. This is a bit different from the simple dual slope ADC where a limited speed of the slope amplifier / comparator  leads to an error in the range around zero. With the MS ADC a delay from the slope amplifier only results in some offset and a bit more minimal time for the rundown steps.
The noise of the slope amplifier can be important for the residual charge measurement, so especially important with a large capacitor. The noise there is set by the integrator, the OP in the slope amplifier and the resistor(s) at the slope amplifier. A low resistance at the slope amplifier needs more current that may lead to nonlinear effects from loading the integrator - at least this is a possible INL source.

[julian1]

The ad847 (15nV/√Hz, 50MHz) is old school and copied from the k2002.  I initially had a lt1358 (25MHz, 8nV/√Hz ) and 10k/10k. as the only other fast op in my possession.

I am uncertain about the need for much slope gain, since the lt1016 already boasts GBW ~= 50GHz according to the datasheet. Maybe the next test will be ne5532 (5nV / 10MHz) and 5k/5k. Power and heating is low because of the limited voltage range +-0.7V, but with 1k/5k I did forget about the possibility of loading on the integrator.

With some term adjustment and a 2 variable regression model, and calibrating against the local ref at 7.1V, I now get measurements in the voltage domain!..

Code: [Select]

    clk_count_int_n   20000000
    period            1.000000s
    nplc              50.00
    clk_count_init_n  10000
    clk_count_fix_n   700
    clk_count_var_n   5500
    mod freq          909Hz
    use_slow_rundown  1
    himux_sel         1101 ref-hi

    sampling ref-hi
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26348, predict 7.099,998,9 stddev(5) 0.36uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26345, predict 7.099,999,3 stddev(5) 0.30uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26342, predict 7.099,999,6 stddev(5) 0.30uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26341, predict 7.099,999,7 stddev(5) 0.36uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26337, predict 7.100,000,2 stddev(5) 0.49uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26336, predict 7.100,000,3 stddev(5) 0.43uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26336, predict 7.100,000,3 stddev(5) 0.38uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26335, predict 7.100,000,4 stddev(5) 0.19uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26343, predict 7.099,999,5 stddev(5) 0.38uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26335, predict 7.100,000,4 stddev(5) 0.38uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26340, predict 7.099,999,8 stddev(5) 0.38uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26341, predict 7.099,999,7 stddev(5) 0.36uV,
    count_up/down 2163 1061, fix_up/down 1612 1612, clk_count_rundown 26339, predict 7.100,000,0 stddev(5) 0.30uV,

    sampling ref-lo
    count_up/down 1696 1540, fix_up/down 1618 1618, clk_count_rundown 59344, predict -0.000,001,1 stddev(5) 0.46uV,
    count_up/down 1696 1540, fix_up/down 1618 1618, clk_count_rundown 59347, predict -0.000,001,5 stddev(5) 0.43uV,
    count_up/down 1696 1540, fix_up/down 1618 1618, clk_count_rundown 59344, predict -0.000,001,1 stddev(5) 0.24uV,
    count_up/down 1696 1540, fix_up/down 1618 1618, clk_count_rundown 59338, predict -0.000,000,4 stddev(5) 0.43uV,
    count_up/down 1696 1540, fix_up/down 1618 1618, clk_count_rundown 59348, predict -0.000,001,6 stddev(5) 0.40uV,
    count_up/down 1696 1540, fix_up/down 1618 1618, clk_count_rundown 59344, predict -0.000,001,1 stddev(5) 0.40uV,
    count_up/down 1696 1540, fix_up/down 1618 1618, clk_count_rundown 59339, predict -0.000,000,6 stddev(5) 0.42uV,
    count_up/down 1696 1540, fix_up/down 1618 1618, clk_count_rundown 59345, predict -0.000,001,3 stddev(5) 0.44uV,
    count_up/down 1696 1540, fix_up/down 1618 1618, clk_count_rundown 59338, predict -0.000,000,4 stddev(5) 0.44uV,
    count_up/down 1696 1540, fix_up/down 1618 1618, clk_count_rundown 59342, predict -0.000,000,9 stddev(5) 0.32uV,
   

I want a good record for baseline performance before playing with other circuit changes (speed, samples, slope amp etc).

INL looks tricky. My sig-gen wanders at the 4th and 5th digits for DC. And my 6.5meter doesn't show final digit uV on a +-10V range.

I experimented with perturbing the modulation frequency slightly, while holding the same cal coefficients. And I get around +-5uV delta sampling ref-in.

Other eevblog threads suggest a good proxy test is to sweep voltage - and plot different modulation parameters/ and swap input polarity (turnover test)

The options I am considering to generate these input voltages are,

Another ltz1000 ref (1.2uV p2p 0.1-10Hz) + bipolar dac (1uV RMS 0.1-10Hz) .

Alternatively a largish (buffered) capacitor and switching to be able to be able to charge/discharge it.

Both possibilities need another custom pcb, which will be slow with the new year.

The problem with the sweep techniques is that they won't reveal the true shape of non-linearity (which might also be corrected with non-linear terms) .

[chuckb]

It seems the Analog to Digital Converter researchers and the Frequency Stability researchers have a similar Functional stage, the low-noise, low-jitter comparator. I have not seen a good analysis or methodology for designing the comparator stage in the ADC. However there are several papers written about the comparator stage for the Frequency Stability analyzers.

http://www.ko4bb.com/getsimple/index.php?id=bruces-zero-crossing-detectors

There may be information or ideas here to apply to the design of the ADC.

[Kleinstein]

With the multi-slope ADC the slope amplifier is not so much about making the comparator to react faster also with a small slope. The slope amplifier also has the job of limiting the bandwidth for the final change measurement / trigger. So the speed is a compromise between the speed and noise.
The speed is somewhat critical in the simple dual slope ADC, when the rundown part can come from both sides. In the MS ADC the final rundown oart usually comes allways from 1 side and a fixed delay is thus not critical.
With the additional final charge measurement from the auxiliary ADC the slope amplifier is also part of the amplification for this signal. In this case the comparator is rather uncritical.


For the turn over test any stable external reference can do, one does not really need a special PCB for this. For the start a LM399 or 1N829 based ref should be good enough, though a bit more noisy. Ideally one would do the turn over test at multiple voltages, e.g. with a divider and buffer amplifier.
The circuit is still simple enough for raster prototype board.
The polatity change can be with 2 SPDT switches. So with the 2 switches one will have 4 readings: 2 offset readings and 2 voltage readings. The 2 offset readings can compensate of the offset of the ADC and also extra offsets / thermal emf from the switches.

The test with the slowly drifting voltage and different ADC modulation modes does not need a sofisticated layout or PCB - I used a breadboard for this part with no problem.

[julian1]

Here's a plot using two sets of modulation parameters - with 10NPLC/ 1nF TDK C0G/16kHz across a +-11V input source.

The overall plot shape/ and (lack of) tightness in the cluster observations is influenced by DA on the cap (10uF/X2 class MKP/PP) used to generate the source voltage, as well as settle time between measurements.  The switching and sweep is automated on the mcu side which is nice. But there's a compromise to be made in shortening the sweep time to get useable results in a reasonable period (1hr) .

Also tested faster modulation 330pF/45kHz with the expection of higher noise, but better INL. However INL appears a bit worse - perhaps due to clock jitter, or more charge injection variation.

Input short noise (at 16kHz) is around 350-400nV RMS at 10 NPLC, which is reasonable, and not really observably higher when sampling ref-hi due to the ltz1000.

But there are some quantitization issues. With a 100k ladder bias resistor (foil), the rundown count acheives a measurement resolution of around 500nV on a +-11V range (perhaps ok for 7.5 digit resolution).

To experiment with higher resolution, I increased the ladder bias resistor from 100k to 250k. 

But somewhat surprisingly this also increased the INL at both 16kHz and 45kHz modulation frequencies.

Initially I considered this might be due to extra DA non-linearity persent due to the longer rundown phase. But I think, there is another effect present as well.

After signal integration is stopped, the cycling of the ref currents is continued until the integrator output voltage lands above the zero-cross - in order to be able to start the rundown.  This continuation cycling completes in a predictable way and within a fixed max period due to the intrinsitc +-ref bias (k2002 background current source, or Kleinstein ladder bias resistor).   

However, the amount of cycling is variable - and so there is a phase that is unrepresented/uncaptured, during which signal mux off leakage might influence the measurement. So I want to try to instrument and test this.

Alternatively if it does prove to be DA non-linearity due to a longer rundown period - I think it might be able to be controlled for with fancy math.

In any case, it's easy to see why residial ADCs became popular in multislope designs. Or else the ability to approach rundown from either direction to avoid extra cycling (perhaps this is what the 3458a does).

[Kleinstein]

The difference curve looks quite good. Still a little noisy, but not not much nonlinearity visible. The slight overall slope is not that uncommon and would only be a slight change in gain with the run-up pattern, so not yet a INL contribution.

Jitter would not cause INL, but more noise with faster modulation. 45 kHz modulation is still not very fast and unless slow chips of a poor oscillator is used the noise contribution should not be so bad. Expect noise from jitter to be  jitter * 2 * ref. voltage * sqrt(modulation_frequency / integration_time).
So 10 ps of RMS jitter would result in some 140 nV of noise with 50 kHz modulation and 10 PLC integration. 10 ps of RMS jitter would be pretty poor. The data I have found are 4 ps for 74LS..., 2.2 ps for 74 HC... and 1 ps for 74AC.... So the overall jitter is more expected to be in the 2-5 ps range.
The charge injection variations should also not be so significant, unless the supply is really noisy.

More INL with a higher modulation frequency can come around from incomplete integrator settling, though the main expected effect is a small change in the gain. A smaller capacitor can here also make things more tricky as the step amplitude gets larger. So for tests one could as well increase the frequency, but keep the capacitor. A smaller capacitor alone does not help against DA. It helps with the noise in measuring the final charge. At 10 PLC integration the final charge noise should not be an issue, even with not so ideal comparator or slope amplifier bandwidth.

To get a predictable sign to start the rundown, one can just add another step to the rundown. AFAIK this is also done in the HP3456 and likely also other DMMs like K2000,K2002.  So the rundown starts with the reference of the same polarity as the small slope: either a little beyound zero corssing or a fixed time if allready the right sign. Then follows the normal fast run-down, slow run-down and maybe even slower or the auxiliary ADC.
This way there is always a fixed number of switching events and even in the same sequence.  Adding extra cylces would be a problem with a variable number of switch operations, not so much the variable delay.

350-400 nV of noise with 10 PLC is OK,  about on par with the KS3446x.

[julian1]

I was asked to give a few more details about my design.

The asymmetric current source with '4053 switch are borrowed from Kleinstein's innovative design. While the fpga for control + 74hc175 synchronization + rundown comparator are more Keithely part choices.

There are a few bodges/changes from the schematic; The 80k signal input is shorted to 40k (properly compensated, but badly distributed) and the current bias resistor is paralleled across only one of lower ladder resistors (shallower slope with less resistance).

The bootstrap circuit was tested independently with a sig-gen and is stable with RC set to 1/2 to 2/3 of the op GBW but has not been used yet. I think it has some issues;

Namely, the source/sink are set to fight each, so the bottom bjt q6 needs to be jumpered by a resistor.  also the 100R emitter degenerators defeat the purpose of bootstrapping by dropping a varying voltage, and should be 0R. I also want to replace the dual diode sot-23, with a more conventional two bjt current source.

At the moment I get a 20uV stderr trying to fit a 3 point (+7, 0, -7V) linear calibration, which I suspect is due to using the opa140 buffer standalone, and without the bootstrap.

I also did a board with Linear Systems dmos switches, and current sources, but it has not been tested.  Also a board with a standalone stm32, but I had trouble trying to juggle control using peripheral timers/interrupts

[julian1]

Then follows the normal fast run-down, slow run-down and maybe even slower or the auxiliary ADC.

Doing a 'fast rundown' phase is a great idea. I tried adding a bunch of short up-direction phases, until an up direction cross, before switching to slow rundown. But the goal was to figure out whether (stopping) extra-cycling was causing INL issues, and it didn't help, and was removed.
 
It turns out, there was still some unbalanced charge injection issues.

- I believed ref switch transitions were ok, because of code to count them. But these checks were forgotten around the rundown changeover sequence. At the conclusion of runup, to keep the switch transition counts the same, the on switch used in the last phase must first be turned off (so both switches are off). And then both switches can turned on for slow rundown. Instead, if the off switch is immediately turned on for slow rundown, there is a off-by-one error in switch counts /and charge injection balance.

Also, I suspect an error in the clk counts, based on how the state transitions is done. This was fixed by using raw clk count values, instead of counting (var,fix) phases and then multiplying by the constant clk duration of the phase. This approach is cleaner and simpler.

The higher frequency (330pF/45kHz) modulation chart now looks more behaved.

[Kleinstein]

An OPA140 as a buffer should not give that much error. The CMR is very good (140 dB typ) and the loop gain is also not that bad (126 dB). So I would expect more like < 5 µV of error from that buffer. One of the weakest points could be the cross-over distortion of the output stage.

The bootstrapped supply may still be a bit on the fast side. When combining amplifiers usually a factor of 6 to 10 in the BW is a good idea.

For the refrence switching there is no need to absolute balance the number of switching the positve and negative side. The important point is only to keep the number constant, independent of the signal. The subtraction of a zero readings takes care of any offset as long as it is constant.

The slope amplifier as shown still looks quite fast. It may help to slow it down a little, either with a capacitor in the FB or simply more gain.

Doing the control with an STM32 can be a bit tricky. I have it working that way, using PWM to control the reference outputs. Run-up with SW and interrupt and the rundown part with HW timing using the trigger function and toogle mode. It is still some hassel to set up the next step in time and causing some delays and not all of the STM32 support the internal comparator as trigger source.
When using just the comparator and slow slope, it would make sense to make the slow rather small. The Keitley2000 already uses 1/128 for the small slope.

The last curve for the linearity looks already quite good.

[macaba]

Confirmation of OPA140 CMRR (OPA140 configured as unity gain buffer. DMM measuring input-to-output. Measured CMRR = 142dB.)

[julian1]

The previous proxy INL chart was for 80k/40k for sig/ref input resistors.

When signal input resistance is cut from 80k to 40k, input-short noise is basically halved. Now around 250-350nV RMS 10NPLC.

But there is a bit of a cubic shape present. This is strongest on the positive side (affected more by bias). Ratio of up/down var phases here is something like 20:1 at >10V.

If 50k/40k sig/ref is used instead (incidently what the 3458a uses), the response is much flatter, albeit a slight non-linear shape is still detectable, The up/down var ratio is much less extreme at the Vinput bounds - something like 6 : 1.  But noise is also higher.

The input resolution is currently around 128nV.
Using a slope amp with 2k/20k.

I think I prefer the lower noise and matched TC, of 40k/40k for sig/ref versus 50k/40k. But it may need some software correction of non-linearity.