AD4630-24 new SAR ADC from Analog Devices

[KT88]

There is a new SAR ADC in pre-release from Analog Devices:2MSPS, 24bits, +/-0.9ppm max INL...
https://www.analog.com/en/products/ad4630-24.html#product-overview

Cheers

Andreas

[antintedo]

What is even more impressive, the typical INL is just 0.1ppm, even for a single ended input.
Noise seems a bit high in comparison to the best SD and SAR ADCs.

[KT88]

Noise at full bandwidth can't be compared directly. A comparison at 1Hz (NSD: −166 dBFS/Hz typical) would be a meaningfull comparison / FoM. Combining the two ADCs would score additional 3dB...

[Kleinstein]

The higher frequency noise looks good. For the lower frequency one would have to see in real life. There may of may no be sifnificant extra /1f noise at the reference input and maybe correlation.

For the linearity don't forget the input buffer. It is not that easy to find a buffer with so little INL.

Another impressive point is the power it needs. Just from the ADC power it would fit battery operation.

[KT88]

No dedicated driver needeed in many cases - it takes only 600nA input bias current at DC.

[Echo88]

Very impressive INL, but the package... 

[jbb]

Yowza!
Dynamic range at full sample rate is allegedly 106dB, ie around 17 bits.

Package is 0.8mm pitch BGA, which is a bit inconvenient but not terrible. I suspect it could be broken out on a 4 layer PCB without going to fancy PCB processes.

(I did a design in my last job with a 0.4mm pitch part and that was really annoying to prototype.)

[coppercone2]

lol, they need to make a grid on top of the chip so you can solder it upsidedown if you wanted to with direct connections between the pads so you can probe them, the whole BGA thing is ridiculous

like if the chip connection package was 3d metal printed with a good sintering machine or whatever after the die was made. then I would hate them less if you can probe them with fine needles or even put parts ontop of the chip deadbug style
The technican is really being screwed over hard by like 0.5cm^2 of copper sheet conductors

[KT88]

The pinout isn't all that bad...the inputs are situated at an outer row (1) surrounded by GND-pins. The interface pins are also 1st and second row (7+8) to the edge. Placing some test points close to the package still gets you closeer to the die than in any other 64-pin package.
To get to such specs a more traditional package would possibly result in slightly inferiour specs...

[chickenHeadKnob]

The pinout isn't all that bad...the inputs are situated at an outer row (1) surrounded by GND-pins. The interface pins are also 1st and second row (7+8) to the edge. Placing some test points close to the package still gets you closeer to the die than in any other 64-pin package.
To get to such specs a more traditional package would possibly result in slightly inferiour specs...

QFN64 with .5mm pitch would be much better for us hobby peeps, and it can't be all that bad for lead inductance. I wish they offered in both package styles so we could see the performance difference (if any).

[arcnet]

The pinout isn't all that bad...the inputs are situated at an outer row (1) surrounded by GND-pins. The interface pins are also 1st and second row (7+8) to the edge. Placing some test points close to the package still gets you closeer to the die than in any other 64-pin package.
To get to such specs a more traditional package would possibly result in slightly inferiour specs...

And this ADC has even the capacitors integrated... 2 uF for the reference, 1 uF for VDD5 and VDD1_8 and 0.2 uF for VDDIO.
IOGND and GND are shared. Many (prototype) pcb manufacturers have 0.1 mm width and spacing nowadays as standard so no problem and for prototyping one might get even away with simple vias as pads (0.2 mm drill and 0.1 mm annular ring) and solder them from the bottom.

[MiDi]

Nice ADC, anyone evaluated this specimen already?
Macaba got 0.5uVpp at 30SPS.

[macaba]

Nice ADC, anyone evaluated this specimen already?
Macaba got 0.5uVpp at 30SPS.

There’s a good chance this figure is wrong, it might be a little higher, maybe towards 2uVpp. (Aligning with datasheet better.) Evaluation is still ongoing…

[KT88]

If power is not constrained it only makes sense to run the ADC at full sample rate and use the internal (up to 2¹⁶ decimation rate) or an external filter to get to the desired bandwidth and dynamic range. A LPF can reduce HF noise sufficiently that nothing of that is folded back into the band of interest. Paralleling both ADCs would gain another 3dB of DR...

[macaba]

There’s a good chance this figure is wrong, it might be a little higher, maybe towards 2uVpp. (Aligning with datasheet better.) Evaluation is still ongoing…

Managed to track down the discrepancy in the input-short noise figure that I mentioned:

A. 2MSPS, microcontroller averaged x32768 = 2uVpp
B. 2MSPS, onboard averaged x32768 = 0.7uVpp

(the number that MiDi posted at 0.5uVpp is using onboard averaged x65536, however I don't have enough uC memory to manually average that many samples from a DMA buffer)

In terms of DIO traffic (as a possible reason for the increased noise)
A. 32768 CNV pulses, 2 channels of 16 clocks of DDR, readback per CNV.
B. 32768 CNV pulses, 2 channels of 16 clocks of DDR, single readback after all CNV pulses.

As a further data point - I combined A & B (onboard averaging, with readback every CNV pulse, using SYNC bit to determine updated sample) and sure enough - higher noise, back at around 2uVpp. I suspect part of this will be extra noise on the die, and most of it will be poor PCB layout/decoupling.

Adds a little challenge for me - how to get 1PLC of samples with only the 2^n onboard averaging options.

EDIT: I'm now reasonably certain this is an issue with layout rather than any deficiency with the part itself.

[Kleinstein]

Some interference from the data transfer effecting the ADC is possible. So it may help to have at least some on board averaging to reduce the data rate.

To get 20 ms seconds averages, one would need 40000 samples at MSPS. This could be 64 samples averaging in the ADC and than 625 fold averaging in the µC.
Alternatively one could use a different, slightly lower frequency, e.g. so that 32768 fold averaging get you 20 ms.
A 3rd way to get effictive mains hum suppression is to use a little reduced weight to the samples at the start and end and a wider data window, a little similar to what most SD ADCs do. A slightly smoothed out start and end has some positive effects a little off exact 50Hz multiples and only needs a little more time and processing.

Just Averaging of the data does not need memory for the whole data. One could use something like a circular DMA buffer and pocess the data while they come in. With a reduced data rate from some averaging already in the ADC this should be doable.

[MiDi]

Avg of 1024 in ADC and 1953 in µC will give near 20ms/1PLC@50Hz mains.
For comparison DMMs running @1PLC with AZ give one value every 2PLCs, the AD4630-24 runs AZ for each reading.

What are the corresponding AC RMS values?
Would be nice if you would publish the raw data 

Chances are if there is interference, it is from the reference, not much to improve with input short to GND close to the pins.

[Kleinstein]

With a shorted input the reference should not have very much effect on the noise. High frequency interference could still come through though.
When measuring a non zero voltage, there may be some additional noise from the reference, but also a little ADC internal.

For the noise it may be interesting to do an FFT on the data, to see if there is 1/f noise. To reduce the data rate maybe with some initial averaging in the ADC.

[fluxgate]

Please note, these SAR ADC's are High Speed devices, due to aliasing they will pickup everything up to hundreds of MHz at the analog Inputs and digital IO. I really recommend using Delta Sigma for  Low Frequency / DC measurements ans low noise nutting.

[KT88]

I really recommend using Delta Sigma for  Low Frequency / DC measurements ans low noise nutting.

Which one?

[coppercone2]

Please note, these SAR ADC's are High Speed devices, due to aliasing they will pickup everything up to hundreds of MHz at the analog Inputs and digital IO. I really recommend using Delta Sigma for  Low Frequency / DC measurements ans low noise nutting.

You need some filters.

If you want to learn more, I recommend a SAR adc. You have more samples to play with, for implementing codes.. and you get a faster response on the work bench.

[Kleinstein]

These new SAR are quite good with the linearity - this is at least on paper. The fast ADC also needs a fast driver and the driver may contribute to the INL.

There are alternative SD ADC, that can also get quite fast, like the AD7175.

Even the SD ADC need some filtering at the input as they internally also sample the input - the requirements are still a bit lower there and especially no short AA filter needed.

[macaba]

I really recommend using Delta Sigma for  Low Frequency / DC measurements ans low noise nutting.

With 18nV/rHz noise density and 0.1PPM INL, along with many other good specifications/features, I don't think there's a delta sigma that gets near the AD4630-24.
(Not to imply it's the DS technique that's the issue, just the implementation limits)

[MiDi]

I really recommend using Delta Sigma for  Low Frequency / DC measurements ans low noise nutting.

I really recommend using Multi Slope for Low Frequency / DC measurements and low noise nutting. 

Some more details:
https://ez.analog.com/webcast-qa/2022-webcasts/1-11-2022-bullseye-transforming-the-precision-narrow-bandwidth-design-journey/m/file-uploads/1944/download

Attachments taken from the presentation.

What we can expect in future:
https://analogdevicesinc.github.io/no-OS/ad463x_8h.html#a081c378bd980443c3684ee785d69512d

[Kleinstein]

Doing a high rate of oversampling with an SAR ADC is not that different to an SD ADC. With the very good INL the AD4630 also gets interesting for oversampling and use with lower speed. The chip already has provisions inside for this. One could even consider to add some intentional ditherring signal to imporve on local linearity a little.
To keep the data rate low and this way to reduce the effect of coupling, it is a good idea to some averating already inside the chip.
One may still need a fast and very linear driver.

[fluxgate]

Sorry, I did not want to say, that you can't get a clear fft out of SAR ADCs or that they are not useful for low frequency stuff.
In comparison to the AD7177 for example, these chips have a wildly different aliasing behavior.

The AD4630 has a -3dB Bandwidth of ~70MHz, this means that it heavily relies on Analog Filters and EM shielding, otherwise digital filtering gives you exactly nothing in the passband.
Of course you can get a very impressive Performance with this ADC, however it's not that forgiving compared to the AD7177.

So, I see no sense in using this chips to measure 1/f noise, while there are better suited Delta Sigma ADCs around.

[Kleinstein]

Chances are the AD7177 would also react from aliasing in the 70 MHz band, maybe a little less than the SAR type chip, but not that significant. Both need AA filtering. The main difference is that with the SD chips the AA filter is usually just passive RC and can have a relatively low cross over. With a fast SAR ADC one usually wants the AA filter to start later (e.g. like at 500kHz) and than would need a steeper filter. When using oversampling and a lower frequency for the AA filter the difference is not that large. Both chips need a careful layout and a good (fast) driver.

The main point for the AD7177 is the easier to solder footprint and likely slightly lower price.

[macaba]

Bit more data attached. It would be interesting to see if the eval board shows the same effect.

[tszaboo]

You absolutely need to drive SAR ADCs with low impedance drivers/opamps. There is a switched capacitance on the input, and you need to be able to charge it within a fraction of the sample time within half of the LSB (step response). So you have a very high speed driver in front of it, otherwise you have nasty INL errors. They put a ADA4896 as example, an OPAMP with the GBW of 230MHz for a reason. You can also kiss goodbye to the DC accuracy if you use this driver, offset voltage is 500uV. And then you need to make sure about aliasing, drive the reference pin with the same care, as an input (because it is an input) and other issues. And the fact, that you have no way to analog debug your system because nobody makes tools to see 1 LSB errors in a 20+ bit system even at 1 MHz.

[KT88]

@macaba: it looks like some digital- or RF signals create alias signals in the off-chip averaging example. It would be interesting to see your layout...

@tszaboo: Yes, SAR converters are demanding when it comes to the input driver. A shorted input however qualifies as low impedance source, if not screwed up in some way.
The AD4630 features a precharge cycle which charges the sample cap to the previous sample (p.20). As long as the signal frequency stays low, the drive requirements are quite relaxed. However, the data sheet still recommends fast amplifiers (p.23).

[Kleinstein]

The demands on the driver are not that much lower for the very low noise SD ADCs. These also sample the input with a capacitor at quite some rate. Chances are that in both cases the actual INL depends also on the driver and the reference driving part.

[fluxgate]

@tszaboo

For highspeed 20+ Bit Systems you can use fft and pure sine sources.
That way you can easily and very fast detect bit errors and verify overall system Performance.
The most difficult part is to find use cases for these systems.

[KT88]

@Kleinstein:
This ADC frontend is different to previous ones. So far the ADC driver had to provide the full charge to the sample cap, starting from zero. This sample cap will be restored to the state of charge of the previous sample - the driver has to provide only the difference. For slowly changing signals this means a substancial reduction in driving current.
The downside is that the situation changes for mux'ed systems and high frequency, large amplitunde signals - the ADC would still work though....

[fluxgate]

If you want to measure DC you can use a Big (~5uF) filter Capacitor in front of the ADC, then you don't need a highspeed opamp at all. Just look at the ltc2508 eval board. If I remember correctly that's how the DC specifications are measured.

I really don't think the AD7177 has the same aliasing issues, as it's intended for much lower frequency, it can have better internal filter. And from the needed Clock Frequency (16 MHz) I'm just gonna assume that it has higher internal sampling Rate.
If you take a look at the AD7177 eval board and Datasheet, they do not care about aliasing, Eval Board RC Filter Frequency is ~35MHz.

However I'm no Delta Sigma Expert and it's been a while since I've had the AD7177 at Hand, so it would be nice if someone with an eval board and signal generator would try it out.

[MiDi]

Bit more data attached. It would be interesting to see if the eval board shows the same effect.

Thanks macaba
On the timeseries for Manual avg (grey) one can spot some drift upwards.
Interesting that Manual shows some 1/f noise, maybe related to the drift.
Any idea where the peaks ~11Hz & 22Hz originate from?
How do you extract rms voltage noise frequency density from timeseries?
How does your test setup look like: metal case, SPI isolator, battery powered PSU?

[KT88]

It would be interesting to see the layout. The data look like a result of a split-ground setup which usually cuases digital noise to interfere with the ADC core... just a hunch.

[macaba]

On the timeseries for Manual avg (grey) one can spot some drift upwards.

Yeah, makes me wonder what the auto-zeroing inside the ADC is actually doing. Also - the constant offset between the two traces?! Maybe still beneficial to have mux in the front end to do occasional zero measurement.

Any idea where the peaks ~11Hz & 22Hz originate from?

Nope. I suspect that in a run of 32768 samples, there will be a sample that is a massive deviation that drags it down/up. Note: I used the ADC test mode (where it outputs a constant value) to check that it isn't a glitch on the flexSPI readback.

How do you extract rms voltage noise frequency density from timeseries?

I have an NSD estimator algorithm that I have validated previously (to ensure the amplitude is "correct"). Uses multi-taper spectral estimation with discrete prolate spheroidal sequences (yes, a mouthful). It provides slightly better spectrums for the same amount of input data when compared to the traditional Welch method, not really enough of an improvement to justify it, it was just an intellectual curiosity for me.

How does your test setup look like: metal case, SPI isolator, battery powered PSU?

No metal case (tried it in my shielded steel experiment box, no change), no SPI isolator (only level translator), USB to laptop (switching laptop between AC and battery didn't make a difference). The analog supplies are powered from 9V battery, digital supplies from USB connection.

The data look like a result of a split-ground setup

Single ground-plane. As this is a BGA package, every ground pin goes through via to ground plane whereas I note, with interest, that the eval board uses solid copper planes directly under the BGA. I may try that, despite being against BGA-layout convention (would also mean double copper thickness compared to plane on internal layer). BGA fanout attached for your intellectual curiosity.

[KT88]

Thanks for sharing the layout. It looks like the groundplane doesn't continue underneath the digital interface traces. Do you use a different groundplane for the micro/FPGA?

[macaba]

Thanks for sharing the layout. It looks like the groundplane doesn't continue underneath the digital interface traces. Do you use a different groundplane for the micro/FPGA?

Ground plane is the dark red background, covers the whole board. The green(?) is power supplies/ref. RP2040 micro is off-board (on the "Pico" dev board) with relatively poor ground connections (single ground wire). Now that I've confirmed the RP2040 PIO to be a perfect match for this ADC, I'll probably do v2 with onboard RP2040.

[miro123]

A. 2MSPS, microcontroller averaged x32768 = 2uVpp
B. 2MSPS, onboard averaged x32768 = 0.7uVpp
Adds a little challenge for me - how to get 1PLC of samples with only the 2^n onboard averaging options.

Are you using STM32, if yes you can consider using stm32H7 - their AXI RAM is up to 512KB

[TiN]

If you can buy it Plane under BGA often used for higher power devices acting as heatsink too.

[CurtisSeizert]

Bit more data attached. It would be interesting to see if the eval board shows the same effect.

I just got things working with the eval board. The eval software times out on long acquisitions, so I could only get 800 samples for an fft.  This was taken with shorted inputs.  Sampling rate was 2 Msps, block size=32768.  The fft x-axis scaling seems to be calculated without taking into account sample averaging, so you need to divide by 32768 to get the actual frequency (divide by 65536 for the fft with that block size).  The "peak" with a dot above it corresponds to about 13 Hz.  The output is 30 bit codes, so peak to peak in this trace is about 1.3 uV over 13s with an offset of -10.6 uV.  With block size of 65536 and 400 samples, peak to peak is just under 1 uV.  The fft peak it labels as the fundamental there is 1 Hz.

Curtis

[macaba]

Thanks for joining in, it's good to get your input.

I see from "AD4630-24 trace.JPG" that it's 130 counts peak-peak, with offset of -1140 counts. I calculate that as being 1.2uVpp with 10.6uV offset (N*(10/2^30)). We are both getting values better than the datasheet value of 1.8uVpp.

Does the input data into the FFT have the mean subtracted to reduce the effect of DC? It's a shame the software isn't allowing longer captures to get a cleaner spectrum.

[KT88]

Better results than secified in the DS are no surprise for such a high DR ADC. Testing to such a high degree of certainty would come at painful price premium...

[CurtisSeizert]

Thanks for joining in, it's good to get your input.

I see from "AD4630-24 trace.JPG" that it's 130 counts peak-peak, with offset of -1140 counts. I calculate that as being 1.2uVpp with 10.6uV offset (N*(10/2^30)). We are both getting values better than the datasheet value of 1.8uVpp.

Does the input data into the FFT have the mean subtracted to reduce the effect of DC? It's a shame the software isn't allowing longer captures to get a cleaner spectrum.

You are right. I did not multiply by the FS voltage.  I knew those numbers looked too good to be true, especially with the board flapping in the breeze.  I will see if I can export the raw data from the capture to perform the fft myself - it is not clear how that spectrum is calculated in the software.  I will see if I can get around the USB timeout for a longer capture.

[macaba]

A. 2MSPS, microcontroller averaged x32768 = 2uVpp
B. 2MSPS, onboard averaged x32768 = 0.7uVpp

EDIT: I'm now reasonably certain this is an issue with layout rather than any deficiency with the part itself.

Quick update, using fresh AD4630 on v2 PCB with improved layout.

A. 2MSPS, microcontroller averaged x32768 = 0.62uVpp
B. 2MSPS, onboard averaged x32768 = 0.65uVpp
(10 second sample block [i.e. 30.5 - 0.1Hz] peak-peak values averaged over 15 minutes [90 blocks])

Improved layout has solved the additional noise issue I was seeing. It's interesting that the microcontroller averaging is slightly better (it's a very stable 2 decimal places, no margin of error issues here), I suspect it's due to the loss of bits in the onboard averaging filter.

Now to move onto other interesting tests and NPLC averaging lengths...

[MiDi]

Little brother with 1CH is out: AD4030-24

[macaba]

Little brother with 1CH is out: AD4030-24

Interesting!

I think as it's the same package, might as well use the 2 channel version - a single-ended front end to avoid the difficulty of getting a differential resistor matching >140dB (one of the major challenges of HPM7177) is easiest, and having the 2 channels in parallel from the same input gains back dynamic range where it is lost by not having fully differential front end.

[Kleinstein]

I don't think one need good resistor matching for a differential front end. Ideally the 2 sides are matched, but if not this mainly reduces the input ranges a little. Normally one does not care about things like 1% of the full scale range lost or 0.01% higher noise from matching to only 1%.

[iMo]

Is there a feasible option other than the LT5400 for the input dividers with SAR/SD ADCs (differential inputs)? I've built myself a simple 10V voltmeter (w/ 24bit SD, single 10V input) and I do not see any feasible variant than a floating opamp + LT5400-8 9k/1k.. Currently I have there an old noname thick film 1:10:100:1000.. divider, but its TC is something like 70ppm/C.. 

[Kleinstein]

There are alternatives for the input divider. It also depends on how the meter is build - there are quite some alternative with an ADC that has a differential input. The simple way is just a divider at the input and than a buffer to the ADC in quasi single ended mode. So a bit like the handheld meters.
The input divider could also be with less steps and than fine switching via gain after the divider.
Other versions can have buffer - divider - buffer to allow high Z mode for more than 2.5 or 5 V. Dirving the ADC with a differential signal with 2 differential amplifier with a gain < 1 as in the HPM7177 is another option, though also with some downsides.

The ORN and MORN resistor networks are somewhat similar to LT5400 with somewhat lower specs and a few different resistor values availabel.
One may not need a 10:1 divider, but other ratios (e.g. 3:1 or 4:1) can work as well, that could be obtained from a few equal resistors.
For the input divider for some 100 V or so a chain of equal SMD (thin film) resistors is an option too.

[iMo]

Yep, we had the discussion on the input stages for differential SAR/SDs in past (with spice simulations), the only critical part imho is the resistive divider, however (the values do not matter, except the lower side should be around 1k, otherwise I see a larger stddev in my SD with no buffer after the divider). Would be great to have the latest update on such cheapo resistor dividers alternatives with ratio TC below 13ppm/K (but in a different thread perhaps)..

[macaba]

Attached is updated NSD.

The datasheet says "1/f noise is canceled internally by auto-zeroing. Noise spectral density is substantially uniform from dc to fs/2." - hmmm

[Kleinstein]

There is some 1/f noise, but still not very much. It is somewhat comparable what they measured at Cern for LTC2378, AD7177 and similar.
The measurement may still include some input amplifier. Another possible source of 1/f noise are thermal fluctuations.
Ideally one may still need some external auto zero mode in the front end.

[Paskis]

Hi,
I've just acquired the ADC with the Zedboard in order to test the performance. The thing is that I cannot evaluate the effective bandwidth 'as I was testing with a sine signal and when I go above 500 kHz the Peak-to-Peak level in the signal heavily drops. I've checked and the input signal was pretty much stable so It has to be the ADC. Any idea what it should be? I would really apprecaite some help.

Thanks

[MasterT]

My curiosity pushed me to  download design files, and what I see right after SMA connector?
Correct, anti aliasing filter R=10 Ohm, C=0.01 uF. Seems o'k,  cut off about 1.6 MHz, only C has impedance 31 Ohm at 500 kHz, quite low even to drive by SG with 50 Ohm default output imp.

 I 'd recommend also to check  RC at the output of OPA driver.
 It's enormously huge load for most OPA that  I know, to drive <100 Ohms, especially if requirements for ultra low noise & low distortion very strict the same time. AD realised that they don't have such extra quality OPA in their possession, so RC filter is way off  in frequency 4.8 MHz, : C = 1000pF ( 318 Ohm !) .   

I see in DS for ADA4896-2  OPA is capable to drive 100 Ohms, Fig. 18, but  THD is hardly gets to -65 dB at 500 kHz!

 I had bad experience in the past with ads1256, when I first time  came to conclusion  that whatever beautiful numbers they put into ADC DS, check if you  can buy OPA that capable to drive this bitch, or if such OPA even exist.

[KT88]

To address a missunderstanding: The R-C in front of the ADC input is not the AAF. It is part of the buffer. The C has to provide sufficient charge to the sample cap and the (low-value-) R has to recharge the cap between two samples to less than an LSB.
This is the reason that ADC drivers exist that can provide up to more than 100mA. They are also fast enough because most regular opamps are also too slow to settle within a few hundreds of nanoseconds to the desired fraction of an LSB.
Another consideration is the kind of signal that should be sampled - many applications like audio or many sensors don't require high frequencies AND high amplitudes at the same time...
The AD4630 and the newer AD4030 have a novel frontend that recharges the sample cap to the previous voltage which reduces the (average) input current significantly - except the input frequency comes closer to the sample frequency - in that case it behaves more and more like a classic SAR-ADC...

Cheers
Andreas

[MasterT]

I know what you mean, but it doesn't change anything. The fact is, that RC filter in front of the ADC is must be there,
other-ways non-linearity would be much worse. And nothing tells that this filter can't be AAF as well, double purpose. 

And after that, there is No 24-bits 2 MSPS low noise ADC.
It's ether 24-bits OR 2 MSPS OR low noise.

At DC & low frequency end, see Figure 17 - THD crosses a line -120 dB at 4 kHz, so actually we have 20-bits and 4 fake-bits.
It's not necessary to sample 4 kHz with 2 MSPS, any SD ADC ($4 MCP3561) would perform much better at 4 kHz on both accounts: Noise & THD.

Excellent linearity in Figure 12 likely at DC voltage end, because I don't even see in Figure 17 THD level ever goes below -140dB to get 0.1 ppm. Again, you don't need 2 MSPS for DC.

There only corner where high sampling rate is justified/ necessary - high frequencyies at the input ( 10 kHz - 1 MHz), and AD is saying: don't even dream about 0.1 ppm - 60 pF (!!!) input sampling capacitor would ruin whatever already mesarable pictured in Figure 17 down to
-65 dB THD, where only 12-bits makes sence, and 12 fake-bits follows to foul naive  idiots.

[KT88]

And nothing tells that this filter can't be AAF as well, double purpose.

Not really - The R-C combination needs to have certain values: The C needs to have sufficient capacitance to provide enough charge to the sample cap and the R plus the buffer amp need to be able to recharge the C in time. This limits the corner frequency of the R-C combination to a very narrow range. Also a first order R-C filter has usually a too shallow roll-off in the stop band...

And after that, there is No 24-bits 2 MSPS low noise ADC.
It's ether 24-bits OR 2 MSPS OR low noise.

You miss the point of such an ADC- it is meant to be oversampled to gain DR for lower frequency signals down to DC signals. The figure of merit is the NSD of -166dB/Hz in this case. This means it performs almost as a 28bit ADC at 1Hz oversampled...

so actually we have 20-bits and 4 fake-bits.

No again: These bits are called noise bits. They enable to average the signal when oversampling - if they were fake the oversampling won't work...

Again, you don't need 2 MSPS for DC.

Yes, you need them - see above.

There only corner where high sampling rate is justified/ necessary - high frequencyies at the input ( 10 kHz - 1 MHz), and AD is saying: don't even dream about 0.1 ppm - 60 pF (!!!) input sampling capacitor would ruin whatever already mesarable pictured in Figure 17 down to
-65 dB THD, where only 12-bits makes sence, and 12 fake-bits follows to foul naive  idiots.

Be carefull who you call idiots... I would strongly recommend to you to learn more about sampling theory - You'll find a lot of material at TI or Analog devices for example... It isn't as simple as you think.

Cheers
Andreas

[iMo]

There is a test jig for both ADCs in LTSpice, you may try to play with it (it simulates the input sampling capacitor's transients as well, AD says)..
You get the 24bit digital word out of the simulation too - see below..

[MasterT]

Quote
And after that, there is No 24-bits 2 MSPS low noise ADC.
It's ether 24-bits OR 2 MSPS OR low noise.

You miss the point of such an ADC- it is meant to be oversampled to gain DR for lower frequency signals down to DC signals. The figure of merit is the NSD of -166dB/Hz in this case. This means it performs almost as a 28bit ADC at 1Hz oversampled...

>>> Don't be stupid, if oversampling is involved than sampling rate is divided, 1 ksps with block size 2048.

Quote
so actually we have 20-bits and 4 fake-bits.
No again: These bits are called noise bits. They enable to average the signal when oversampling - if they were fake the oversampling won't work...

Quote
Again, you don't need 2 MSPS for DC.
Yes, you need them - see above.

>>> Read above, SD ADC perfectly outperform in low sampling rate area, and oversampling is exactly apply here.

Quote
There only corner where high sampling rate is justified/ necessary - high frequencyies at the input ( 10 kHz - 1 MHz), and AD is saying: don't even dream about 0.1 ppm - 60 pF (!!!) input sampling capacitor would ruin whatever already mesarable pictured in Figure 17 down to
-65 dB THD, where only 12-bits makes sence, and 12 fake-bits follows to foul naive  idiots.

Be carefull who you call idiots... I would strongly recommend to you to learn more about sampling theory - You'll find a lot of mateial at TI or Analog devices for example... It isn't as simple as you think.

>>> Get lost, you have No idea who write app. notes for TI & AD. Will put your in ban list

[iMo]

The question here is perhaps how good are those AD4630-24/AD4030-24 for a "DC" measurement - compared to those ADS1263/AD7177/LTC2500-32 we collected in past and which are still waiting in our shoe boxes to be soldered into a nice PCB 

[KT88]

Don't be stupid,

Don't be insulting...
Everybody in this forum has a different level of experience from beginner to expert. We are here to learn from each other and share our work or hobby challenges and solutions.
There is nothing wrong about not knowing stuff - everybody can learn more...

When I mention "oversampling" in the metrology section, I anticipate a somewhat experienced audience that knows at least briefly the trade-offs of oversampling - hence I didn't explain it furthermore.
Oversampling is also not limited to the built-in features of a specific ADC -it can be done in a processor or FPGA. It is also not limited to powers of 2.

The NSD of -166dB/Hz is from the data sheet - if it is wrong you could report it to Analog Devices if you like...

I mentioned TI and Analog because if you google for oversampling or other terms used with ADCs they come up first usually. I also stated "for example" which means that these are not the only resources, of course.

Cheers

Andreas

[KT88]

The question here is perhaps how good are those AD4630-24/AD4030-24 for a "DC" measurement - compared to those ADS1263/AD7177/LTC2500-32 we collected in past and which are still waiting in our shoe boxes to be soldered into a nice PCB

This is indeed the most interesting question as until now SD- or several flavours of multi-slope converters were superiour over SAR converters.
The INL spec of 0.1ppm is very promising as well as the (oversampled-) dynamic range.

Cheers

Andreas

[Kleinstein]

The INL is not directly limiting the useful resolution. So 24 bit resolution can still be there even with 100 ppm INL. With higher resolution it is quite normal that the INL error can be considerably larger than 1 LSB. Especially the tested INL specs hardly can be better than 1 LSB as there is not enough time to do a full histogram test. The noise can be a limiting factor to how much INL testing can be done in a reasonable time. Resolution better than the the INL limit is still quite useful.
With 24 bit ADCs it is quite common to find some of the bits burried in the noise and an effective resolution that is lower. There is not need to have the quantization noise as the dominant noise source.


The higher THD of the amplifier only applies to the case when there is a large amplitude signal present - with lower amplitude at the higher frequencies and other signals at lower frequency things can become quite a lot better.

With the anti aliasing filtering it depends if you have a signal source that is more in a time domain or more in the frequency domain. So it depends on the application. In some cases it is more appropriate to look in the frequency domain and one needs an AA filter and maybe low THD even for a large signal. In other cases one cares about the settling time, but not about aliasing, as one is not interested in the signal between the sampling times, but the voltage at a give time. Quite often there is no MHz range full scale signal, but a more DC background and only moderate amplitude at higher frequency for the details. The THD can also have transient parts that does not matter after settling and one can profit from not haviing an AA filter to slow doen settling.


The MCP3561 and many other SD ADCs have relatively similar driving requirements to the SAR ADCs, as there is actually also capacitove sampling. With a poor driver a SD ADC INL can also suffers. Similar the reference driver may need extra care. For the high performance ADCs they should note the drivers used for the specs - the performance limits may very well be due to the drivers.

The MCP3561 noise and INL performance are still inferior at 4 kHz compared to the AD4630 with averaging. The same advantage from oversampling also applies to the SAR ADC. The comparison is a bit tricky as both give different quantities. The AD4630 gives some 136 dB DR for 1000 fold oversampling, that should about compare to an OSR value of 2048 or 4096 with the MCP3561 with some 3-4 µV of RMS noise  wich would be around 120 dB DR. So about a 16 dB advantage for the AD4630.

The MCP3561 data-sheet shows the 2nd harmonic (but not the higher ones) for a 1 kHz test signal, that looks good. However the INL curve shown is more of the point symmetric type that would mainly create odd harmonics. So the test at 1 kHz is missleading: -130 dB for the 2nd harmonic does not rule out a THD worse than -100 dB.
Looking at the THD is also mainly looking at the soft INL and not so much at more localized issues (e.g. idele tones), that may be the limiting factor to the INL.

There is no need to sample a 4 kHz signal with 2 MSPS, but one can and than use digital filtering to remove the unwanted higher frequency noise. Oversampling simplifies the AA filter.
With oversampling and digital filtering the AD4630 actually gets quite similar to an SD ADC, just with a SINC1 filter.
 

[KT88]

There is no need to sample a 4 kHz signal with 2 MSPS

Yes and no... it would help to lower the noise floor if a higher (than Nyquist) sampling rate is chosen.
There is also a significant difference to SD- and previous SAR converters which is the pre-charge feature:

The acquisition circuit on each input pin is also
precharged to the previous sample voltage, which minimizes the
kickback charge to the input driver.

DS, p.20, converter operation section.
An equivalent circuit for the input can also be found on p.20.
This means that there is barly any kick-back for a steady state signal - something that hasn't been done so far.
As a result in (more or less) DC-applications the driving part is quite easy and doesn't introduce significant harmonics...

Cheers

Andreas

[macaba]

I often see statements along the battles lines of "SD vs. SAR" which doesn't make much sense to me.

As a more generic abstraction that is useful to a front-end circuit designer, it comes down to:
capacitive-sampling input vs. resistive input
and the ADC's noise level/linearity that is mostly a function of the quality of implementation of a technique (and the semiconductor process it is made on), not the name of technique.
It might be true to say that before the AD4630, there weren't many competitive SAR ICs when compared to SD ICs.

For an excellent explanation of the merits of the two types of input, pages 29-31 of AD4134 datasheet is good ("THEORY OF OPERATION").

(Footnote: ADI took the AD4630 one step further with the precharge mechanism which blurs the lines a bit).

[KT88]

I often see statements along the battles lines of "SD vs. SAR" which doesn't make much sense to me.

I agree - it mostly depends on the application. But sometimes like in the case of the AD4630 right now we see a shift in how the Architecture gains some advancements for certain applications.
It doesn't, by no means,  render other ADC topologies usesless...

[iMo]

The ~4y old LTC2500-32 is a SAR for example:
±0.5ppm INL (Typ)
104dB SNR (Typ) at 1Msps
148dB Dynamic Range (Typ) at 61sps
@200kHz input sig: SINAD 99dBFS, SNR 100dBFS, THD -106dBFS

[MasterT]

The INL is not directly limiting the useful resolution. So 24 bit resolution can still be there even with 100 ppm INL. With higher resolution it is quite normal that the INL error can be considerably larger than 1 LSB.

>>> Non sense for me. It does limit, anything below INL line is a fake, garbage to discard not bothering to push over data bus.
I'd prefer other way around, have 12/ 16-bits with better INL < 10ppm

The higher THD of the amplifier only applies to the case when there is a large amplitude signal present - with lower amplitude at the higher frequencies and other signals at lower frequency things can become quite a lot better.

>>> Drop this clowns wizardry, lowering amplitude you are losing SNR.
As I say:
24-bits - No 2 MSPS
2 MSPS - No 24-bits
Lowering SNR - No Low Noise.

With the anti aliasing filtering it depends if you have a signal source that is more in a time domain or more in the frequency domain. So it depends on the application......

>>> I don't understand what does this means. What I see is rough violation by AD common practices for test equipment: put a sticker if a module  poses a threat for external test SG or other test equipment  not complying with 50 Ohm input spec. And AAF 10 Oms & 10 nF may demage SG at 500 kHz.

The MCP3561 noise and INL performance are still inferior at 4 kHz compared to the AD4630 with averaging. The same advantage from oversampling also applies to the SAR ADC. The comparison is a bit tricky as both give different quantities. The AD4630 gives some 136 dB DR for 1000 fold oversampling, that should about compare to an OSR value of 2048 or 4096 with the MCP3561 with some 3-4 µV of RMS noise  wich would be around 120 dB DR. So about a 16 dB advantage for the AD4630.

>>> LNA at the input of the MCP3561 (TLE2027 50 nV/ sqrt(Hz) or similar would bring 40 dB. 
But I'd leave this discussion for another topic.

[Kleinstein]

The INL is not directly limiting the useful resolution. So 24 bit resolution can still be there even with 100 ppm INL. With higher resolution it is quite normal that the INL error can be considerably larger than 1 LSB.

>>> Non sense for me. It does limit, anything below INL line is a fake, garbage to discard not bothering to push over data bus.
I'd prefer other way around, have 12/ 16-bits with better INL < 10ppm
 

I also prefer INL lower than 1 LSB, but this is essentially not possibly with better than 12 bits. As long as the curve is monotonic (DNL < 1 LSB) the resolution is still usefull, especially as the INL error is the maximum error and this often applies to the upper / lower end of the range (like the extreme 10%) or a few special points.
Essentially all 24 Bit ADCs have an INL error larger than 1 LSB:  the 3458 DMM and the AD4630 are about the only ones were the INL is at least close to 1 LSB (at 24 bit). The input buffer for the AD4630 may limit that.

Especially with SD ADC it is common to give a 24 bit resolution, as the data are send in 24 data format. The noise is often higher and quite often the INL is in the 5 ppm range. With SD ADCs the numerical resolution is cheap and they can thus use the computer typical steps like 16 / 24 / 32 bit for the resolution. There is absolutely no need to have the quatization noise as the limit -  in the high resolution range it is more to the opposite: the data should be wide enough that the quatization noise is only a minor issue. So a resolution higher (at lest some 2-3 bits) than the ENOB is useful.  So with some of the better 24 bit SD ADCs one may wish for a few more extra bits in the result, though one can often get around this by reading faster and average externally.
The good INL is precious and a resolution better than the INL specs makes absolute sense - it makes little sense if the resolution limits the INL in this performance range.
Wanting INL better than 1 LSB made some sense in the old days at the very high speed with low resolution (e.g. 8 Bit  and > 1 GSPS), but even there the FPGA / data handling is usually no longer the bottleneck and an extra Bit of resolution is usually wellcome even the LSB is than smaller than the INL.

What I see is rough violation by AD common practices for test equipment: put a sticker if a module  poses a threat for external test SG or other test equipment  not complying with 50 Ohm input spec. And AAF 10 Oms & 10 nF may demage SG at 500 kHz.

Function generators and essentially all RF test gear does survive a short at the output. They don't need the 50 Ohms for protection, but to get low reflection and well defined performance. The rare cases (some RF power amplifiers) when a test gear does not like the reflections from a short or an open input there should be a warning on that instrument. They use the RF type connector on test boards also also for other signals - even more DC ones and without the usual 50 Ohm termination. The SMA connectors are just convenient and reasonable priced.

 

The MCP3561 noise and INL performance are still inferior at 4 kHz compared to the AD4630 with averaging. The same advantage from oversampling also applies to the SAR ADC. The comparison is a bit tricky as both give different quantities. The AD4630 gives some 136 dB DR for 1000 fold oversampling, that should about compare to an OSR value of 2048 or 4096 with the MCP3561 with some 3-4 µV of RMS noise  wich would be around 120 dB DR. So about a 16 dB advantage for the AD4630.

>>> LNA at the input of the MCP3561 (TLE2027 50 nV/ sqrt(Hz) or similar would bring 40 dB. 

An amplifier at the input does not improve the DR of the ADC. It can help for the total system, but the same also applies to other ADCs.
With that much noise, I very much doubt the amplifier would help very much. The input noise of the AD4630 is at some 18 µV RMS for 2 MSPS and thus around 18 nV/sqrt(Hz).
The TLE2027 gives a considerably lower noise (~ 3 nV/sqrt(Hz)) - still this only helps the system not the ADC directly and no way near 40 dB. It may provide 40 dB  of gain, but than the amplifier noise would limit the DR even more than the ADC.

[iMo]

What Kleinstein indicates above means - with enough ADC resolution even the larger INLs are acceptable, because you can correct the ADC results numerically. Small INLs are required when you have no capability to provide the numerical correction to the incoming data. INL is usually hidden in the noise and you have to process the incoming data first, otherwise you will not see the INL. With say 18uVrms noise you are at 100uVpp noise in the data, with say 2Vpp input that is XX times more than the INL..

[KT88]

One aspect is that a better INL is desirable because the INL won't be infinitly stable over temperature and other disturbing factors. Without total isolation from the ambient a 10-ish improvement should be possible (only an educated guess though).
Another aspect is that oversampling (averaging) is a trade-off between signal bandwidth and dynamic range. This is what happens when one chooses a higher number of PLCs with a 3458A (or other meters) the reading of the last digits gets more stable.
The rms noise in the 1st nyquist zone doesn't tell anything about the accuracy of the ADC. It can be orders of magniude higher than the INL. In fact the ADC cores have inentionally noisy LSBs in order to allow for a better averaging result. One reason for the noise of the LSBs is dithering, which blurs the DNL over a wide range of codes. The result of dithering together with a very random dither-code distribution achieves the high linearity of the samples even below 1LSB...

[MasterT]

What Kleinstein indicates above means - with enough ADC resolution even the larger INLs are acceptable, because you can correct the ADC results numerically. Small INLs are required when you have no capability to provide the numerical correction to the incoming data. INL is usually hidden in the noise and you have to process the incoming data first, otherwise you will not see the INL. With say 18uVrms noise you are at 100uVpp noise in the data, with say 2Vpp input that is XX times more than the INL..

I like to tweak /hack / overdrive dsp parts, adc and dac, but not with $200 boards.  Would expect clear explanation how each parameters defined, in what test conditions etc. W/o any speculation, what could be done or why I can't get same good pictures like in DS. I respect Microchip, for less ad on the front page.

And second, I'm sure AD already did numerical correction internally,  nothing to squeeze out when 0.1 ppm linearity speaks. Seen recently some TI products call it "background calibration" in the description. Technology I know since 1989, when it was invented for multi-slope ADC.

[KT88]

Would expect clear explanation how each parameters defined, in what test conditions etc. W/o any speculation, what could be done or why I can't get same good pictures like in DS.

Here you go: https://www.analog.com/en/education/education-library/data-conversion-handbook.html

[Kleinstein]

The AD data conversion handbook is great and shows quite a lot about the testing. However there are still a few somethwat open points, like the ADC drivers used and how and if the INL par the ADC dirver is included or maybe not.  The PCB iterations show that it is not just the ADC chip that matters, but as it looks like also the layout and other parts around the chip.
The same also applies to most SD ADC chips - even of they have a slower data rate, the actual input sampling can be even faster and more nasty to drive.

[KT88]

@ Kleinstein: I fully agree: there is much more to know about precision analog and mixed-signal circuit design. Another good read is the following:
https://www.analog.com/en/education/education-library/linear-circuit-design-handbook.html
In particular Ch.12 deals with PCB design.
Apologies for being a bit Analog Devices heavy but searching for Handbook scores a metric ton of material https://www.analog.com/en/education/education-library/op-amp-applications-handbook.html
Unfortunately or interestingly (however one looks at it) there is much more to learn...

[MasterT]

The AD data conversion handbook is great and shows quite a lot about the testing. However there are still a few somethwat open points, like the ADC drivers used and how and if the INL par the ADC dirver is included or maybe not.  The PCB iterations show that it is not just the ADC chip that matters, but as it looks like also the layout and other parts around the chip.
The same also applies to most SD ADC chips - even of they have a slower data rate, the actual input sampling can be even faster and more nasty to drive.

Right. It's competitive world, in between major players / companies as well as between countries / blocks. Cold war never stops, just went to a shadow for a while.
Though, when I see 60 pF, it rings me a bell of the "sabotage technology".  SD ADC has much lower sampling capacitance.
And it's still the question how AD takes Figure 17 if one best the best their OPA (recommended to use by AD) can't provide such performance even close.

Books the same shit, nobody in the sane state of mind would publicly disclose internal whereabouts theirs product.

[KT88]

OK, if the sample cap bothers you - there is a remedy: https://www.analog.com/en/products/ad7134.html?doc=AD7134.pdf#product-overview.
 

[iMo]

I like to tweak /hack / overdrive dsp parts, adc and dac, but not with $200 boards.

I would not expect from that board the same as from a 3458A. I do not know what you actually want to do with the board, but when targeting precision DC measurements I am pretty confident you will get flicker free 7.5 digits out of the board easily. Easily means - with something like 10-20 seconds "equivalent averaging time". I have here 2 boards (18y old AD 24bit SD eval boards) and it works that way.
With 0.6uVpp input noise at lowest possible sampling rate (as shown in previous posts) with say +/-2V ADC input range your 1LSB is 2/(2^23)= 240nV, and 0.6uV/240nV = 3. That is with shorted inputs where the noise of Vref does not apply, under real conditions while measuring say 10V DUT reference against your Vref, the noise in your data will be much higher, my bet you will see something like 3-6uVrms (the standard deviation in your data) when lucky, therefore you would need longer integration times to see flicker free 7.5digits. After you see that flicker free data you may start to compensate the INL, the TC and cope with other issues involved..

PS: .. like 61Hz "sampling rate" == 2MSPS/32768.. + the mcu averaging..

A. 2MSPS, microcontroller averaged x32768 = 0.62uVpp
B. 2MSPS, onboard averaged x32768 = 0.65uVpp
(10 second sample block [i.e. 30.5 - 0.1Hz] peak-peak values averaged over 15 minutes [90 blocks])
Improved layout has solved the additional noise issue I was seeing. It's interesting that the microcontroller averaging is slightly better (it's a very stable 2 decimal places, no margin of error issues here), I suspect it's due to the loss of bits in the onboard averaging filter.

[Kleinstein]

The relatively high sampling capacitance is kind of needed, because of the KT/C sampling noise limit. High performance SD ADCs chips (e.g. AD7177 or similar) of the switched capacitor type also need a relatively high sampling capacitance, though they can get away with a little less due to a higher sampling frequency. However this shifts the driving problem to even higher frequencies. With a switched capacitor ADC one kind of has to choose your poison: higher capacitance or high frequency sampling. As the capacitance on the chip is expensive it is not such a surprise the rather high conversion speed and oversampling is the way to get very low noise. In this view the the 2 MSPS raw conversion rate is still relatively moderate. I would not be surprisef to see even faster similar ADCs, possibly without acess to the raw data before averaging.

The extra precharge amplifier is already a way to reduce the kickback from the relatively large sampling capacitor. If the current pulse is reduces enough, one does not really care the actual size of the capacitors (it still effects the price though).
The idea is not totally new: the AD7768 SD ADC already has this in a similar way.

The way with fast conversions and than averaging makes absolute sense: it gives a flexibilty to use the same chip for different speeds and simplifies the AA filter. For the user it does not make that much difference if the input is sampled by an SAR or SD converter in the MHz range. It looks like the SAR type converters somehow, surprisingly get the better INL.

[KT88]

The noise floor stays the same regardless of the sample rate. The final result depends on the number af samples averaged.
The precharge of the sample cap removes a lot of the challenges with the input buffer. This is limited to low frequencies though because it only works for small deltas between two samples. For high frequencies and muxed inputs the pre-charge has no advantage...

[MasterT]

I did testing with ad7988-5, ad7693, ad7982, ad7984 modules  and non of them has cap at the input, only suspiciously low resistance (600||600 = 300) that I always removed before testing.

Some pictures posted here:
https://ez.analog.com/data_converters/precision_adcs/f/q-a/544153/eval-ad7982-pmdz-high-thd-3-level

It;s not only sampling cap that's trigger my 6-th sense , but also input AAF on evaluation module.
Since ADC has beautiful digits in DS for BOTH DC (linearity) & AC (THD) why someone would over complicate, actually de-rail any possibility to evaluate ADC with sine wave sources?
 Bla-bla-bla about RF, noise, etc not acceptable - jumpers cost nothing compare to IC itself.

[KT88]

Ok, now I see your point... This is just a generic EMI filter. As you can see in the schematic, there are a lot of optional parts in the circuit to allow you to configure the circuit to your needs. As pointed out in an earlier post, this ADC is more advantagous for lower frequencies down to DC.
Deleting or reducing the input caps won't be an issue if no noise is introduced through the setup of the signal source....

[MasterT]

My guess is,  uCPU numerical correction in ad4630 is the Only  difference from  AD798X product lines.

I'm also quite well understand that crunching data 2 MSPS / 24-bits  more efficient than 8 MHz / 1-//-4-bits (SD ADC like max11270 or mcp3561) in the noise reduction aspect.

 Though, if great Sisyphean labour /efforts were put into DC spec. improvement, why there is no noise reduction in the Reference path? What, noise spec. measured with inputs shorted? Still smells toxic , IMHO




 

[Kleinstein]

Reducing the reference noise is not that easy. The chip already includes some reference filtering for the higher frequency part. More can be done externally, but the typical large capacitors are more an external thing and it depends on the refrence used.

Measuring the noise with shorted input is kind of standard, as this case is easy to reproduce. Any other voltage needs extra effort and may introduce extra noise depending on the details of the implementation. Ideally one would have additional points, but testing such an ADC already takes long enough and the data-sheet are already quite long.

[MasterT]

Reducing the reference noise is not that easy. The chip already includes some reference filtering for the higher frequency part. More can be done externally, but the typical large capacitors are more an external thing and it depends on the refrence used.

Measuring the noise with shorted input is kind of standard, as this case is easy to reproduce. Any other voltage needs extra effort and may introduce extra noise depending on the details of the implementation. Ideally one would have additional points, but testing such an ADC already takes long enough and the data-sheet are already quite long.

1. Easy, not easy - who care if cost is not > 10% of the module?
2. Capacitors don't play any role here, since output impedance is very low and a few Farad capacitance wouldn't reduce 0.1-10 Hz at all. 
3. Don't care also for standard, absurd for me. Was trying to figure out noise level out of the DS FFT plot, but AD (intentionally?) doesn't mention FFT size, so can't compare with an experimental data I have for mcp & max SD ADC.  BTW, microchip DS about 100 pages, with complete description including internal architecture, and does indicate FFT sizes.

 

[KT88]

Something to consider: Both the LTC6655-5 and the show +/- 500nV peak noise at 10Hz bandwidth. This is +/- 0.1ppm peak. Further averaging like 100PLC would get it ever further down...
I don't think this leaves a lot to complain...

[KT88]

@MasterT: If we start to compare the AD4620-24 with the mcp3561, let's just compare Gain drift: 0.025 vs. 0.5 ppm/°C. That is a 20x difference or comparing apples with....potatoes

[iMo]

But the difference between the apples and potatoes plays no role with LTC6655-5 (max 2ppm/C) 

[KT88]

Sure - that's more a play for LTZ-/ADR1000...

[MasterT]

Something to consider: Both the LTC6655-5 and the show +/- 500nV peak noise at 10Hz bandwidth. This is +/- 0.1ppm peak. Further averaging like 100PLC would get it ever further down...
I don't think this leaves a lot to complain...

Nothing of the kind. We have SAR, 2 MSPS so this "backdoor" open widely up to 10-th MHz, I mean reference input port, noise level counts up to x1000 times.
Well if not x1000 due HF attenuation done inside ref chip and caps help, but at least up to 10-30 uV.

 Where is this  −166 dBFS/Hz  now?  Under  cat's tail?

[Kleinstein]

There is some filtering for the high frequency part of the reference noise. So not much aliasing there and the upper BW limit would be around 1 MHz.  If oversampling and averaging is used for higher precision (e.g. to get 10 Hz BW) this also applies to the reference noise.  So it is a comparison of the ADC noise and reference noise density (after scaling if needed). If I got the math right the ADCs white noise is around 18 nV/sqrt(Hz) - compare that to some 40 nV/sqrt(Hz) for the LTZ1000 at 7 V and  thus about 20 nV for a 3.5 V signal. So  for the white noise part they are about on par and as far as I understood the 1/f noise  of the ADC is not great, but still a bit better than the LTZ.

How much of the reference noise is effective depends on the actual voltage measured and this usually is less than full scale.

The NR part of a reference can help for the higher frequency noise, but is usually not effective below some 100 Hz or even lower. So for the near DC use (e.g. a DMM) the noise reduction is not helping that much.  Some extra noise filtering for the reference makes  absolute sense, especially for higher data rate use (e.g. audio), where filtering is feasable. The REF61xx is however noisy below some 1 kHz even with the NR capacitor - so of limited use for the audio band, but OK for the higher frequency part.

[MasterT]

 I'm afraid things more complicated, than simple noise math equations.  Since we have switched capacitor load for voltage reference, output impedance of the voltage reference may have more importance than noise level itself. 
In the middle frequency range ~ 1 kHz, where capacitor 47 uF have R-react. = 3.3 Ohm and doesn't help much with settling time, likely inter-modulation / interaction processes would happened, so ADC turns into noise generator as well.
I see TI starts to characterise REF61xx specifically for this case - sourcing high resolution / high speed SAR ADC.
 Zenner  as a voltage reference, shunt TL431, another series,   slow / weakly buffered references may be wrong type in this case, despite how low noise level they may have.

 And it also imply, noise tests for ADC with shorted inputs dumb stupid things, well, at least for high speed SAR ADC.
 Have to ask AD for FFT plot clarification.

[KT88]

I'm afraid things more complicated, than simple noise math equations.

Yes, indeed!

[Kleinstein]

An oversampling SAR ADC does not care very much about the 1 kHz range impedance of the reference. 1 kHz is also rather easy to buffer. Unless the input signal has a lot of content at 1 kHz there is essentially no ripple current at 1 kHz. The switches capacitor part gives ripple in the > 2 MHz range and this is dominated by the capacitors and not the reference chip. Here it only matters how good the reference can handle a low ESR capacitor at the output.  This can be different with a SD ADC, that can show significant ripple in the reference current at some idle tones. Here the reference impedance at some intermediate frequencies ( e.g. 100 kHz) may effect the INL (not so much the noise). So espeically for the SD ADCs it would be good to note more details for the INL specs (e.g. what reference and what input driver).

The Ref61xx output buffer seems to be good for the high frequency range (e.g. > 10 kHz) and there the NR capacitor also works well. However it somewhat fails in the low frequency range and is quite noisy there. So it may be a good reference for a high speed ADC, unless one uses this ADC to measure low frequencies or "DC".
The LTC6655 on the other side is quite good for the low frequency part, but the buffer does not provide very low impedance at the high frequencies - still not bad and maybe sufficient for many uses. If needed one may have to add an extra reference buffer.


The reference part is a bit tricky for switched capacitor ADCs - both SAR and SD types. Similar the input driver is difficult and possibly limiting for high perfomance ADCs. This however does not mean that the noise test with a shorted input is stupid - more the opposite: the shorted input is less effected by the reference and can in theory even skip the input driver. It is thus easy to reproduce and well defined and a good test. Noise wise the input driver is usually not that limiting (maybe for the 1/f part). The reference driver part can still be relevant, even with a shorted input.

It is always good to have more information and an extra test with a different test point (like 1/2 the full scale) would be nice, but this is not so easy and depends more on the details external to the ADC chip. This is more a test for the complete circuit / system, not so much an important point in the ADCs data-sheet.

[MasterT]

1.
An oversampling SAR ADC does not care very much about the 1 kHz range impedance of the reference.
2.
 Unless the input signal has a lot of content at 1 kHz there is essentially no ripple current at 1 kHz.

1.
 Oversampling is loosing effectiveness for any NON multiple AC frequencies presented at the input. In other words, practically for anything.
2.
 Who says it does not?

 We are discussing   -167 dBc noise level, if I remember, and if someone (TI) starts to worry about InterModulation with 16-18-bits,
"essentially no current" has to be printed in digits rather than in emoticons for 24-bits, would you think?

[KT88]

1. Oversampling allows a trade-of between Bandwidth and dynamic range.
2. RTFDS - it's 167 dBc/Hz which is a figure of merit like gain-bandwidth-product for an opamp. I never heard that anybody claimed it to be BS because one looses bandwidth when setting a gain>1!

[Kleinstein]

Together with a little anti aliasing filtering at the input the oversampling ADC approximates an integrating ADC. With internal averaging the AD4630 gets quite similar to a SD ADC of switched capcitor type (the usualy versions).  For the input side it sees similar sampling and the frequency response is set by the digital filtering/averaging. Oversampling works OK to reduce the noise - no need for special frequencies.  For later use it helps to set the length for averaging to be a multiple of a power line cycle. This is for hum suppression and not for noise reasons.  Hum may be mistaken for noise in some cases and it is good to get extra hum suppression.

The source impedance of the reference matters when there is ripple current - without a ripple current there is little effect if the reference impedance is a little higher.
The SAR ADC inputs seem to draw a current about proportional to the input voltage, and with a differential drive the current (as the sum) would be essentially constant.
Chances are the reference driving is more critical with a single sided drive compared to the differential drive case. The INL also looks a little better with differential drive.
I would expect a relatively similar reference current for a SD ADC, at least for the lower frequency part. With an SD ADC there is additional AC current from the internal modulation and at some points idle tones (frequencies quite a bit lower than the modulation / sampling frequency). The SAR ADC has no such Idle tones but could have multiple smaller peaks that repeat with the sampling frequency. With many SD ADCs differential drive also has an advantage for the INL.

It is a bit confusing that they call the ADC 24 bit and 2 MSPS. At 2 MSPS the noise is naturally higher and the effective resolution is more like 16 bits, though the digital data still have more bits. They get 24 bit resolution (and even a little more) with oversampling and averaging at a lower speed.
You find a rather similar picture with SD ADCs, like the MCP3561:  At the highest speed (some 150 kSPS)  the effective resolution is at some 15 bits and at the lowest speed may exceed 23 bits by a little.
So in both cases one can trade  BW for resolution and at the highest speed the noise levels are way higher than the nominal resolution. In both cases this is oversampling at work. For the quatization noise the SD ADC can have some additional advantage from the noise shaping and a noise reduction faster than the normal square root of N. This however only applies to the quantization noise and not to other noise sources, like the capacitor sampling (reset) noise. For these noise sources there is the classical square root law from averaging / reduction of the bandwidth.

[iMo]

"32bit 1MSPS" with LTC2500-32, or "24bit 2MSPS" with this one, or any other ADC - that is how it works since ever with marketing those chips. Afaik, all those datasheets include detailed tables on oversampling or sampling rate vs. achievable resolution, or sample noise, or noise free bits, etc. So looking at those tables is the first step when evaluating the situation, whatever the title page show..

[KT88]

And the elephant in the room:
A guy rudely mocking against oversampling SAR-ADCs is in favour of SD-converters - an ADC toplogy fundamentally based on oversampling! 
Also some multi-bit SD-ADCs entertain a low-res SAR these days....

[MasterT]

Non coherent stream of wikipedia BS, or provocative jokes clear signs of AI. 

AI is not capable to understand FFT , newer will be.
So it was expected.

Dose of holy water was injected.

[Echo88]

Are there any infos wether its necessary to use a external reference buffer for the AD4030-24/AD4630-24 to get the specified INL/noise or is the internal ref buffer sufficient?
In the AD4630-24-presentation they show the ADA4523 used to drive the inputs and the reference input for the high accuracy example configuration, whereas in the high speed variant the LTC6655LN is used without a driver...

Also im wondering which ADC-averaging/µC-averaging-configuration would be optimal to get the highest digital filter attentuation for 50Hz hum for ADC usage with say ~10Hz sample output rate?
The ADC uses a internal clock source, so when i use the internal averaging filter only the internal clock wil contribute to the ADC-noise with its jitter and not the triggering of the external CNV-pin?
Havent yet looked completely trough the datasheet, does it have a continuous sampling mode?

The idea of using a single ended amplifier for the AD4030-24 is interesting, would it really achieve the same specs as a differential HPM7177-frontend since the AD4030 generally has +3dB SNR compared to the 2-channel-version AD4630-24 like user macaba suggested?

[Kleinstein]

The DS shows an integrated buffer for the reference. In single ended mode the ref input current (after the buffer) depends on the signal and this may lead to some more INL error (especially a square part). So for single ended mode one may need a good reference buffer to get the best INL.

For the digital filtering there are different options, especially if part of the filtering is done externally. More internal filtering reduces the data trafic and this can help and also allow a less powerfull µC to do the final averaging.
As the clock is somewhat variable for best 50 Hz suppression one would adapter the filter to the actual ADC clock and thus use not very much ADC internal averaging.  There are many options for a digital filter:
Sinc1 is simple averaging over a set aperture and the easiest but with limited 50 Hz suppression if the length does no perfectly fits. 0.1 % matching would result in some 60 dB hum suppression.
It is not just the internal oscillator, but also the mains frequency that is somewhat variable. Just adapting the window length to the actual mains frequency is a real option.
The ADC internal averaging limits on how fine the aperture can be adjusted.
Sinc2 would give better hum suppression, but also more longer settling / apperture for the same noise BW. So one has to compromise somewhat.
There are other similar filter that can provide better hum suppression, but at the cost of more math needed.

[Echo88]

Hmm, since i never really was much into programming i do my simple µC-stuff with arduinos.
The Due with its SAM3X8E at 84MHz should be fast enough to handle the SPI-traffic when the ADC itself already does some averaging, especially when using all 4 SDO-lanes.
Does that provide enough room to implement a Sinc2/3-filter like its done in a SD-ADC or would i need a FPGA?
Would be nice to be able to have the choice between filters and the corresponding step response to optimize it for a given task.
Gotta read more about those filter topics and their µC-implementations.

I think i will implement both options for the reference on my test board: with and without buffer OP.
Why would the ref input current differ between single ended/differential input mode?

[Kleinstein]

It looks like the ref input current varries about linear with the input voltage. I see this like compensating some change for eche conversion. In differential mode it looks like there are 2 more or less identical ADCs for both sides and there currents in the sum stays about constant, as one goes up and the other goes down.

AFAIK the sinc2 and sinc3 filters are still rather simple and the 84 MHz µC should be able to do the math in real time, especiall if the data are reduced by something like a factor of 8 by the ADC. The crude averaging at the ADC should not make a big difference to a calculations with all the data -  some fine changes in the 50-500 kHz range. The question is more the required memory. With a variable overall aperture due to the possibly odd clock ratio one may have to do some minor modifications to the filter (e.g. adjust the overall lenght in the center part). It would not matter if the filter is only close to a sinc2, as long as the main properties like good hum suppresion are still there.

[Echo88]

What amount of low frequency noise can be expected from the AD4030-24 for BW 0.1-10Hz and say ~20Hz SPS?
The datasheet states 1.3µVpp but according to Figure 24 they use 2048 averaged Samples, which would lead to a sample rate of 19.5SPS * 2048 Samples -> ~40000SPS, while the ADC is capable of generating 2MSPS.
Am i wrong in that calculation/thought-process or should the ADC be better specced for the 0.1-10Hz BW when using the full 2MSPS?
The AD7177-2 meanwhile claims 0.5µVpp in Table 6 at 16.66SPS and 4.5µVpp (2.5Vref) 0.1-10Hz voltagenoise on page 5...

https://www.analog.com/media/en/technical-documentation/data-sheets/ad4030-24.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/ad7177-2.pdf

[coppercone2]

I wanna see someone do something that needs those bits

I wonder some kind of sintering experiment could make use of that

its awesome but... we don't have a god damn LHC. I know its also useful for radiation dating in some big ass machine but still that had a few million dollar price tag associated with it.

[KE5FX]

OK, if the sample cap bothers you - there is a remedy: https://www.analog.com/en/products/ad7134.html?doc=AD7134.pdf#product-overview.

Data sheet copyright date:



Product page:



This isn't funny anymore. 

[Kleinstein]

The AD4134 is a pretty much direct replacement for the AD7134 - so no need to worry that much. It could still be inconvenient if this need a PCB change, as at the high end level the PCB design can be critical.

I wanna see someone do something that needs those bits

I wonder some kind of sintering experiment could make use of that

its awesome but... we don't have a god damn LHC. I know its also useful for radiation dating in some big ass machine but still that had a few million dollar price tag associated with it.

The question on where do we need such an ADC is a good one.  Though likely not the intended use, one possible customer could be high end audio, for those who want super low noise and THD.
The large dynamic range could be of good use in a spectrum analyser / dynimic signal analyser - though the speed may be a bit on the low side for more general use.
A reasonabel use may be a digial lock in amplifier - so to resolve relatively small signals from a noise background. For most cases the AD4630 would be overkill, but with a noisy signal and could help to save on analog filtering.

[Echo88]

Possible applications include:

Dynamic signal analysers,
DMMs,
to build high resolution/accuracy DACs like shown in AN86,
high resolution/accuracy temperature or resistor measurement,
usage of ultra high range sensors like seismometers of photodiodes,

Can i get an opinion on my noise question please?

[iMo]

What amount of low frequency noise can be expected from the AD4030-24 for BW 0.1-10Hz and say ~20Hz SPS?
The datasheet states 1.3µVpp but according to Figure 24 they use 2048 averaged Samples, which would lead to a sample rate of 19.5SPS * 2048 Samples -> ~40000SPS, while the ADC is capable of generating 2MSPS.
Am i wrong in that calculation/thought-process or should the ADC be better specced for the 0.1-10Hz BW when using the full 2MSPS?
..

My bet would be the 1.3uVpp in the Figure 24 is the best what you can get (~200nVrms).
That is at the lowest possible internal SPS setting.
The higher the sampling rate the higher the noise, afaik. And the additional internal averaging (still 32x to make) does not compensate for the higher conversion noise with 2MSPS, it seems..
You may go lower with the noise with an external averaging, imho.

PS: ..imho you cannot go lower with SPS as that SAR ADC uses capacitors instead of resistors..

[Kleinstein]

I interprete the  "Low Frequency Noise (Output Data Rate = 19.5 SPS After Averaging Blocks of 2048 Samples)"  as using 2048 samples averaging inside the ADC chip and than additional external averaging of 50 samples to get to the 19.5 SPS nominal sampling rate. So the ADC wold still run at the normal 2 MSPS.
It is not very clear un what conditions the curve is measured.

A point I could not find are details of the 1/f noise or other extra low frequency noise. This may also depend on the parts around the ADC and PCB details.  At the low noise levels of this ADC some residual mains related hum could be an issue and may show up the 0.1 - 10 Hz measurement, as the 19.5 SPS is not able to suppress 50Hz and is not good for 60 Hz hum. This is especially the case with the ADC clock that is not very accurate, but normally an internal clock.
It depends on the application on how important the low frequency noise is.

[KT88]

Although the noise amplitude increases with the sampling rate because of the wider bandwidth, the dynamic range increases and with that the noise amplitude if the output data is filtered / averaged.
To make ADCs more comparable the spec / FoM of "NSD: −166 dBFS/Hz typical" is shown. This means the NSD at a bandwidth of 1Hz.
A quick and dirty way to calculate this is to calculate 3dB/octave for the oversampling filter and take the nyquist frequency as the starting point e.g. 1MHz for the full sample rate of 2MSPS... This figure is also known as 'process gain'.
If we take the roughly 106dB of SNR we can add the process gain to that number.
This also shows that you lose dynamic range if the sample rate is reduced.
1/f noise should not be present with recent SAR converters as they usually entertain some sort of AZ technology.
One thing that my look like 1/f noise could be wide bandwidth noise that is folded down into the low frequeny region. For this task the input R/C circuit doubles down as an AAF for high frequency noise of the ADC-driver...

Edit: As an example, the SNR is about 106dB and 1Hz to 1MHz are 20 octaves resulting in 60dB of process gain (20 x 3dB). As the result we get the *NSD: −166 dBFS/Hz typical* mentioned in the data sheet (106+60).

Cheers

Andreas

[Kleinstein]

Ieally there should be no 1/f noise, at least not from the main signal path. However when looking for details and small contributions there usually still a little bit of extra low frequency noise comes in. This can be things like variations in the internal clock that somehow translate to a variable offset or variations in the supplies or just thermal effects.  In a more normal circuit resistors can contribute to 1/f noise.

When looking at frequencies well below 1 Hz there is also addition noise in the SD ADCs like AD7190 and many AZ OPs. It may be not much, but quite often there is some if one looks hard enough (low enough in frequency).

[Echo88]

I completely forgot about the test that Macaba already did on the AD4630-24, with a result in post 45 of this thread:

"A. 2MSPS, microcontroller averaged x32768 = 0.62uVpp" at 61SPS

Missing/omitted parameters/specs and the missing explanation of how they measured this stuff ("biascurrent of older AZ-OPs? Measuring it takes time and costs money, lets calculate it  ") is a bane of existence.

With the knowledge of the approximate realistic lowest noise i can now try to design a more suitable adc-driver.

[iMo]

What he wrote is:

A. 2MSPS, microcontroller averaged x32768 = 0.62uVpp
B. 2MSPS, onboard averaged x32768 = 0.65uVpp
(10 second sample block [i.e. 30.5 - 0.1Hz] peak-peak values averaged over 15 minutes [90 blocks])

Does the 90 blocks averaging apply for A and B?

[coppercone2]

Well I asked about this, and a 'direct' application of nanovolt measurements is sintering. Apparently you can measure the conductivity of materials as they are being sintered to get the proper 'bonding' or whatever you want to call it. Like powdered metal parts (titanium, stainless, so forth)

That sounds like something useful for DIY parts. That's what I was getting at, can this enable you to do anything NEW, not slightly better. The problem for me is that I have a DSA already (and you can get them cheap sometimes, like me), and yeah.. maybe it could lower the noise floor a little if you made it, but damn I just don't feel compelled. The whole making a seismograph/sensor is actually the hard part (its almost always precision expensive mechanical engineering that you need to benefit from these parts).

Experiments with strain sound possibly cheap (maybe just a heavy screw and a heater would be enough with a crude die. At least it does not feel like a mega project to think about compared to some other nanovolt things, since you are just essentially measuring a resistor directly.

[branadic]

Another possible application can be an atan2-interpolator for high-resolution encoders and other 1Vpp sin/cos sensors.

-branadic-

[Kleinstein]

Measuring resistance changes is usually easier and better done with a bridge circuit of some kind instead of a more DMM like circuit with current source and votlage measurement. A high qualtiy ADC could to a certain degree replace one half of a bridge  (use a 24 bit ADC instead of 2 good resistors - which is not as stupid as it sounds at first). However a transformer may be the better alternative.

Sintering experiments are usually done at elevated temperature and this makes it really difficult to keep the temperature stable enough, so that resistance changes are not dominated by thermal effects.

Unless there is a way to use an external clock for the ADC, I see some problems in using this ADC for anthing else than raltively low frequency signals with averaging or maybe more randowm samples RMS measurements.  With a significant AC amplitude the timing jitter would be a rather big contribution to the overall noise. To really make full used of the high speed (e.g. for 100 kHz range AC signals) one would normally also want state of the art (ps range), low jitter timing.

[KT88]

Unless there is a way to use an external clock for the ADC...

RTFDS : p29
It is possible...

Cheers

Andreas

[MiDi]

What amount of low frequency noise can be expected from the AD4030-24 for BW 0.1-10Hz and say ~20Hz SPS?
The datasheet states 1.3µVpp but according to Figure 24 they use 2048 averaged Samples, which would lead to a sample rate of 19.5SPS * 2048 Samples -> ~40000SPS, while the ADC is capable of generating 2MSPS.
Am i wrong in that calculation/thought-process or should the ADC be better specced for the 0.1-10Hz BW when using the full 2MSPS?
The AD7177-2 meanwhile claims 0.5µVpp in Table 6 at 16.66SPS and 4.5µVpp (2.5Vref) 0.1-10Hz voltagenoise on page 5...

https://www.analog.com/media/en/technical-documentation/data-sheets/ad4030-24.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/ad7177-2.pdf

No idea why ADI choose such strange sampling for 0.1-10Hz figure, it is just nuts to give worse figure than what it is capable of 
Got 18uVrms@2MSPS from histogram, for mean of 2^15 samples gives 0.1uVrms or ~0.6uVpp, which is close to Macabas measurements (0.59uVpp).

[Kleinstein]

Unless there is a way to use an external clock for the ADC...

RTFDS : p29
It is possible...

Cheers

Andreas

The part around page 29 does not help - that part is discussing the clock for the serial interface, not the actual conversion.
It looks like there is no true clock to the ADC - more like  an external start of conversion signal (CNV) and than an internal timing for the individual steps of the conversion. So one can start the conversions quite accurate, but as it looks like not the start of the aquisation. So good 50/60 Hz suppression is possible, but when pushing the limits with the sampling rate, there could be some extra jitter / settling error.

[Echo88]

https://www.analog.com/media/en/evaluation-documentation/evaluation-design-files/eval-ad4630-24-design-files.zip

I was wondering about the DS-claim "CNV-pin needs low jitter clock to achieve ADC-specs" and how to fulfill it.
Am i assuming correctly that the CNV-circuit used on the AD4630-Evalboard (100MHz oscillator, inverter, FF, logic-level-shifter) is using the low jitter of the 100MHz oscillator, while enabling an arbitrary clock input via pin "CNV_FMC" from a µC or low grade oscillator, so one doesnt need to worry about jitter?

For example: 1.6384MHz (1638400 / 2^15 = 50SPS, filters 50Hz hum via the ADC-integrated Sinc1-Filter) as an oscillator is difficult to get, im thinking about using an available 3.2768MHz oscillator and generic /2-divider without needing to worry about jitter.

I found the internal 80MHz-clock/CNV-combination also weird. 

[KT88]

It looks like there is no true clock to the ADC - more like  an external start of conversion signal (CNV)

Correct - The bit decisions are self-clocked. The complexity of the bit decisions is much more complex than in early R-2R SAR cores. CapDACs have usually a couple of redundant bits as well as pipelined structures some times. External clocking won't make any sense for this type of ADC.
For the sampling of the incoming signal the edge of CNV is the defining moment. With the rising edge of CNV the sample cap disconnects form the input for roughly 300ns. After that it reconnects to the input and has 200ns to settle @2MSPS (hence the importance of the ADC driver to settle within this timing window).

[KT88]

I was wondering about the DS-claim "CNV-pin needs low jitter clock to achieve ADC-specs" and how to fulfill it.

This is important in particular for frequency domain applications not so much if one is interested in DC (averaging over many samples).
Considering a slope: if the sampling moment is off the amplidude has changed in the meantime.
This becomes more important with higher frequencies and resolution (more LSBs are affected).

[MiDi]

Little sister AD4632-24 with 0.5MSPS released, sharing same datasheet.