There’s a good chance this figure is wrong, it might be a little higher, maybe towards 2uVpp. (Aligning with datasheet better.) Evaluation is still ongoing…
Managed to track down the discrepancy in the input-short noise figure that I mentioned:
A. 2MSPS, microcontroller averaged x32768 = 2uVpp
B. 2MSPS, onboard averaged x32768 = 0.7uVpp
(the number that MiDi posted at 0.5uVpp is using onboard averaged x65536, however I don't have enough uC memory to manually average that many samples from a DMA buffer)
In terms of DIO traffic (as a possible reason for the increased noise)
A. 32768 CNV pulses, 2 channels of 16 clocks of DDR, readback per CNV.
B. 32768 CNV pulses, 2 channels of 16 clocks of DDR, single readback after all CNV pulses.
As a further data point - I combined A & B (onboard averaging, with readback every CNV pulse, using SYNC bit to determine updated sample) and sure enough - higher noise, back at around 2uVpp. I suspect part of this will be extra noise on the die, and most of it will be poor PCB layout/decoupling.
Adds a little challenge for me - how to get 1PLC of samples with only the 2^n onboard averaging options.
EDIT: I'm now reasonably certain this is an issue with layout rather than any deficiency with the part itself.