AD4630-24 new SAR ADC from Analog Devices

[KT88]

There is a new SAR ADC in pre-release from Analog Devices:2MSPS, 24bits, +/-0.9ppm max INL...
https://www.analog.com/en/products/ad4630-24.html#product-overview

Cheers

Andreas

[antintedo]

What is even more impressive, the typical INL is just 0.1ppm, even for a single ended input.
Noise seems a bit high in comparison to the best SD and SAR ADCs.

[KT88]

Noise at full bandwidth can't be compared directly. A comparison at 1Hz (NSD: −166 dBFS/Hz typical) would be a meaningfull comparison / FoM. Combining the two ADCs would score additional 3dB...

[Kleinstein]

The higher frequency noise looks good. For the lower frequency one would have to see in real life. There may of may no be sifnificant extra /1f noise at the reference input and maybe correlation.

For the linearity don't forget the input buffer. It is not that easy to find a buffer with so little INL.

Another impressive point is the power it needs. Just from the ADC power it would fit battery operation.

[KT88]

No dedicated driver needeed in many cases - it takes only 600nA input bias current at DC.

[Echo88]

Very impressive INL, but the package... 

[jbb]

Yowza!
Dynamic range at full sample rate is allegedly 106dB, ie around 17 bits.

Package is 0.8mm pitch BGA, which is a bit inconvenient but not terrible. I suspect it could be broken out on a 4 layer PCB without going to fancy PCB processes.

(I did a design in my last job with a 0.4mm pitch part and that was really annoying to prototype.)

[coppercone2]

lol, they need to make a grid on top of the chip so you can solder it upsidedown if you wanted to with direct connections between the pads so you can probe them, the whole BGA thing is ridiculous

like if the chip connection package was 3d metal printed with a good sintering machine or whatever after the die was made. then I would hate them less if you can probe them with fine needles or even put parts ontop of the chip deadbug style
The technican is really being screwed over hard by like 0.5cm^2 of copper sheet conductors

[KT88]

The pinout isn't all that bad...the inputs are situated at an outer row (1) surrounded by GND-pins. The interface pins are also 1st and second row (7+8) to the edge. Placing some test points close to the package still gets you closeer to the die than in any other 64-pin package.
To get to such specs a more traditional package would possibly result in slightly inferiour specs...

[chickenHeadKnob]

The pinout isn't all that bad...the inputs are situated at an outer row (1) surrounded by GND-pins. The interface pins are also 1st and second row (7+8) to the edge. Placing some test points close to the package still gets you closeer to the die than in any other 64-pin package.
To get to such specs a more traditional package would possibly result in slightly inferiour specs...

QFN64 with .5mm pitch would be much better for us hobby peeps, and it can't be all that bad for lead inductance. I wish they offered in both package styles so we could see the performance difference (if any).

[arcnet]

The pinout isn't all that bad...the inputs are situated at an outer row (1) surrounded by GND-pins. The interface pins are also 1st and second row (7+8) to the edge. Placing some test points close to the package still gets you closeer to the die than in any other 64-pin package.
To get to such specs a more traditional package would possibly result in slightly inferiour specs...

And this ADC has even the capacitors integrated... 2 uF for the reference, 1 uF for VDD5 and VDD1_8 and 0.2 uF for VDDIO.
IOGND and GND are shared. Many (prototype) pcb manufacturers have 0.1 mm width and spacing nowadays as standard so no problem and for prototyping one might get even away with simple vias as pads (0.2 mm drill and 0.1 mm annular ring) and solder them from the bottom.

[MiDi]

Nice ADC, anyone evaluated this specimen already?
Macaba got 0.5uVpp at 30SPS.

[macaba]

Nice ADC, anyone evaluated this specimen already?
Macaba got 0.5uVpp at 30SPS.

There’s a good chance this figure is wrong, it might be a little higher, maybe towards 2uVpp. (Aligning with datasheet better.) Evaluation is still ongoing…

[KT88]

If power is not constrained it only makes sense to run the ADC at full sample rate and use the internal (up to 2¹⁶ decimation rate) or an external filter to get to the desired bandwidth and dynamic range. A LPF can reduce HF noise sufficiently that nothing of that is folded back into the band of interest. Paralleling both ADCs would gain another 3dB of DR...

[macaba]

There’s a good chance this figure is wrong, it might be a little higher, maybe towards 2uVpp. (Aligning with datasheet better.) Evaluation is still ongoing…

Managed to track down the discrepancy in the input-short noise figure that I mentioned:

A. 2MSPS, microcontroller averaged x32768 = 2uVpp
B. 2MSPS, onboard averaged x32768 = 0.7uVpp

(the number that MiDi posted at 0.5uVpp is using onboard averaged x65536, however I don't have enough uC memory to manually average that many samples from a DMA buffer)

In terms of DIO traffic (as a possible reason for the increased noise)
A. 32768 CNV pulses, 2 channels of 16 clocks of DDR, readback per CNV.
B. 32768 CNV pulses, 2 channels of 16 clocks of DDR, single readback after all CNV pulses.

As a further data point - I combined A & B (onboard averaging, with readback every CNV pulse, using SYNC bit to determine updated sample) and sure enough - higher noise, back at around 2uVpp. I suspect part of this will be extra noise on the die, and most of it will be poor PCB layout/decoupling.

Adds a little challenge for me - how to get 1PLC of samples with only the 2^n onboard averaging options.

EDIT: I'm now reasonably certain this is an issue with layout rather than any deficiency with the part itself.

[Kleinstein]

Some interference from the data transfer effecting the ADC is possible. So it may help to have at least some on board averaging to reduce the data rate.

To get 20 ms seconds averages, one would need 40000 samples at MSPS. This could be 64 samples averaging in the ADC and than 625 fold averaging in the µC.
Alternatively one could use a different, slightly lower frequency, e.g. so that 32768 fold averaging get you 20 ms.
A 3rd way to get effictive mains hum suppression is to use a little reduced weight to the samples at the start and end and a wider data window, a little similar to what most SD ADCs do. A slightly smoothed out start and end has some positive effects a little off exact 50Hz multiples and only needs a little more time and processing.

Just Averaging of the data does not need memory for the whole data. One could use something like a circular DMA buffer and pocess the data while they come in. With a reduced data rate from some averaging already in the ADC this should be doable.

[MiDi]

Avg of 1024 in ADC and 1953 in µC will give near 20ms/1PLC@50Hz mains.
For comparison DMMs running @1PLC with AZ give one value every 2PLCs, the AD4630-24 runs AZ for each reading.

What are the corresponding AC RMS values?
Would be nice if you would publish the raw data 

Chances are if there is interference, it is from the reference, not much to improve with input short to GND close to the pins.

[Kleinstein]

With a shorted input the reference should not have very much effect on the noise. High frequency interference could still come through though.
When measuring a non zero voltage, there may be some additional noise from the reference, but also a little ADC internal.

For the noise it may be interesting to do an FFT on the data, to see if there is 1/f noise. To reduce the data rate maybe with some initial averaging in the ADC.

[fluxgate]

Please note, these SAR ADC's are High Speed devices, due to aliasing they will pickup everything up to hundreds of MHz at the analog Inputs and digital IO. I really recommend using Delta Sigma for  Low Frequency / DC measurements ans low noise nutting.

[KT88]

I really recommend using Delta Sigma for  Low Frequency / DC measurements ans low noise nutting.

Which one?

[coppercone2]

Please note, these SAR ADC's are High Speed devices, due to aliasing they will pickup everything up to hundreds of MHz at the analog Inputs and digital IO. I really recommend using Delta Sigma for  Low Frequency / DC measurements ans low noise nutting.

You need some filters.

If you want to learn more, I recommend a SAR adc. You have more samples to play with, for implementing codes.. and you get a faster response on the work bench.

[Kleinstein]

These new SAR are quite good with the linearity - this is at least on paper. The fast ADC also needs a fast driver and the driver may contribute to the INL.

There are alternative SD ADC, that can also get quite fast, like the AD7175.

Even the SD ADC need some filtering at the input as they internally also sample the input - the requirements are still a bit lower there and especially no short AA filter needed.

[macaba]

I really recommend using Delta Sigma for  Low Frequency / DC measurements ans low noise nutting.

With 18nV/rHz noise density and 0.1PPM INL, along with many other good specifications/features, I don't think there's a delta sigma that gets near the AD4630-24.
(Not to imply it's the DS technique that's the issue, just the implementation limits)

[MiDi]

I really recommend using Delta Sigma for  Low Frequency / DC measurements ans low noise nutting.

I really recommend using Multi Slope for Low Frequency / DC measurements and low noise nutting. 

Some more details:
https://ez.analog.com/webcast-qa/2022-webcasts/1-11-2022-bullseye-transforming-the-precision-narrow-bandwidth-design-journey/m/file-uploads/1944/download

Attachments taken from the presentation.

What we can expect in future:
https://analogdevicesinc.github.io/no-OS/ad463x_8h.html#a081c378bd980443c3684ee785d69512d

[Kleinstein]

Doing a high rate of oversampling with an SAR ADC is not that different to an SD ADC. With the very good INL the AD4630 also gets interesting for oversampling and use with lower speed. The chip already has provisions inside for this. One could even consider to add some intentional ditherring signal to imporve on local linearity a little.
To keep the data rate low and this way to reduce the effect of coupling, it is a good idea to some averating already inside the chip.
One may still need a fast and very linear driver.