AD4630-24 new SAR ADC from Analog Devices

[Kleinstein]

There are alternatives for the input divider. It also depends on how the meter is build - there are quite some alternative with an ADC that has a differential input. The simple way is just a divider at the input and than a buffer to the ADC in quasi single ended mode. So a bit like the handheld meters.
The input divider could also be with less steps and than fine switching via gain after the divider.
Other versions can have buffer - divider - buffer to allow high Z mode for more than 2.5 or 5 V. Dirving the ADC with a differential signal with 2 differential amplifier with a gain < 1 as in the HPM7177 is another option, though also with some downsides.

The ORN and MORN resistor networks are somewhat similar to LT5400 with somewhat lower specs and a few different resistor values availabel.
One may not need a 10:1 divider, but other ratios (e.g. 3:1 or 4:1) can work as well, that could be obtained from a few equal resistors.
For the input divider for some 100 V or so a chain of equal SMD (thin film) resistors is an option too.

[iMo]

Yep, we had the discussion on the input stages for differential SAR/SDs in past (with spice simulations), the only critical part imho is the resistive divider, however (the values do not matter, except the lower side should be around 1k, otherwise I see a larger stddev in my SD with no buffer after the divider). Would be great to have the latest update on such cheapo resistor dividers alternatives with ratio TC below 13ppm/K (but in a different thread perhaps)..

[macaba]

Attached is updated NSD.

The datasheet says "1/f noise is canceled internally by auto-zeroing. Noise spectral density is substantially uniform from dc to fs/2." - hmmm

[Kleinstein]

There is some 1/f noise, but still not very much. It is somewhat comparable what they measured at Cern for LTC2378, AD7177 and similar.
The measurement may still include some input amplifier. Another possible source of 1/f noise are thermal fluctuations.
Ideally one may still need some external auto zero mode in the front end.

[Paskis]

Hi,
I've just acquired the ADC with the Zedboard in order to test the performance. The thing is that I cannot evaluate the effective bandwidth 'as I was testing with a sine signal and when I go above 500 kHz the Peak-to-Peak level in the signal heavily drops. I've checked and the input signal was pretty much stable so It has to be the ADC. Any idea what it should be? I would really apprecaite some help.

Thanks

[MasterT]

My curiosity pushed me to  download design files, and what I see right after SMA connector?
Correct, anti aliasing filter R=10 Ohm, C=0.01 uF. Seems o'k,  cut off about 1.6 MHz, only C has impedance 31 Ohm at 500 kHz, quite low even to drive by SG with 50 Ohm default output imp.

 I 'd recommend also to check  RC at the output of OPA driver.
 It's enormously huge load for most OPA that  I know, to drive <100 Ohms, especially if requirements for ultra low noise & low distortion very strict the same time. AD realised that they don't have such extra quality OPA in their possession, so RC filter is way off  in frequency 4.8 MHz, : C = 1000pF ( 318 Ohm !) .   

I see in DS for ADA4896-2  OPA is capable to drive 100 Ohms, Fig. 18, but  THD is hardly gets to -65 dB at 500 kHz!

 I had bad experience in the past with ads1256, when I first time  came to conclusion  that whatever beautiful numbers they put into ADC DS, check if you  can buy OPA that capable to drive this bitch, or if such OPA even exist.

[KT88]

To address a missunderstanding: The R-C in front of the ADC input is not the AAF. It is part of the buffer. The C has to provide sufficient charge to the sample cap and the (low-value-) R has to recharge the cap between two samples to less than an LSB.
This is the reason that ADC drivers exist that can provide up to more than 100mA. They are also fast enough because most regular opamps are also too slow to settle within a few hundreds of nanoseconds to the desired fraction of an LSB.
Another consideration is the kind of signal that should be sampled - many applications like audio or many sensors don't require high frequencies AND high amplitudes at the same time...
The AD4630 and the newer AD4030 have a novel frontend that recharges the sample cap to the previous voltage which reduces the (average) input current significantly - except the input frequency comes closer to the sample frequency - in that case it behaves more and more like a classic SAR-ADC...

Cheers
Andreas

[MasterT]

I know what you mean, but it doesn't change anything. The fact is, that RC filter in front of the ADC is must be there,
other-ways non-linearity would be much worse. And nothing tells that this filter can't be AAF as well, double purpose. 

And after that, there is No 24-bits 2 MSPS low noise ADC.
It's ether 24-bits OR 2 MSPS OR low noise.

At DC & low frequency end, see Figure 17 - THD crosses a line -120 dB at 4 kHz, so actually we have 20-bits and 4 fake-bits.
It's not necessary to sample 4 kHz with 2 MSPS, any SD ADC ($4 MCP3561) would perform much better at 4 kHz on both accounts: Noise & THD.

Excellent linearity in Figure 12 likely at DC voltage end, because I don't even see in Figure 17 THD level ever goes below -140dB to get 0.1 ppm. Again, you don't need 2 MSPS for DC.

There only corner where high sampling rate is justified/ necessary - high frequencyies at the input ( 10 kHz - 1 MHz), and AD is saying: don't even dream about 0.1 ppm - 60 pF (!!!) input sampling capacitor would ruin whatever already mesarable pictured in Figure 17 down to
-65 dB THD, where only 12-bits makes sence, and 12 fake-bits follows to foul naive  idiots.

[KT88]

And nothing tells that this filter can't be AAF as well, double purpose.

Not really - The R-C combination needs to have certain values: The C needs to have sufficient capacitance to provide enough charge to the sample cap and the R plus the buffer amp need to be able to recharge the C in time. This limits the corner frequency of the R-C combination to a very narrow range. Also a first order R-C filter has usually a too shallow roll-off in the stop band...

And after that, there is No 24-bits 2 MSPS low noise ADC.
It's ether 24-bits OR 2 MSPS OR low noise.

You miss the point of such an ADC- it is meant to be oversampled to gain DR for lower frequency signals down to DC signals. The figure of merit is the NSD of -166dB/Hz in this case. This means it performs almost as a 28bit ADC at 1Hz oversampled...

so actually we have 20-bits and 4 fake-bits.

No again: These bits are called noise bits. They enable to average the signal when oversampling - if they were fake the oversampling won't work...

Again, you don't need 2 MSPS for DC.

Yes, you need them - see above.

There only corner where high sampling rate is justified/ necessary - high frequencyies at the input ( 10 kHz - 1 MHz), and AD is saying: don't even dream about 0.1 ppm - 60 pF (!!!) input sampling capacitor would ruin whatever already mesarable pictured in Figure 17 down to
-65 dB THD, where only 12-bits makes sence, and 12 fake-bits follows to foul naive  idiots.

Be carefull who you call idiots... I would strongly recommend to you to learn more about sampling theory - You'll find a lot of material at TI or Analog devices for example... It isn't as simple as you think.

Cheers
Andreas

[iMo]

There is a test jig for both ADCs in LTSpice, you may try to play with it (it simulates the input sampling capacitor's transients as well, AD says)..
You get the 24bit digital word out of the simulation too - see below..

[MasterT]

Quote
And after that, there is No 24-bits 2 MSPS low noise ADC.
It's ether 24-bits OR 2 MSPS OR low noise.

You miss the point of such an ADC- it is meant to be oversampled to gain DR for lower frequency signals down to DC signals. The figure of merit is the NSD of -166dB/Hz in this case. This means it performs almost as a 28bit ADC at 1Hz oversampled...

>>> Don't be stupid, if oversampling is involved than sampling rate is divided, 1 ksps with block size 2048.

Quote
so actually we have 20-bits and 4 fake-bits.
No again: These bits are called noise bits. They enable to average the signal when oversampling - if they were fake the oversampling won't work...

Quote
Again, you don't need 2 MSPS for DC.
Yes, you need them - see above.

>>> Read above, SD ADC perfectly outperform in low sampling rate area, and oversampling is exactly apply here.

Quote
There only corner where high sampling rate is justified/ necessary - high frequencyies at the input ( 10 kHz - 1 MHz), and AD is saying: don't even dream about 0.1 ppm - 60 pF (!!!) input sampling capacitor would ruin whatever already mesarable pictured in Figure 17 down to
-65 dB THD, where only 12-bits makes sence, and 12 fake-bits follows to foul naive  idiots.

Be carefull who you call idiots... I would strongly recommend to you to learn more about sampling theory - You'll find a lot of mateial at TI or Analog devices for example... It isn't as simple as you think.

>>> Get lost, you have No idea who write app. notes for TI & AD. Will put your in ban list

[iMo]

The question here is perhaps how good are those AD4630-24/AD4030-24 for a "DC" measurement - compared to those ADS1263/AD7177/LTC2500-32 we collected in past and which are still waiting in our shoe boxes to be soldered into a nice PCB 

[KT88]

Don't be stupid,

Don't be insulting...
Everybody in this forum has a different level of experience from beginner to expert. We are here to learn from each other and share our work or hobby challenges and solutions.
There is nothing wrong about not knowing stuff - everybody can learn more...

When I mention "oversampling" in the metrology section, I anticipate a somewhat experienced audience that knows at least briefly the trade-offs of oversampling - hence I didn't explain it furthermore.
Oversampling is also not limited to the built-in features of a specific ADC -it can be done in a processor or FPGA. It is also not limited to powers of 2.

The NSD of -166dB/Hz is from the data sheet - if it is wrong you could report it to Analog Devices if you like...

I mentioned TI and Analog because if you google for oversampling or other terms used with ADCs they come up first usually. I also stated "for example" which means that these are not the only resources, of course.

Cheers

Andreas

[KT88]

The question here is perhaps how good are those AD4630-24/AD4030-24 for a "DC" measurement - compared to those ADS1263/AD7177/LTC2500-32 we collected in past and which are still waiting in our shoe boxes to be soldered into a nice PCB

This is indeed the most interesting question as until now SD- or several flavours of multi-slope converters were superiour over SAR converters.
The INL spec of 0.1ppm is very promising as well as the (oversampled-) dynamic range.

Cheers

Andreas

[Kleinstein]

The INL is not directly limiting the useful resolution. So 24 bit resolution can still be there even with 100 ppm INL. With higher resolution it is quite normal that the INL error can be considerably larger than 1 LSB. Especially the tested INL specs hardly can be better than 1 LSB as there is not enough time to do a full histogram test. The noise can be a limiting factor to how much INL testing can be done in a reasonable time. Resolution better than the the INL limit is still quite useful.
With 24 bit ADCs it is quite common to find some of the bits burried in the noise and an effective resolution that is lower. There is not need to have the quantization noise as the dominant noise source.


The higher THD of the amplifier only applies to the case when there is a large amplitude signal present - with lower amplitude at the higher frequencies and other signals at lower frequency things can become quite a lot better.

With the anti aliasing filtering it depends if you have a signal source that is more in a time domain or more in the frequency domain. So it depends on the application. In some cases it is more appropriate to look in the frequency domain and one needs an AA filter and maybe low THD even for a large signal. In other cases one cares about the settling time, but not about aliasing, as one is not interested in the signal between the sampling times, but the voltage at a give time. Quite often there is no MHz range full scale signal, but a more DC background and only moderate amplitude at higher frequency for the details. The THD can also have transient parts that does not matter after settling and one can profit from not haviing an AA filter to slow doen settling.


The MCP3561 and many other SD ADCs have relatively similar driving requirements to the SAR ADCs, as there is actually also capacitove sampling. With a poor driver a SD ADC INL can also suffers. Similar the reference driver may need extra care. For the high performance ADCs they should note the drivers used for the specs - the performance limits may very well be due to the drivers.

The MCP3561 noise and INL performance are still inferior at 4 kHz compared to the AD4630 with averaging. The same advantage from oversampling also applies to the SAR ADC. The comparison is a bit tricky as both give different quantities. The AD4630 gives some 136 dB DR for 1000 fold oversampling, that should about compare to an OSR value of 2048 or 4096 with the MCP3561 with some 3-4 µV of RMS noise  wich would be around 120 dB DR. So about a 16 dB advantage for the AD4630.

The MCP3561 data-sheet shows the 2nd harmonic (but not the higher ones) for a 1 kHz test signal, that looks good. However the INL curve shown is more of the point symmetric type that would mainly create odd harmonics. So the test at 1 kHz is missleading: -130 dB for the 2nd harmonic does not rule out a THD worse than -100 dB.
Looking at the THD is also mainly looking at the soft INL and not so much at more localized issues (e.g. idele tones), that may be the limiting factor to the INL.

There is no need to sample a 4 kHz signal with 2 MSPS, but one can and than use digital filtering to remove the unwanted higher frequency noise. Oversampling simplifies the AA filter.
With oversampling and digital filtering the AD4630 actually gets quite similar to an SD ADC, just with a SINC1 filter.
 

[KT88]

There is no need to sample a 4 kHz signal with 2 MSPS

Yes and no... it would help to lower the noise floor if a higher (than Nyquist) sampling rate is chosen.
There is also a significant difference to SD- and previous SAR converters which is the pre-charge feature:

The acquisition circuit on each input pin is also
precharged to the previous sample voltage, which minimizes the
kickback charge to the input driver.

DS, p.20, converter operation section.
An equivalent circuit for the input can also be found on p.20.
This means that there is barly any kick-back for a steady state signal - something that hasn't been done so far.
As a result in (more or less) DC-applications the driving part is quite easy and doesn't introduce significant harmonics...

Cheers

Andreas

[macaba]

I often see statements along the battles lines of "SD vs. SAR" which doesn't make much sense to me.

As a more generic abstraction that is useful to a front-end circuit designer, it comes down to:
capacitive-sampling input vs. resistive input
and the ADC's noise level/linearity that is mostly a function of the quality of implementation of a technique (and the semiconductor process it is made on), not the name of technique.
It might be true to say that before the AD4630, there weren't many competitive SAR ICs when compared to SD ICs.

For an excellent explanation of the merits of the two types of input, pages 29-31 of AD4134 datasheet is good ("THEORY OF OPERATION").

(Footnote: ADI took the AD4630 one step further with the precharge mechanism which blurs the lines a bit).

[KT88]

I often see statements along the battles lines of "SD vs. SAR" which doesn't make much sense to me.

I agree - it mostly depends on the application. But sometimes like in the case of the AD4630 right now we see a shift in how the Architecture gains some advancements for certain applications.
It doesn't, by no means,  render other ADC topologies usesless...

[iMo]

The ~4y old LTC2500-32 is a SAR for example:
±0.5ppm INL (Typ)
104dB SNR (Typ) at 1Msps
148dB Dynamic Range (Typ) at 61sps
@200kHz input sig: SINAD 99dBFS, SNR 100dBFS, THD -106dBFS

[MasterT]

The INL is not directly limiting the useful resolution. So 24 bit resolution can still be there even with 100 ppm INL. With higher resolution it is quite normal that the INL error can be considerably larger than 1 LSB.

>>> Non sense for me. It does limit, anything below INL line is a fake, garbage to discard not bothering to push over data bus.
I'd prefer other way around, have 12/ 16-bits with better INL < 10ppm

The higher THD of the amplifier only applies to the case when there is a large amplitude signal present - with lower amplitude at the higher frequencies and other signals at lower frequency things can become quite a lot better.

>>> Drop this clowns wizardry, lowering amplitude you are losing SNR.
As I say:
24-bits - No 2 MSPS
2 MSPS - No 24-bits
Lowering SNR - No Low Noise.

With the anti aliasing filtering it depends if you have a signal source that is more in a time domain or more in the frequency domain. So it depends on the application......

>>> I don't understand what does this means. What I see is rough violation by AD common practices for test equipment: put a sticker if a module  poses a threat for external test SG or other test equipment  not complying with 50 Ohm input spec. And AAF 10 Oms & 10 nF may demage SG at 500 kHz.

The MCP3561 noise and INL performance are still inferior at 4 kHz compared to the AD4630 with averaging. The same advantage from oversampling also applies to the SAR ADC. The comparison is a bit tricky as both give different quantities. The AD4630 gives some 136 dB DR for 1000 fold oversampling, that should about compare to an OSR value of 2048 or 4096 with the MCP3561 with some 3-4 µV of RMS noise  wich would be around 120 dB DR. So about a 16 dB advantage for the AD4630.

>>> LNA at the input of the MCP3561 (TLE2027 50 nV/ sqrt(Hz) or similar would bring 40 dB. 
But I'd leave this discussion for another topic.

[Kleinstein]

The INL is not directly limiting the useful resolution. So 24 bit resolution can still be there even with 100 ppm INL. With higher resolution it is quite normal that the INL error can be considerably larger than 1 LSB.

>>> Non sense for me. It does limit, anything below INL line is a fake, garbage to discard not bothering to push over data bus.
I'd prefer other way around, have 12/ 16-bits with better INL < 10ppm
 

I also prefer INL lower than 1 LSB, but this is essentially not possibly with better than 12 bits. As long as the curve is monotonic (DNL < 1 LSB) the resolution is still usefull, especially as the INL error is the maximum error and this often applies to the upper / lower end of the range (like the extreme 10%) or a few special points.
Essentially all 24 Bit ADCs have an INL error larger than 1 LSB:  the 3458 DMM and the AD4630 are about the only ones were the INL is at least close to 1 LSB (at 24 bit). The input buffer for the AD4630 may limit that.

Especially with SD ADC it is common to give a 24 bit resolution, as the data are send in 24 data format. The noise is often higher and quite often the INL is in the 5 ppm range. With SD ADCs the numerical resolution is cheap and they can thus use the computer typical steps like 16 / 24 / 32 bit for the resolution. There is absolutely no need to have the quatization noise as the limit -  in the high resolution range it is more to the opposite: the data should be wide enough that the quatization noise is only a minor issue. So a resolution higher (at lest some 2-3 bits) than the ENOB is useful.  So with some of the better 24 bit SD ADCs one may wish for a few more extra bits in the result, though one can often get around this by reading faster and average externally.
The good INL is precious and a resolution better than the INL specs makes absolute sense - it makes little sense if the resolution limits the INL in this performance range.
Wanting INL better than 1 LSB made some sense in the old days at the very high speed with low resolution (e.g. 8 Bit  and > 1 GSPS), but even there the FPGA / data handling is usually no longer the bottleneck and an extra Bit of resolution is usually wellcome even the LSB is than smaller than the INL.

What I see is rough violation by AD common practices for test equipment: put a sticker if a module  poses a threat for external test SG or other test equipment  not complying with 50 Ohm input spec. And AAF 10 Oms & 10 nF may demage SG at 500 kHz.

Function generators and essentially all RF test gear does survive a short at the output. They don't need the 50 Ohms for protection, but to get low reflection and well defined performance. The rare cases (some RF power amplifiers) when a test gear does not like the reflections from a short or an open input there should be a warning on that instrument. They use the RF type connector on test boards also also for other signals - even more DC ones and without the usual 50 Ohm termination. The SMA connectors are just convenient and reasonable priced.

 

The MCP3561 noise and INL performance are still inferior at 4 kHz compared to the AD4630 with averaging. The same advantage from oversampling also applies to the SAR ADC. The comparison is a bit tricky as both give different quantities. The AD4630 gives some 136 dB DR for 1000 fold oversampling, that should about compare to an OSR value of 2048 or 4096 with the MCP3561 with some 3-4 µV of RMS noise  wich would be around 120 dB DR. So about a 16 dB advantage for the AD4630.

>>> LNA at the input of the MCP3561 (TLE2027 50 nV/ sqrt(Hz) or similar would bring 40 dB. 

An amplifier at the input does not improve the DR of the ADC. It can help for the total system, but the same also applies to other ADCs.
With that much noise, I very much doubt the amplifier would help very much. The input noise of the AD4630 is at some 18 µV RMS for 2 MSPS and thus around 18 nV/sqrt(Hz).
The TLE2027 gives a considerably lower noise (~ 3 nV/sqrt(Hz)) - still this only helps the system not the ADC directly and no way near 40 dB. It may provide 40 dB  of gain, but than the amplifier noise would limit the DR even more than the ADC.

[iMo]

What Kleinstein indicates above means - with enough ADC resolution even the larger INLs are acceptable, because you can correct the ADC results numerically. Small INLs are required when you have no capability to provide the numerical correction to the incoming data. INL is usually hidden in the noise and you have to process the incoming data first, otherwise you will not see the INL. With say 18uVrms noise you are at 100uVpp noise in the data, with say 2Vpp input that is XX times more than the INL..

[KT88]

One aspect is that a better INL is desirable because the INL won't be infinitly stable over temperature and other disturbing factors. Without total isolation from the ambient a 10-ish improvement should be possible (only an educated guess though).
Another aspect is that oversampling (averaging) is a trade-off between signal bandwidth and dynamic range. This is what happens when one chooses a higher number of PLCs with a 3458A (or other meters) the reading of the last digits gets more stable.
The rms noise in the 1st nyquist zone doesn't tell anything about the accuracy of the ADC. It can be orders of magniude higher than the INL. In fact the ADC cores have inentionally noisy LSBs in order to allow for a better averaging result. One reason for the noise of the LSBs is dithering, which blurs the DNL over a wide range of codes. The result of dithering together with a very random dither-code distribution achieves the high linearity of the samples even below 1LSB...

[MasterT]

What Kleinstein indicates above means - with enough ADC resolution even the larger INLs are acceptable, because you can correct the ADC results numerically. Small INLs are required when you have no capability to provide the numerical correction to the incoming data. INL is usually hidden in the noise and you have to process the incoming data first, otherwise you will not see the INL. With say 18uVrms noise you are at 100uVpp noise in the data, with say 2Vpp input that is XX times more than the INL..

I like to tweak /hack / overdrive dsp parts, adc and dac, but not with $200 boards.  Would expect clear explanation how each parameters defined, in what test conditions etc. W/o any speculation, what could be done or why I can't get same good pictures like in DS. I respect Microchip, for less ad on the front page.

And second, I'm sure AD already did numerical correction internally,  nothing to squeeze out when 0.1 ppm linearity speaks. Seen recently some TI products call it "background calibration" in the description. Technology I know since 1989, when it was invented for multi-slope ADC.

[KT88]

Would expect clear explanation how each parameters defined, in what test conditions etc. W/o any speculation, what could be done or why I can't get same good pictures like in DS.

Here you go: https://www.analog.com/en/education/education-library/data-conversion-handbook.html