The INL is not directly limiting the useful resolution. So 24 bit resolution can still be there even with 100 ppm INL. With higher resolution it is quite normal that the INL error can be considerably larger than 1 LSB.
>>> Non sense for me. It does limit, anything below INL line is a fake, garbage to discard not bothering to push over data bus.
I'd prefer other way around, have 12/ 16-bits with better INL < 10ppm
I also prefer INL lower than 1 LSB, but this is essentially not possibly with better than 12 bits. As long as the curve is monotonic (DNL < 1 LSB) the resolution is still usefull, especially as the INL error is the maximum error and this often applies to the upper / lower end of the range (like the extreme 10%) or a few special points.
Essentially all 24 Bit ADCs have an INL error larger than 1 LSB: the 3458 DMM and the AD4630 are about the only ones were the INL is at least close to 1 LSB (at 24 bit). The input buffer for the AD4630 may limit that.
Especially with SD ADC it is common to give a 24 bit resolution, as the data are send in 24 data format. The noise is often higher and quite often the INL is in the 5 ppm range. With SD ADCs the numerical resolution is cheap and they can thus use the computer typical steps like 16 / 24 / 32 bit for the resolution. There is absolutely no need to have the quatization noise as the limit - in the high resolution range it is more to the opposite: the data should be wide enough that the quatization noise is only a minor issue. So a resolution higher (at lest some 2-3 bits) than the ENOB is useful. So with some of the better 24 bit SD ADCs one may wish for a few more extra bits in the result, though one can often get around this by reading faster and average externally.
The good INL is precious and a resolution better than the INL specs makes absolute sense - it makes little sense if the resolution limits the INL in this performance range.
Wanting INL better than 1 LSB made some sense in the old days at the very high speed with low resolution (e.g. 8 Bit and > 1 GSPS), but even there the FPGA / data handling is usually no longer the bottleneck and an extra Bit of resolution is usually wellcome even the LSB is than smaller than the INL.
What I see is rough violation by AD common practices for test equipment: put a sticker if a module poses a threat for external test SG or other test equipment not complying with 50 Ohm input spec. And AAF 10 Oms & 10 nF may demage SG at 500 kHz.
Function generators and essentially all RF test gear does survive a short at the output. They don't need the 50 Ohms for protection, but to get low reflection and well defined performance. The rare cases (some RF power amplifiers) when a test gear does not like the reflections from a short or an open input there should be a warning on that instrument. They use the RF type connector on test boards also also for other signals - even more DC ones and without the usual 50 Ohm termination. The SMA connectors are just convenient and reasonable priced.
The MCP3561 noise and INL performance are still inferior at 4 kHz compared to the AD4630 with averaging. The same advantage from oversampling also applies to the SAR ADC. The comparison is a bit tricky as both give different quantities. The AD4630 gives some 136 dB DR for 1000 fold oversampling, that should about compare to an OSR value of 2048 or 4096 with the MCP3561 with some 3-4 µV of RMS noise wich would be around 120 dB DR. So about a 16 dB advantage for the AD4630.
>>> LNA at the input of the MCP3561 (TLE2027 50 nV/ sqrt(Hz) or similar would bring 40 dB.
An amplifier at the input does not improve the DR of the ADC. It can help for the total system, but the same also applies to other ADCs.
With that much noise, I very much doubt the amplifier would help very much. The input noise of the AD4630 is at some 18 µV RMS for 2 MSPS and thus around 18 nV/sqrt(Hz).
The TLE2027 gives a considerably lower noise (~ 3 nV/sqrt(Hz)) - still this only helps the system not the ADC directly and no way near 40 dB. It may provide 40 dB of gain, but than the amplifier noise would limit the DR even more than the ADC.