AD4630-24 new SAR ADC from Analog Devices

[Kleinstein]

The AD data conversion handbook is great and shows quite a lot about the testing. However there are still a few somethwat open points, like the ADC drivers used and how and if the INL par the ADC dirver is included or maybe not.  The PCB iterations show that it is not just the ADC chip that matters, but as it looks like also the layout and other parts around the chip.
The same also applies to most SD ADC chips - even of they have a slower data rate, the actual input sampling can be even faster and more nasty to drive.

[KT88]

@ Kleinstein: I fully agree: there is much more to know about precision analog and mixed-signal circuit design. Another good read is the following:
https://www.analog.com/en/education/education-library/linear-circuit-design-handbook.html
In particular Ch.12 deals with PCB design.
Apologies for being a bit Analog Devices heavy but searching for Handbook scores a metric ton of material https://www.analog.com/en/education/education-library/op-amp-applications-handbook.html
Unfortunately or interestingly (however one looks at it) there is much more to learn...

[MasterT]

The AD data conversion handbook is great and shows quite a lot about the testing. However there are still a few somethwat open points, like the ADC drivers used and how and if the INL par the ADC dirver is included or maybe not.  The PCB iterations show that it is not just the ADC chip that matters, but as it looks like also the layout and other parts around the chip.
The same also applies to most SD ADC chips - even of they have a slower data rate, the actual input sampling can be even faster and more nasty to drive.

Right. It's competitive world, in between major players / companies as well as between countries / blocks. Cold war never stops, just went to a shadow for a while.
Though, when I see 60 pF, it rings me a bell of the "sabotage technology".  SD ADC has much lower sampling capacitance.
And it's still the question how AD takes Figure 17 if one best the best their OPA (recommended to use by AD) can't provide such performance even close.

Books the same shit, nobody in the sane state of mind would publicly disclose internal whereabouts theirs product.

[KT88]

OK, if the sample cap bothers you - there is a remedy: https://www.analog.com/en/products/ad7134.html?doc=AD7134.pdf#product-overview.
 

[iMo]

I like to tweak /hack / overdrive dsp parts, adc and dac, but not with $200 boards.

I would not expect from that board the same as from a 3458A. I do not know what you actually want to do with the board, but when targeting precision DC measurements I am pretty confident you will get flicker free 7.5 digits out of the board easily. Easily means - with something like 10-20 seconds "equivalent averaging time". I have here 2 boards (18y old AD 24bit SD eval boards) and it works that way.
With 0.6uVpp input noise at lowest possible sampling rate (as shown in previous posts) with say +/-2V ADC input range your 1LSB is 2/(2^23)= 240nV, and 0.6uV/240nV = 3. That is with shorted inputs where the noise of Vref does not apply, under real conditions while measuring say 10V DUT reference against your Vref, the noise in your data will be much higher, my bet you will see something like 3-6uVrms (the standard deviation in your data) when lucky, therefore you would need longer integration times to see flicker free 7.5digits. After you see that flicker free data you may start to compensate the INL, the TC and cope with other issues involved..

PS: .. like 61Hz "sampling rate" == 2MSPS/32768.. + the mcu averaging..

A. 2MSPS, microcontroller averaged x32768 = 0.62uVpp
B. 2MSPS, onboard averaged x32768 = 0.65uVpp
(10 second sample block [i.e. 30.5 - 0.1Hz] peak-peak values averaged over 15 minutes [90 blocks])
Improved layout has solved the additional noise issue I was seeing. It's interesting that the microcontroller averaging is slightly better (it's a very stable 2 decimal places, no margin of error issues here), I suspect it's due to the loss of bits in the onboard averaging filter.

[Kleinstein]

The relatively high sampling capacitance is kind of needed, because of the KT/C sampling noise limit. High performance SD ADCs chips (e.g. AD7177 or similar) of the switched capacitor type also need a relatively high sampling capacitance, though they can get away with a little less due to a higher sampling frequency. However this shifts the driving problem to even higher frequencies. With a switched capacitor ADC one kind of has to choose your poison: higher capacitance or high frequency sampling. As the capacitance on the chip is expensive it is not such a surprise the rather high conversion speed and oversampling is the way to get very low noise. In this view the the 2 MSPS raw conversion rate is still relatively moderate. I would not be surprisef to see even faster similar ADCs, possibly without acess to the raw data before averaging.

The extra precharge amplifier is already a way to reduce the kickback from the relatively large sampling capacitor. If the current pulse is reduces enough, one does not really care the actual size of the capacitors (it still effects the price though).
The idea is not totally new: the AD7768 SD ADC already has this in a similar way.

The way with fast conversions and than averaging makes absolute sense: it gives a flexibilty to use the same chip for different speeds and simplifies the AA filter. For the user it does not make that much difference if the input is sampled by an SAR or SD converter in the MHz range. It looks like the SAR type converters somehow, surprisingly get the better INL.

[KT88]

The noise floor stays the same regardless of the sample rate. The final result depends on the number af samples averaged.
The precharge of the sample cap removes a lot of the challenges with the input buffer. This is limited to low frequencies though because it only works for small deltas between two samples. For high frequencies and muxed inputs the pre-charge has no advantage...

[MasterT]

I did testing with ad7988-5, ad7693, ad7982, ad7984 modules  and non of them has cap at the input, only suspiciously low resistance (600||600 = 300) that I always removed before testing.

Some pictures posted here:
https://ez.analog.com/data_converters/precision_adcs/f/q-a/544153/eval-ad7982-pmdz-high-thd-3-level

It;s not only sampling cap that's trigger my 6-th sense , but also input AAF on evaluation module.
Since ADC has beautiful digits in DS for BOTH DC (linearity) & AC (THD) why someone would over complicate, actually de-rail any possibility to evaluate ADC with sine wave sources?
 Bla-bla-bla about RF, noise, etc not acceptable - jumpers cost nothing compare to IC itself.

[KT88]

Ok, now I see your point... This is just a generic EMI filter. As you can see in the schematic, there are a lot of optional parts in the circuit to allow you to configure the circuit to your needs. As pointed out in an earlier post, this ADC is more advantagous for lower frequencies down to DC.
Deleting or reducing the input caps won't be an issue if no noise is introduced through the setup of the signal source....

[MasterT]

My guess is,  uCPU numerical correction in ad4630 is the Only  difference from  AD798X product lines.

I'm also quite well understand that crunching data 2 MSPS / 24-bits  more efficient than 8 MHz / 1-//-4-bits (SD ADC like max11270 or mcp3561) in the noise reduction aspect.

 Though, if great Sisyphean labour /efforts were put into DC spec. improvement, why there is no noise reduction in the Reference path? What, noise spec. measured with inputs shorted? Still smells toxic , IMHO




 

[Kleinstein]

Reducing the reference noise is not that easy. The chip already includes some reference filtering for the higher frequency part. More can be done externally, but the typical large capacitors are more an external thing and it depends on the refrence used.

Measuring the noise with shorted input is kind of standard, as this case is easy to reproduce. Any other voltage needs extra effort and may introduce extra noise depending on the details of the implementation. Ideally one would have additional points, but testing such an ADC already takes long enough and the data-sheet are already quite long.

[MasterT]

Reducing the reference noise is not that easy. The chip already includes some reference filtering for the higher frequency part. More can be done externally, but the typical large capacitors are more an external thing and it depends on the refrence used.

Measuring the noise with shorted input is kind of standard, as this case is easy to reproduce. Any other voltage needs extra effort and may introduce extra noise depending on the details of the implementation. Ideally one would have additional points, but testing such an ADC already takes long enough and the data-sheet are already quite long.

1. Easy, not easy - who care if cost is not > 10% of the module?
2. Capacitors don't play any role here, since output impedance is very low and a few Farad capacitance wouldn't reduce 0.1-10 Hz at all. 
3. Don't care also for standard, absurd for me. Was trying to figure out noise level out of the DS FFT plot, but AD (intentionally?) doesn't mention FFT size, so can't compare with an experimental data I have for mcp & max SD ADC.  BTW, microchip DS about 100 pages, with complete description including internal architecture, and does indicate FFT sizes.

 

[KT88]

Something to consider: Both the LTC6655-5 and the show +/- 500nV peak noise at 10Hz bandwidth. This is +/- 0.1ppm peak. Further averaging like 100PLC would get it ever further down...
I don't think this leaves a lot to complain...

[KT88]

@MasterT: If we start to compare the AD4620-24 with the mcp3561, let's just compare Gain drift: 0.025 vs. 0.5 ppm/°C. That is a 20x difference or comparing apples with....potatoes

[iMo]

But the difference between the apples and potatoes plays no role with LTC6655-5 (max 2ppm/C) 

[KT88]

Sure - that's more a play for LTZ-/ADR1000...

[MasterT]

Something to consider: Both the LTC6655-5 and the show +/- 500nV peak noise at 10Hz bandwidth. This is +/- 0.1ppm peak. Further averaging like 100PLC would get it ever further down...
I don't think this leaves a lot to complain...

Nothing of the kind. We have SAR, 2 MSPS so this "backdoor" open widely up to 10-th MHz, I mean reference input port, noise level counts up to x1000 times.
Well if not x1000 due HF attenuation done inside ref chip and caps help, but at least up to 10-30 uV.

 Where is this  −166 dBFS/Hz  now?  Under  cat's tail?

[Kleinstein]

There is some filtering for the high frequency part of the reference noise. So not much aliasing there and the upper BW limit would be around 1 MHz.  If oversampling and averaging is used for higher precision (e.g. to get 10 Hz BW) this also applies to the reference noise.  So it is a comparison of the ADC noise and reference noise density (after scaling if needed). If I got the math right the ADCs white noise is around 18 nV/sqrt(Hz) - compare that to some 40 nV/sqrt(Hz) for the LTZ1000 at 7 V and  thus about 20 nV for a 3.5 V signal. So  for the white noise part they are about on par and as far as I understood the 1/f noise  of the ADC is not great, but still a bit better than the LTZ.

How much of the reference noise is effective depends on the actual voltage measured and this usually is less than full scale.

The NR part of a reference can help for the higher frequency noise, but is usually not effective below some 100 Hz or even lower. So for the near DC use (e.g. a DMM) the noise reduction is not helping that much.  Some extra noise filtering for the reference makes  absolute sense, especially for higher data rate use (e.g. audio), where filtering is feasable. The REF61xx is however noisy below some 1 kHz even with the NR capacitor - so of limited use for the audio band, but OK for the higher frequency part.

[MasterT]

 I'm afraid things more complicated, than simple noise math equations.  Since we have switched capacitor load for voltage reference, output impedance of the voltage reference may have more importance than noise level itself. 
In the middle frequency range ~ 1 kHz, where capacitor 47 uF have R-react. = 3.3 Ohm and doesn't help much with settling time, likely inter-modulation / interaction processes would happened, so ADC turns into noise generator as well.
I see TI starts to characterise REF61xx specifically for this case - sourcing high resolution / high speed SAR ADC.
 Zenner  as a voltage reference, shunt TL431, another series,   slow / weakly buffered references may be wrong type in this case, despite how low noise level they may have.

 And it also imply, noise tests for ADC with shorted inputs dumb stupid things, well, at least for high speed SAR ADC.
 Have to ask AD for FFT plot clarification.

[KT88]

I'm afraid things more complicated, than simple noise math equations.

Yes, indeed!

[Kleinstein]

An oversampling SAR ADC does not care very much about the 1 kHz range impedance of the reference. 1 kHz is also rather easy to buffer. Unless the input signal has a lot of content at 1 kHz there is essentially no ripple current at 1 kHz. The switches capacitor part gives ripple in the > 2 MHz range and this is dominated by the capacitors and not the reference chip. Here it only matters how good the reference can handle a low ESR capacitor at the output.  This can be different with a SD ADC, that can show significant ripple in the reference current at some idle tones. Here the reference impedance at some intermediate frequencies ( e.g. 100 kHz) may effect the INL (not so much the noise). So espeically for the SD ADCs it would be good to note more details for the INL specs (e.g. what reference and what input driver).

The Ref61xx output buffer seems to be good for the high frequency range (e.g. > 10 kHz) and there the NR capacitor also works well. However it somewhat fails in the low frequency range and is quite noisy there. So it may be a good reference for a high speed ADC, unless one uses this ADC to measure low frequencies or "DC".
The LTC6655 on the other side is quite good for the low frequency part, but the buffer does not provide very low impedance at the high frequencies - still not bad and maybe sufficient for many uses. If needed one may have to add an extra reference buffer.


The reference part is a bit tricky for switched capacitor ADCs - both SAR and SD types. Similar the input driver is difficult and possibly limiting for high perfomance ADCs. This however does not mean that the noise test with a shorted input is stupid - more the opposite: the shorted input is less effected by the reference and can in theory even skip the input driver. It is thus easy to reproduce and well defined and a good test. Noise wise the input driver is usually not that limiting (maybe for the 1/f part). The reference driver part can still be relevant, even with a shorted input.

It is always good to have more information and an extra test with a different test point (like 1/2 the full scale) would be nice, but this is not so easy and depends more on the details external to the ADC chip. This is more a test for the complete circuit / system, not so much an important point in the ADCs data-sheet.

[MasterT]

1.
An oversampling SAR ADC does not care very much about the 1 kHz range impedance of the reference.
2.
 Unless the input signal has a lot of content at 1 kHz there is essentially no ripple current at 1 kHz.

1.
 Oversampling is loosing effectiveness for any NON multiple AC frequencies presented at the input. In other words, practically for anything.
2.
 Who says it does not?

 We are discussing   -167 dBc noise level, if I remember, and if someone (TI) starts to worry about InterModulation with 16-18-bits,
"essentially no current" has to be printed in digits rather than in emoticons for 24-bits, would you think?

[KT88]

1. Oversampling allows a trade-of between Bandwidth and dynamic range.
2. RTFDS - it's 167 dBc/Hz which is a figure of merit like gain-bandwidth-product for an opamp. I never heard that anybody claimed it to be BS because one looses bandwidth when setting a gain>1!

[Kleinstein]

Together with a little anti aliasing filtering at the input the oversampling ADC approximates an integrating ADC. With internal averaging the AD4630 gets quite similar to a SD ADC of switched capcitor type (the usualy versions).  For the input side it sees similar sampling and the frequency response is set by the digital filtering/averaging. Oversampling works OK to reduce the noise - no need for special frequencies.  For later use it helps to set the length for averaging to be a multiple of a power line cycle. This is for hum suppression and not for noise reasons.  Hum may be mistaken for noise in some cases and it is good to get extra hum suppression.

The source impedance of the reference matters when there is ripple current - without a ripple current there is little effect if the reference impedance is a little higher.
The SAR ADC inputs seem to draw a current about proportional to the input voltage, and with a differential drive the current (as the sum) would be essentially constant.
Chances are the reference driving is more critical with a single sided drive compared to the differential drive case. The INL also looks a little better with differential drive.
I would expect a relatively similar reference current for a SD ADC, at least for the lower frequency part. With an SD ADC there is additional AC current from the internal modulation and at some points idle tones (frequencies quite a bit lower than the modulation / sampling frequency). The SAR ADC has no such Idle tones but could have multiple smaller peaks that repeat with the sampling frequency. With many SD ADCs differential drive also has an advantage for the INL.

It is a bit confusing that they call the ADC 24 bit and 2 MSPS. At 2 MSPS the noise is naturally higher and the effective resolution is more like 16 bits, though the digital data still have more bits. They get 24 bit resolution (and even a little more) with oversampling and averaging at a lower speed.
You find a rather similar picture with SD ADCs, like the MCP3561:  At the highest speed (some 150 kSPS)  the effective resolution is at some 15 bits and at the lowest speed may exceed 23 bits by a little.
So in both cases one can trade  BW for resolution and at the highest speed the noise levels are way higher than the nominal resolution. In both cases this is oversampling at work. For the quatization noise the SD ADC can have some additional advantage from the noise shaping and a noise reduction faster than the normal square root of N. This however only applies to the quantization noise and not to other noise sources, like the capacitor sampling (reset) noise. For these noise sources there is the classical square root law from averaging / reduction of the bandwidth.

[iMo]

"32bit 1MSPS" with LTC2500-32, or "24bit 2MSPS" with this one, or any other ADC - that is how it works since ever with marketing those chips. Afaik, all those datasheets include detailed tables on oversampling or sampling rate vs. achievable resolution, or sample noise, or noise free bits, etc. So looking at those tables is the first step when evaluating the situation, whatever the title page show..