AD4630-24 new SAR ADC from Analog Devices

[KT88]

And the elephant in the room:
A guy rudely mocking against oversampling SAR-ADCs is in favour of SD-converters - an ADC toplogy fundamentally based on oversampling! 
Also some multi-bit SD-ADCs entertain a low-res SAR these days....

[MasterT]

Non coherent stream of wikipedia BS, or provocative jokes clear signs of AI. 

AI is not capable to understand FFT , newer will be.
So it was expected.

Dose of holy water was injected.

[Echo88]

Are there any infos wether its necessary to use a external reference buffer for the AD4030-24/AD4630-24 to get the specified INL/noise or is the internal ref buffer sufficient?
In the AD4630-24-presentation they show the ADA4523 used to drive the inputs and the reference input for the high accuracy example configuration, whereas in the high speed variant the LTC6655LN is used without a driver...

Also im wondering which ADC-averaging/µC-averaging-configuration would be optimal to get the highest digital filter attentuation for 50Hz hum for ADC usage with say ~10Hz sample output rate?
The ADC uses a internal clock source, so when i use the internal averaging filter only the internal clock wil contribute to the ADC-noise with its jitter and not the triggering of the external CNV-pin?
Havent yet looked completely trough the datasheet, does it have a continuous sampling mode?

The idea of using a single ended amplifier for the AD4030-24 is interesting, would it really achieve the same specs as a differential HPM7177-frontend since the AD4030 generally has +3dB SNR compared to the 2-channel-version AD4630-24 like user macaba suggested?

[Kleinstein]

The DS shows an integrated buffer for the reference. In single ended mode the ref input current (after the buffer) depends on the signal and this may lead to some more INL error (especially a square part). So for single ended mode one may need a good reference buffer to get the best INL.

For the digital filtering there are different options, especially if part of the filtering is done externally. More internal filtering reduces the data trafic and this can help and also allow a less powerfull µC to do the final averaging.
As the clock is somewhat variable for best 50 Hz suppression one would adapter the filter to the actual ADC clock and thus use not very much ADC internal averaging.  There are many options for a digital filter:
Sinc1 is simple averaging over a set aperture and the easiest but with limited 50 Hz suppression if the length does no perfectly fits. 0.1 % matching would result in some 60 dB hum suppression.
It is not just the internal oscillator, but also the mains frequency that is somewhat variable. Just adapting the window length to the actual mains frequency is a real option.
The ADC internal averaging limits on how fine the aperture can be adjusted.
Sinc2 would give better hum suppression, but also more longer settling / apperture for the same noise BW. So one has to compromise somewhat.
There are other similar filter that can provide better hum suppression, but at the cost of more math needed.

[Echo88]

Hmm, since i never really was much into programming i do my simple µC-stuff with arduinos.
The Due with its SAM3X8E at 84MHz should be fast enough to handle the SPI-traffic when the ADC itself already does some averaging, especially when using all 4 SDO-lanes.
Does that provide enough room to implement a Sinc2/3-filter like its done in a SD-ADC or would i need a FPGA?
Would be nice to be able to have the choice between filters and the corresponding step response to optimize it for a given task.
Gotta read more about those filter topics and their µC-implementations.

I think i will implement both options for the reference on my test board: with and without buffer OP.
Why would the ref input current differ between single ended/differential input mode?

[Kleinstein]

It looks like the ref input current varries about linear with the input voltage. I see this like compensating some change for eche conversion. In differential mode it looks like there are 2 more or less identical ADCs for both sides and there currents in the sum stays about constant, as one goes up and the other goes down.

AFAIK the sinc2 and sinc3 filters are still rather simple and the 84 MHz µC should be able to do the math in real time, especiall if the data are reduced by something like a factor of 8 by the ADC. The crude averaging at the ADC should not make a big difference to a calculations with all the data -  some fine changes in the 50-500 kHz range. The question is more the required memory. With a variable overall aperture due to the possibly odd clock ratio one may have to do some minor modifications to the filter (e.g. adjust the overall lenght in the center part). It would not matter if the filter is only close to a sinc2, as long as the main properties like good hum suppresion are still there.

[Echo88]

What amount of low frequency noise can be expected from the AD4030-24 for BW 0.1-10Hz and say ~20Hz SPS?
The datasheet states 1.3µVpp but according to Figure 24 they use 2048 averaged Samples, which would lead to a sample rate of 19.5SPS * 2048 Samples -> ~40000SPS, while the ADC is capable of generating 2MSPS.
Am i wrong in that calculation/thought-process or should the ADC be better specced for the 0.1-10Hz BW when using the full 2MSPS?
The AD7177-2 meanwhile claims 0.5µVpp in Table 6 at 16.66SPS and 4.5µVpp (2.5Vref) 0.1-10Hz voltagenoise on page 5...

https://www.analog.com/media/en/technical-documentation/data-sheets/ad4030-24.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/ad7177-2.pdf

[coppercone2]

I wanna see someone do something that needs those bits

I wonder some kind of sintering experiment could make use of that

its awesome but... we don't have a god damn LHC. I know its also useful for radiation dating in some big ass machine but still that had a few million dollar price tag associated with it.

[KE5FX]

OK, if the sample cap bothers you - there is a remedy: https://www.analog.com/en/products/ad7134.html?doc=AD7134.pdf#product-overview.

Data sheet copyright date:



Product page:



This isn't funny anymore. 

[Kleinstein]

The AD4134 is a pretty much direct replacement for the AD7134 - so no need to worry that much. It could still be inconvenient if this need a PCB change, as at the high end level the PCB design can be critical.

I wanna see someone do something that needs those bits

I wonder some kind of sintering experiment could make use of that

its awesome but... we don't have a god damn LHC. I know its also useful for radiation dating in some big ass machine but still that had a few million dollar price tag associated with it.

The question on where do we need such an ADC is a good one.  Though likely not the intended use, one possible customer could be high end audio, for those who want super low noise and THD.
The large dynamic range could be of good use in a spectrum analyser / dynimic signal analyser - though the speed may be a bit on the low side for more general use.
A reasonabel use may be a digial lock in amplifier - so to resolve relatively small signals from a noise background. For most cases the AD4630 would be overkill, but with a noisy signal and could help to save on analog filtering.

[Echo88]

Possible applications include:

Dynamic signal analysers,
DMMs,
to build high resolution/accuracy DACs like shown in AN86,
high resolution/accuracy temperature or resistor measurement,
usage of ultra high range sensors like seismometers of photodiodes,

Can i get an opinion on my noise question please?

[iMo]

What amount of low frequency noise can be expected from the AD4030-24 for BW 0.1-10Hz and say ~20Hz SPS?
The datasheet states 1.3µVpp but according to Figure 24 they use 2048 averaged Samples, which would lead to a sample rate of 19.5SPS * 2048 Samples -> ~40000SPS, while the ADC is capable of generating 2MSPS.
Am i wrong in that calculation/thought-process or should the ADC be better specced for the 0.1-10Hz BW when using the full 2MSPS?
..

My bet would be the 1.3uVpp in the Figure 24 is the best what you can get (~200nVrms).
That is at the lowest possible internal SPS setting.
The higher the sampling rate the higher the noise, afaik. And the additional internal averaging (still 32x to make) does not compensate for the higher conversion noise with 2MSPS, it seems..
You may go lower with the noise with an external averaging, imho.

PS: ..imho you cannot go lower with SPS as that SAR ADC uses capacitors instead of resistors..

[Kleinstein]

I interprete the  "Low Frequency Noise (Output Data Rate = 19.5 SPS After Averaging Blocks of 2048 Samples)"  as using 2048 samples averaging inside the ADC chip and than additional external averaging of 50 samples to get to the 19.5 SPS nominal sampling rate. So the ADC wold still run at the normal 2 MSPS.
It is not very clear un what conditions the curve is measured.

A point I could not find are details of the 1/f noise or other extra low frequency noise. This may also depend on the parts around the ADC and PCB details.  At the low noise levels of this ADC some residual mains related hum could be an issue and may show up the 0.1 - 10 Hz measurement, as the 19.5 SPS is not able to suppress 50Hz and is not good for 60 Hz hum. This is especially the case with the ADC clock that is not very accurate, but normally an internal clock.
It depends on the application on how important the low frequency noise is.

[KT88]

Although the noise amplitude increases with the sampling rate because of the wider bandwidth, the dynamic range increases and with that the noise amplitude if the output data is filtered / averaged.
To make ADCs more comparable the spec / FoM of "NSD: −166 dBFS/Hz typical" is shown. This means the NSD at a bandwidth of 1Hz.
A quick and dirty way to calculate this is to calculate 3dB/octave for the oversampling filter and take the nyquist frequency as the starting point e.g. 1MHz for the full sample rate of 2MSPS... This figure is also known as 'process gain'.
If we take the roughly 106dB of SNR we can add the process gain to that number.
This also shows that you lose dynamic range if the sample rate is reduced.
1/f noise should not be present with recent SAR converters as they usually entertain some sort of AZ technology.
One thing that my look like 1/f noise could be wide bandwidth noise that is folded down into the low frequeny region. For this task the input R/C circuit doubles down as an AAF for high frequency noise of the ADC-driver...

Edit: As an example, the SNR is about 106dB and 1Hz to 1MHz are 20 octaves resulting in 60dB of process gain (20 x 3dB). As the result we get the *NSD: −166 dBFS/Hz typical* mentioned in the data sheet (106+60).

Cheers

Andreas

[Kleinstein]

Ieally there should be no 1/f noise, at least not from the main signal path. However when looking for details and small contributions there usually still a little bit of extra low frequency noise comes in. This can be things like variations in the internal clock that somehow translate to a variable offset or variations in the supplies or just thermal effects.  In a more normal circuit resistors can contribute to 1/f noise.

When looking at frequencies well below 1 Hz there is also addition noise in the SD ADCs like AD7190 and many AZ OPs. It may be not much, but quite often there is some if one looks hard enough (low enough in frequency).

[Echo88]

I completely forgot about the test that Macaba already did on the AD4630-24, with a result in post 45 of this thread:

"A. 2MSPS, microcontroller averaged x32768 = 0.62uVpp" at 61SPS

Missing/omitted parameters/specs and the missing explanation of how they measured this stuff ("biascurrent of older AZ-OPs? Measuring it takes time and costs money, lets calculate it  ") is a bane of existence.

With the knowledge of the approximate realistic lowest noise i can now try to design a more suitable adc-driver.

[iMo]

What he wrote is:

A. 2MSPS, microcontroller averaged x32768 = 0.62uVpp
B. 2MSPS, onboard averaged x32768 = 0.65uVpp
(10 second sample block [i.e. 30.5 - 0.1Hz] peak-peak values averaged over 15 minutes [90 blocks])

Does the 90 blocks averaging apply for A and B?

[coppercone2]

Well I asked about this, and a 'direct' application of nanovolt measurements is sintering. Apparently you can measure the conductivity of materials as they are being sintered to get the proper 'bonding' or whatever you want to call it. Like powdered metal parts (titanium, stainless, so forth)

That sounds like something useful for DIY parts. That's what I was getting at, can this enable you to do anything NEW, not slightly better. The problem for me is that I have a DSA already (and you can get them cheap sometimes, like me), and yeah.. maybe it could lower the noise floor a little if you made it, but damn I just don't feel compelled. The whole making a seismograph/sensor is actually the hard part (its almost always precision expensive mechanical engineering that you need to benefit from these parts).

Experiments with strain sound possibly cheap (maybe just a heavy screw and a heater would be enough with a crude die. At least it does not feel like a mega project to think about compared to some other nanovolt things, since you are just essentially measuring a resistor directly.

[branadic]

Another possible application can be an atan2-interpolator for high-resolution encoders and other 1Vpp sin/cos sensors.

-branadic-

[Kleinstein]

Measuring resistance changes is usually easier and better done with a bridge circuit of some kind instead of a more DMM like circuit with current source and votlage measurement. A high qualtiy ADC could to a certain degree replace one half of a bridge  (use a 24 bit ADC instead of 2 good resistors - which is not as stupid as it sounds at first). However a transformer may be the better alternative.

Sintering experiments are usually done at elevated temperature and this makes it really difficult to keep the temperature stable enough, so that resistance changes are not dominated by thermal effects.

Unless there is a way to use an external clock for the ADC, I see some problems in using this ADC for anthing else than raltively low frequency signals with averaging or maybe more randowm samples RMS measurements.  With a significant AC amplitude the timing jitter would be a rather big contribution to the overall noise. To really make full used of the high speed (e.g. for 100 kHz range AC signals) one would normally also want state of the art (ps range), low jitter timing.

[KT88]

Unless there is a way to use an external clock for the ADC...

RTFDS : p29
It is possible...

Cheers

Andreas

[MiDi]

What amount of low frequency noise can be expected from the AD4030-24 for BW 0.1-10Hz and say ~20Hz SPS?
The datasheet states 1.3µVpp but according to Figure 24 they use 2048 averaged Samples, which would lead to a sample rate of 19.5SPS * 2048 Samples -> ~40000SPS, while the ADC is capable of generating 2MSPS.
Am i wrong in that calculation/thought-process or should the ADC be better specced for the 0.1-10Hz BW when using the full 2MSPS?
The AD7177-2 meanwhile claims 0.5µVpp in Table 6 at 16.66SPS and 4.5µVpp (2.5Vref) 0.1-10Hz voltagenoise on page 5...

https://www.analog.com/media/en/technical-documentation/data-sheets/ad4030-24.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/ad7177-2.pdf

No idea why ADI choose such strange sampling for 0.1-10Hz figure, it is just nuts to give worse figure than what it is capable of 
Got 18uVrms@2MSPS from histogram, for mean of 2^15 samples gives 0.1uVrms or ~0.6uVpp, which is close to Macabas measurements (0.59uVpp).

[Kleinstein]

Unless there is a way to use an external clock for the ADC...

RTFDS : p29
It is possible...

Cheers

Andreas

The part around page 29 does not help - that part is discussing the clock for the serial interface, not the actual conversion.
It looks like there is no true clock to the ADC - more like  an external start of conversion signal (CNV) and than an internal timing for the individual steps of the conversion. So one can start the conversions quite accurate, but as it looks like not the start of the aquisation. So good 50/60 Hz suppression is possible, but when pushing the limits with the sampling rate, there could be some extra jitter / settling error.

[Echo88]

https://www.analog.com/media/en/evaluation-documentation/evaluation-design-files/eval-ad4630-24-design-files.zip

I was wondering about the DS-claim "CNV-pin needs low jitter clock to achieve ADC-specs" and how to fulfill it.
Am i assuming correctly that the CNV-circuit used on the AD4630-Evalboard (100MHz oscillator, inverter, FF, logic-level-shifter) is using the low jitter of the 100MHz oscillator, while enabling an arbitrary clock input via pin "CNV_FMC" from a µC or low grade oscillator, so one doesnt need to worry about jitter?

For example: 1.6384MHz (1638400 / 2^15 = 50SPS, filters 50Hz hum via the ADC-integrated Sinc1-Filter) as an oscillator is difficult to get, im thinking about using an available 3.2768MHz oscillator and generic /2-divider without needing to worry about jitter.

I found the internal 80MHz-clock/CNV-combination also weird. 

[KT88]

It looks like there is no true clock to the ADC - more like  an external start of conversion signal (CNV)

Correct - The bit decisions are self-clocked. The complexity of the bit decisions is much more complex than in early R-2R SAR cores. CapDACs have usually a couple of redundant bits as well as pipelined structures some times. External clocking won't make any sense for this type of ADC.
For the sampling of the incoming signal the edge of CNV is the defining moment. With the rising edge of CNV the sample cap disconnects form the input for roughly 300ns. After that it reconnects to the input and has 200ns to settle @2MSPS (hence the importance of the ADC driver to settle within this timing window).