ADR1399 reference

[DavidAzulay5000]

Next week I receive several units of the ADR1399
I started doing simulations in LTSPICE
to volt reference 10 volts
In your opinion, there is something to change in the circuit
I have a lot of vishay precision resistors 0.01%
of
10K
5K
2.5K
1K
100 ohm
Etc. etc
So I will use them
I have dozens of units

[iMo]

Here is an example re PSRR - the injected 200mVpp 50Hz hum into 15V Vcc translates into 3.7uVpp with the 1nF, and into 310uVpp with the 100nF feedback capacitor..

[Andreas]

@Andreas I have now added two 100nF caps (C6 &C7) directly at the pins of the ADR1339. One of which is now in parallel with the 5.1Ohm 1uF (R3 & C3) RC circuit from the datasheet which I also moved on the backside and very close to the pins. Is that correct or are those circuits redundant?

Hello,

C7 can only be used with a LM399
C3+R3 is needed by the ADR1399 for stability. C7 will lead to oscillations here.

With the output capacitance one shoud aim for C5 * R5  > 2*C6*R12 . So less than 100 nF should be OK,

its more like C5 * (R5||R4) > (C6 + CLoad) * (R12 + semiconductor resistances)
100nF is plenty but you do not need to optimize for speed.

with best regards

Andreas

[Andreas]

Here is an example re PSRR - the injected 200mVpp 50Hz hum into 15V Vcc

200 mV is insane.
if you have more than 5 mVpp you should work on your star grounding concept.

with best regards

Andreas

[iMo]

Here is an example re PSRR - the injected 200mVpp 50Hz hum into 15V Vcc

200 mV is insane..

That is just an example to visualize/demonstrate the issue. The larger the feedback capacitor the lower attenuation of a potential noise coming from the Vcc (provided the simulation works ok).. What is important is to see the ratio 1nF/100nF == 3.7uVpp/310uVpp.. Thus with your 100nF FB capacitor the Vcc noise attenuation (related to the 10V output) is 100x lower than with the 1nF FB capacitor..

[dietert1]

Yes, the simulation shows that for all practical purposes there is no problem. Use a power supply with less ripple and try various capacitors to find a small capacitance that gives good stability. I'm not shure the simulation can resolve this. One possible method to improve stability is a small capacitor from the opamp output to the output transistor base, once more like 1 nF or below.

One can also replace R4 10K by a JFET constant current source. With the zener between opamp and transistor one can run the opamp from the 10 V output voltage in order to eliminate supply drift/ripple going into the opamp. Then the only entry point left is the collector of the output transistor.

Regards, Dieter

[iMo]

@dietert1: Something like this..

[dietert1]

Yes, appears to work. As far as i understand ripple with 100nF is down from 310 to 9 uV. With a 1 nF capacitor you should be down from 3.7 uV to about 120 nV. At 200 mV supply ripple.

Regards, Dieter

[DavidAzulay5000]

 

[Kleinstein]

The use if the LT5400 for the gain is an interesting solution. Combining a separate resistor with the LT5400 array is not ideal, though may still be acceptable for only some 2% of the final voltage.

The suggested LT1113 in the plan is however not a good choice, as it has too much 1/f noise.  I would more look at LT1013, OP07, OPA202, OPA207 or ADA4077 or maybe an auto zero type like LTC2057 or MCP6V51.

It would make sense to plan for at least some filtering and an output stage that is capacitive load tolerant like discussed before.

[DavidAzulay5000]

The use if the LT5400 for the gain is an interesting solution. Combining a separate resistor with the LT5400 array is not ideal, though may still be acceptable for only some 2% of the final voltage.

The suggested LT1113 in the plan is however not a good choice, as it has too much 1/f noise.  I would more look at LT1013, OP07, OPA202, OPA207 or ADA4077 or maybe an auto zero type like LTC2057 or MCP6V51.

It would make sense to plan for at least some filtering and an output stage that is capacitive load tolerant like discussed before.

i am going to use the ltc2057 i order them the 925 ohm resistor is a 1k 20 turn trim pot

[iMo]

Do not use trimpots (10t/20t), those are source of instabilities. When you have to use a trimpot then with as small as possible value compared to the rest of the divider (1k is rather large value, imho).
The LT5400 ratio TC is <1ppm/C, thus the 925 ohm resistor contributes heavily to the overall TC. The trimmers are +/-50ppm/C typically.
Do a simulation over TEMP, for example:

.op
.step TEMP 20 40 1

with "R3=925 tc=30e-6"

as an example..

[DavidAzulay5000]

Do not use trimpots (10t/20t), those a source of instabilities. When you have to use a trimpot then with as small as possible value compared to the rest of the divider (1k is rather large value, imho).

My method is always to put TRIM POT resistors
At first
Check what the exact resistance value is after everything stabilizes
And after that replace the resistors with the exact value

[iMo]

Yes, appears to work. As far as i understand ripple with 100nF is down from 310 to 9 uV. With a 1 nF capacitor you should be down from 3.7 uV to about 120 nV. At 200 mV supply ripple.

Regards, Dieter

Output ripple so low that is not measurable in the LTSpice with 1nF and 200mV Vcc hum..

The situation changes of course with squared pulses (ie a switcher), with 200mVpp 2us/10us pulses the output ripple is around 600uVpp with both 1nF and 100nF and the OP07.

[DavidAzulay5000]

I have a problem with an error in the simulation in LTSPICE
Once I try to use the LTC2057

[iMo]

Attach your .asc file..

[DavidAzulay5000]

Attach your .asc file..

[iMo]

For example with 30ppm/C trimmer..

PS:
and the Vrefout change in ppm: with combination of a 25ohm 30ppm/C trimmer and a 900ohm -4ppm/C resistor (as an example).

[DavidAzulay5000]

For example with 30ppm/C trimmer..

PS:
and the Vrefout change in ppm: with combination of a 25ohm 30ppm/C trimmer and a 900ohm -4ppm/C resistor (as an example).

thanks i fix the error problem i update the ltspice and the error no more

[DavidAzulay5000]

For example with 30ppm/C trimmer..

PS:
and the Vrefout change in ppm: with combination of a 25ohm 30ppm/C trimmer and a 900ohm -4ppm/C resistor (as an example).

How do you make the graph of temperature in relation to voltage in LTSPICE

[iMo]

See the commands in my above simulation..
.op
.step TEMP 20 50 1
and after the simulation stops do select a voltages or currents (click on the node or wire in the schematics), etc..

[DavidAzulay5000]

See the commands in my above simulation..
.op
.step TEMP 20 50 1
and after the simulation stops do select a voltages or currents (click on the node or wire in the schematics), etc..

Attach your .asc file.. thanks

[DavidAzulay5000]

I managed to create the graph
But it's strange that for this I have to delete the entire part of the LT3083

[DavidAzulay5000]

I managed to arrange the simulation to include everything
And I also did a TRIM POT simulation
From a temperature of 20 degrees to 80 degrees
Strange the stability at 55 degrees

[mawyatt]

Maybe a dumb question but will throw it out anyway.

Do we know IF the models utilized in these simulations reflect the actual devices being simulated?

Are second/third order effects such as PSRR, chip heater effects, thermal gradients and so on included is such device IC models? Not to mention effects related to actual PCB implementation and the environment. Also, noted the discrete resistor TC seem to include the linear temp coefficients and not the quadratic effects, and what about the LT resistor array TC effects?

Best,