ADS1256 input offset behavior

[w42i]

I recently got one of the cheap ADS1256 boards available from Amazon, eBay etc., see attached image. The schematic and layout seems to be the same as in this post: https://www.eevblog.com/forum/projects/baidu-download-help-ads1256-ad-module-files/msg2880584/#msg2880584

There are some other threads discussing the reference voltage generation

• https://www.eevblog.com/forum/beginners/opamp-between-vref-and-adc/
• https://www.eevblog.com/forum/projects/ads1256-reference-details/

but I decided to do some more basic tests and check how zero zero really is. Since the results were really interesting, I decided to share them.

I shorted all inputs to GND and exercised the input multiplexer and measured every ADC input against every other ADC input using the following test conditions:

• Disregard the additional cap between pin 12 and 13 of the ADS1256 in the picture. It is for another test described below but the picture was taken afterwards.
• 2.5Hz sampling rate
• PGA = 64
• ADC internal buffer on or off
• Inputs shorted to GND "directly" at the ADC inputs (100R input resistors of the board not in the loop). These are the bridges you can see at the positions of R5, R7, R9 and so in the attached image.

The results are 9 by 9 matrices containing the offset between each channel combination, see the attached image. The value on the top of each cell is ADC_count/PGA ("normalized" ADC counts) and the bottom value is the offset voltage assuming a 2.5V reference voltage.

My findings (Inputs_grounded_at_R_footprint_reduced.png) are:

• The matrix is almost skew-symmetric, so exchanging INP and INN mostly changes the sign.
• Each input compared with itself produces good results, usually on the order of one normalized count.
• The offset between AINCOM and any other channel is rather high. This is the reason why the same matrix is shown twice to expand the color scale: Without AINCOM in the left column and with AINCOM in the right.
• The offset between two channels increases when their "distance" increases. Compare, for example, the results between AIN0/AIN1 and AIN0/AIN7.
• The difference between adjacent channels also increases from AIN0 to AIN7.
• Results with the buffer off (bottom matrix row) are not as consistent as with buffer on. Row and column 1 seem to behave a bit differently and this seems to change when I mess around with the board (e.g. solder/desolder wires).
• Results with PGA = 1 seem comparable (results not shown).

While the board layout is not optimal, I don't see any real blunders. I tried adding another 100nF very close to AVDD, because the caps on the board are located a bit off to the side, but could not observe significant changes (and removed the modification).

Now for the fun part: Watch what happens, if a 100nF capacitor is soldered as close as I could manage (AIN6_7_cap.jpg) to the ADS1256 inputs in 100nF_betw_AIN6_AIN7.png: The offset between AIN6 and AIN7 goes down from about 30 counts to 4 or less. The offset pattern between the other channels also changes, and the pattern is quite different without the buffer.

In another test I shorted AIN0 and AINCOM in addition to the short on the R5 footprint. This reduced the approx. 280 count offset seen in the attached results, but only close to zero if AIN0 and AINCOM were shorted hard and close to the package. If the additional short had a length of, say, 2cm, the offset was still about 140 counts.

Conclusion: Even when the input buffer is enabled, the ADS1256 inputs seem to require a really low high-frequency source resistance. Note that the ADS1256 board has 100nF caps from all inputs to GND (according to the schematic, I didn't measure them), so there is already a 50nF differential mode capacitance between all inputs. However, the distance is about 2cm and this seems to be too much!?
If the offset is the same for all differential and common mode input voltages, it could be removed with a system calibration. I don't have measurement gear at home to verify this.

I also found this remark https://www.eevblog.com/forum/metrology/ad4630-24-new-sar-adc-from-analog-devices/msg4279420/#msg4279420 from MasterT:

... I had bad experience in the past with ads1256, when I first time  came to conclusion  that whatever beautiful numbers they put into ADC DS, check if you  can buy OPA that capable to drive this bitch, or if such OPA even exist.

Of course, I cannot completely rule out software bugs (wrote it myself), but the results seem fairly consistent. Measuring the the reference voltage differentially with two channels results in a deviation from the expected 2.5V of about 0.011%, roughly twice the typical gain error of 0.005% in the ADS1256 datasheet (PGA set to 1 in this case, of course). Well, could be less, but may be OK.

Maybe I did something else wrong. In this case, don't hesitate to complain.

[Kleinstein]

The PCB layout uses a ground plane the is not contineous below the ADC. There is a chance that there is some current flow in the ground plane, where the short to GND are connected. This can be DC current, but also AC current, especially from  the reference input and filter capacitor for the reference.
The ground connection to the reference filtering does not look that good, though a bit hard to see in the files I found.

The added capacitor at the inputs 6 and 7 may effect AC current from the input, but also current spikes on ground.

[w42i]

I also suspected some shifts due to ground plane currents and measured the difference between the AINCOM and AIN0 with my Fluke 189 DMM which has 1µV resolution in the mV range. A difference of about 50µV was visible, much less than the ADS1256 reading of about 200µV. So AC currents are quite likely.

These cheap (and easily available) ADS1256 boards seem to be less usable for precision stuff than I had hoped for.

[iMo]

So let you design a new board applying all the lessons learned - a better decoupling, a better routing on 4 layers, a better reference, a better buffer opamp, etc., etc..
A Sunday evening afternoon exercise for talented EEnthusiasts, imho.. 

[tszaboo]

These are temperature measurement front ends, without the built-in current source. Yet, their inputs should be treated the same way as you would measure a TC or a PT100 on a long cable. So series resistance, 1x capacitor to GND from each input, and 10x capacitor between each differential inputs. For example 1K, 10n, 100n would probably be a good start. Reference voltage needs to be driven with a low impedance source (~ 50MHz opamp) or the internal used. There are several application notes on how to measure those from TI.
It doesn't surprise me that an implementation by some rando is not optimal.

[joeqsmith]

....

Of course, I cannot completely rule out software bugs (wrote it myself), but the results seem fairly consistent. Measuring the the reference voltage differentially with two channels results in a deviation from the expected 2.5V of about 0.011%, roughly twice the typical gain error of 0.005% in the ADS1256 datasheet (PGA set to 1 in this case, of course). Well, could be less, but may be OK.

Maybe I did something else wrong. In this case, don't hesitate to complain.

We started using the 55&56 when they first became available.  I found a few problems and as a result, they changed the datasheets.   I thought I still had one of their original eval boards around that we could compare but no luck finding it.

I don't recall too many problems with the analog side of the parts.  I could check my notes if you like.  Be aware, that depending how you intend to use the part, there may be tricks to make it more efficient.   Basically what I remember is they removed sections from the datasheets for some of the other modes rather than trying to explain to customers what the actual problems were.   If you could find a copy of the original data sheet, that would at least show you what was removed.     

[ivo]

CuriousScientist has been iterating designs with this ADC for a year or few, seems it became their 'pet' favourite chip. They have blogs going over the chinese boards and also many assembling their own designs

https://curiousscientist.tech/blog/tag/ads1256

If you were super interested, I think I remember them saying they'd be likely happy to send one of their boards to someone else at cost or similar if they were contacted.

[Kleinstein]

The PCBs from the CuriousScientist still seem to have a solid ground plane. At least it looks more solid and not the extra cuts to make it even worse.
So the layout may be a little better, but could still have issues.