The INL curves measured from the input in AZ mode and AD_in point without Az are in deed rather similar, even more than I have expected. This is because there are 2 INL contribution that I think I under-stand: One is self heating of R200 (center part) in combination with a TC. The other is DA to cause charge transfer between conversions and thus an error mainly in the AZ mode, but should have little influence on longer times with a fixed input.
The odd thing is that these two contributions should be different for the two cases: more self heating (e.g nearly twice as much) in the non AZ mode and the DA effect mainly in AZ mode. The voltage dependence is different ((U-2V)³ vs U² ) so it is not that one is exchanged for the other.
This makes it unlikely that these two contributions are causing most of the common curve.
One possible test could be looking at the S.out test-point again, and compare the curves for a few different input voltages (e.g. 0 V, 4 V, 6 V, 10 V) to see if something changes at around +5 V input. With higher input voltage the curve before the comparator triggers gets increasingly steeper. Its possible for the slope amplifier to just reach positive saturation at about 5 V input. A change in waveform at S.out could effect INL via capacitive coupling towards the current source S1024 (not very likely due to distance) and also through coupling via the supply. Another possibility could be an excursion of the integrator that goes too far at the beginning of run-up.
For the range -1V to +2 V it might be worth to get a few more points for the INL curve(s), to see how wide the dip around 0 really is. Some coupling effects might only effect very small ranges and thus look odd with just a few points.
Having a kind of automated INL test could allow for testing small modifications (like added bias, added decoupling) to see if the INL curve changes. With getting the curve manually this might not be very practical as is would need quite a few curves with preferably more points.
@Mickle T:
U104 needs to be in the right GBW range. The internal compensation of that OP is used for the whole loop too. This OP has to be considerably slower than the LT1220 used for the output and the JFET stage. One might get away with a faster OP when a small capacitor in local feedback (output to inverting input, a little like with the fast amplifier channel). I would more consider an LT1055 or OPA171 for U104, as there is an extra advantage in having a FET type.
My simulation still worked with the LT1056, but it did not include parasitic capacitance, e.g. of the switches. The version with TL071 already showed quite some ringing in real world - so anything faster might get tricky. The noise and drift of U104 should not be that critical as the JFETs in front should have a gain of around 20-40 at low frequencies. So the TL071, LF411, LF351, AD711 and similar could be acceptable. Noise wise the AD8675 is also not that good as the input side of U104 is in the 40 K Ohms range.
For U107 a faster OP should be not problem, but low input bias could be an advantage. The current noise of the AD8675 would already add to the amplifiers noise in the x 10 range. So again a FET based OP is likely a better choice.