Electronics > Metrology
Analog frontends for DMMs approaching 8.5 digits - Discussions
Ole:
I do have a few ideas on cancelling out the Gate Leakage current on JFETs,
the easiest one, in my opinion, would be similar to the bias cancellation circuit in the Datron 1281.
Though that design has the problem of, if I am reading that correctly, the tempco of the leakage.
I have added a concept for cancelling the Gate Leakage current, though this would work best with close thermal coupling between the primary JFET and the Compensator JFET. Though this too would need to be carefully measured and adjusted to work ideally.
On another topic:
Concerning the AZ-Cycling I had the idea to utilise a 8:2 MUX (MAX329 or MUX36D04) with four phases, two of which being Zero Phases. Though this would be aimed at a differential front end.
The MUX36 could be problematic concerning guarding as its a TSSOP Part.
Kleinstein:
Normally the gate current of the JFETs is not a big problem, it is low, at least at room temperature. Like with normal diodes the leakage current is not very dependent on the voltage (except for very low and very high voltages). So the obvious way to compensate if the leakage of another gate to the other side. As this is leakage to source and drain it would compensate for 2 JFETs switched off.
A nice point is that the temperature dependence is expected to be similar.
With just a single JFET one may not have to compensate and it depends on other bias paths if and how many diode connected JFETs make sense for compensation.
David Hess:
Take a look at how external input bias current cancellation works using a second operational amplifier in the same package. This comes up in single supply parts because single supply input stages cannot include input bias current cancellation, but it can be added externally with a second operational amplifier in the same package.
Since the input bias currents match for parts in the same package, the second amplifier is configured as a follower with a high feedback resistance which creates an offset proportional to the input bias current, and then the same resistance between its output and the input to be corrected adds the needed current for correction. For scaling the feedback resistance could be made variable.
Tektronix implemented input bias current cancellation on their 7A22 differential amplifier using a pair of thermisters with one controlling offset and one controlling gain, so I guess there were two effects going on, or maybe that was for linearization.
julian1:
Still exploring cmos switches for a bit,
Briefly for sn74lv4053a one difference with the previous tests - is the zener used to set the boot supply rail.
but tests show that a bootstrap supply rail between 4V to 5.5V doesn't matter much for leakage or charge injection.
Also tried another sn74lv4053a, purchased a few years apart from the one used for initial tests, but with the same result.
So i am not sure how to explain the discrepancy with previous test results.
Running az modulation. all muxes fitted.
DC accumulation on 10nF/ over 10s.
test14.
sn74lv4053a
+10V dc bais
1000nplc/off 20mV. 18mV.
100nplc/2s 17mV. 17mV.
10nplc/200ms 21mV. 22mV.
1nplc/20ms 35mV. 73mV. 70mV. large measured difference. odd. but was definltey there.
But max4053 looks a lot better,
I almost wasn't going to bother re-testing it, based on past resulsts.
Identical setup as above - accumulation on 10nF/ 10s.
max4053
+10V dc bias.
1000nplc/off 0.3mV. 0.5mV
100nplc 0.8mV.
10nplc 3.8mV. 3.6mV.
1nplc 30mV. 28mV.
max4053
-10V dc bias.
leave five minutes for +4.5mV/10s. cap DA to settle.
1000nplc/off 2.5mV 2.8mV - oct 8 2.3mV.
100nplc 3.0mV. 3.3mV - oct 8. 2.3mV
10nplc 5.6mV. 5.7mV - oct 8. 5.2mV.
1nplc 30mV 30mV. - oct 8 29mV.
max4053
0V dc bias.
1000nplc/off 0.8mV.
100nplc 1.0mV. 1mV.
10nplc 3.8mV. 3.6mV.
1nplc 28mV.
leakage is more controlled - <1pA for +10V and 0V, and <3pA for -10V dc-bias.
for charge injection
ie. 1nplc == 20ms. 10s/0.02s == 500 cycles.
this is 30mV / 500 == 0.06pC .
if I have the units correct, through full-cycle switch.
The above tests were done with the azmux held off, with only the pre-charge switch switching.
this would eliminate/isolate any leakage through the amplifer input jfets (if fitted) .
test15.
When the azmux also changed to for normal sampling between PC-OUT (S1) and LO (S6), the result is similar.
max4053
+10V dc bias
1000nplc/off 1.0mV 0.2mV.
100nplc 0.2mV 0.2mV
10nplc 1.0mV 1.2mV
1nplc 20.5mV. 20.5mV
max4053
-10V dc bias
wait for DA.
1000nplc/off 3.8mV. 3.2mV maybe a little DA still from +10V test.
100nplc 2.5mV
10nplc 10mV. 10mV.
1nplc 56mV. 55mV. 56mV
max4053
0V dc bias.
1000nplc/off 1.3mV 1.2mV.
100nplc 1.8mV
10nplc 4.8mV
1nplc 38mV. 37mV.
Edit. add more data
Kleinstein:
The data with the max4053 look good.
At least for 10 PLC mode and likely still with some 5 PLC the charge injection is good. For 1 PLC it may be an issue in a few cases, but would be OK too most of the time.
I am a little surprized that the charge injection / charge pumping depends so much on the bias voltage. The idea with the bootstrapped supply to the switches was to make the charge injection part at least independent of the external voltage. There may be an effect of the waiting time for the charge injection due to some DA or similar settling effect at the MUX / amplifier.
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