Electronics > Metrology

Analog frontends for DMMs approaching 8.5 digits - Discussions

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Scratch the idea using the 10nF accumulation cap as switched capacitor. I had units, uV and mV for leakage drift confused. But perhaps a board level 1uF PP cap might be physically manageable and could be added to the board.

Edit. actually 6.8uF PP is manageable.
for the turnover test, and to transfer the charge from dcv-source to the input, it might be necessary, to switch a few-times, to overcome the capacitance (protection, muxes) of the input section.

For the INL test an external relay could be an option, but it could also help to have control over it, either directly or just a sync signal.

Instead of the simple turn over test, one could consider the more general sum of 2 voltages version. This needs 2 separate DT switches. 2 inputs could substitute 1 switch and 2 low side paths also the 2nd switch. Here especially the case with 1/2 the voltage is interesting as it is a bit easier too look at the result. As an additional advantage over the simple turn over test one also includes a check and compensation for the meters / switch offsets. The 2 extra readings allow a more accurate turn over test for the ADC than just a single relay for a polarity reversal.

The external part would need a low noise short time voltage reference for 2 connected voltages, ideally with several values to choose.
 A simple version could be a chain of batteries (e.g. 8 x 1.5 V) and connectors/switches to choose different points to connect. The external ref. part needs to be isolated and separately powered. So it could well be an external unit. To make the test work well it may need quite a few repeats (at least if the references are noisy) and automation can help with this and avoid thermal EMF from handling the cables.  A fixed speed also allows to compensate for drift better. With a low noise reference manual switching may still be an option for a first test. I don't see a need for very many test voltages and the choice of which voltage to use could still be manual.

Using a capacitor for the turn over test could be tricky and at least require a large capacitor, as parasitic capacitance can pump out some charge and effect the test. One may have to do the test with different capacitor sizes, e.g. 2 capacitors in parallel and options to disconnect on both ends (e.g. with jumpers). It may need quite some care and still the capacitance or manybe thermal EMF at the switches as a possible source of error.

For the slow drifting test voltage the 10 nF may be a bit on the small side. With 10 pA if leakage this would still be 1 mV per second or 3.6 V per hour.  For may tests I liked it usually a bit slower, more like 1 V per hour. Ideally one wants to look at the critical regions with even mode details / lower speed.  It may need a bit extra averaging and not just a single 1 PLC conversion to the the short range INL errors tested with this method. One is hoping for errors < 0.5 µV and this is about the RMS noise for a single 1 PLC conversion. So one should have more like 20-100 averages per point.

Another test that comes naturally is using the ACAL procedure with additional test voltages, like +1 V and -1 V for the 1 V range gain. Ideally the gain for the x10 gain step should be the same from both tests. The difference gives a hint on the liniearity of the ADC and gain stage combined. The extra test voltages make a relatively fast self test and via averaging also alow to average out some of the INL error to get a more accurate ACAL result for the gain steps.

A quick update,

One goal for a new board, is to change the copper features to improve the input switching parasitics, based on the previous experiments.
The design now features traditional ring guards wherever leakage needs to be controlled.
As well as a copper fill at BOOTIN potential, underneath the AZ mux, and surrounding the azmux node and amplifer jfets, to reduce capacitive loading.

Input leakage can be tested by first charging 10n cap for 10sec, then turn off azmux and observe leakage by sampling boot.
leakage looks very controlled.

    > reset ; dcv-source 10; test05
        0.57mV 0.54mV

    > reset ; dcv-source 0; test05
        0.7mV 0.8mV

    > reset ; dcv-source -10; test05
        1.2mV 1.1mV.

Precharge switching,
Change injection is constant at different input bias voltages - as expected due to the switch bootstapping.
This can be improved/trimmed, by lowering the supply voltage on 4053, and trimming VEE relative to BOOT, with a bipolar current source.
But I haven't bothered for the moment.
Accumulated charge injection, nplc 1, on 10nF for 10s, using lv4053,

    > reset ; dcv-source 10; nplc 1; test14
      6mV. 6.4mV

    > reset ; dcv-source 0; nplc 1; test14
      7.2mV  7.2mV

    > reset ; dcv-source -10; nplc 1; test14
      7.8mV 7.6mV

Normal Az switching,
The copper fill at BOOTIN (copying the AZ input voltage), under the azmux works to suppress the capacitive loading of the switch-node output.

    > reset ; dcv-source 10; nplc 1; test15
      5.0mV 4.95mV

    > reset ; dcv-source 0; nplc 1; test15
      7.5mV 8.2mV

    > reset ; dcv-source -10; nplc 1; test15

Board has two distinct input channels, with separate pre-charge switches.
So four-cycle RM and AG (to compensate thermal walk of a high-gain amplifier) functions are possible,

ratio of ref-hi, 10nplc, sampled on two separate channels,
ratio, 3 of 4 meas 0.999,999,9 mean(10) 0.9999999V, stddev(10) 0.06uV,
ratio, 0 of 4 meas 0.999,999,9 mean(10) 0.9999999V, stddev(10) 0.06uV,
ratio, 1 of 4 meas 0.999,999,9 mean(10) 0.9999999V, stddev(10) 0.06uV,
ratio, 2 of 4 meas 1.000,000,1 mean(10) 0.9999999V, stddev(10) 0.07uV,
ratio, 3 of 4 meas 1.000,000,0 mean(10) 0.9999999V, stddev(10) 0.07uV,
ratio, 0 of 4 meas 1.000,000,0 mean(10) 0.9999999V, stddev(10) 0.07uV,

For sum-tests,
I spent quite some time trying to get an arrangement with two series 10u film caps to work.
This included a bunch of over-engineered muxing - for cap selection, and polarity, and to be able to charge to different spot voltages.
But I couldn't avoid a constant leakage of -2uV/s likely to the negative rail (probably due to 0.65" ssop dpdt mux package).
In the past I used relays, but that would be too cumbersome with multiple relays needed

To try the battery approach,
8x 1.2V enneloup batteries in a battery-holder with taps, switched manually
Method - is sample AB for 10 readings, 10nplc, then BC (bottom half) , then AC (series ), take the means, and calculate the diff/delta.
repeat 5 times.
eg. diff = 4.8V + 4.8V - 9.6V

After reducing resolution, change series rundown bias-resistor from 220R to 1k. and new cal.

> data cal show
Matrix: 3 by 1
row 0:     17.4986934
row 1:    -17.9358312
row 2:   -0.458200302
model_id    0
model_cols  3
stderr(V)   0.86uV  (nplc10)
res         0.115uV  digits      7.94 (nplc 10)

diff -3.50uV
diff -5.12uV
diff -4.66uV
diff -4.04uV
diff -1.76uV

diff -5.39uV
diff -4.11uV
diff -3.88uV
diff -0.94uV
diff -3.44uV

diff -5.95uV
diff -2.77uV
diff -3.09uV
diff -4.99uV
diff -2.00uV

diff -4.51uV
diff -6.62uV
diff -5.07uV
diff -4.34uV
diff -1.98uV

diff -8.43uV
diff -7.10uV
diff -3.93uV
diff -7.28uV
diff -2.49uV

6.0 repeat.
diff -8.09uV
diff -4.13uV
diff -3.95uV
diff -3.43uV
diff -4.59uV

diff -1.94uV
diff -2.22uV
diff 0.08uV
diff -2.07uV
diff -4.10uV

diff -3.94uV
diff -1.96uV
diff -2.35uV
diff -2.66uV
diff -2.43uV

I've only just got this working, and am not quite sure how to interpret the offset.
Probably it would be good to try the negative polarity, and I would like to experiment more with a two-variable weighting model for the adc reference currents.

The board includes footprints for 8, and 10pin mdacs, for creating +- spot voltage and these are working,
The idea here was to test inl in a sum-type ratio mode, through a polarity flip.
But I forgot to add a resistor divider, which would need to be bodged.
And I don't like the idea of lower-impedance source, as one cannot buffer the divider since the buffer Vos will not invert through the polarity mdac reference voltage flip.
The mdacs look to be reasonably low noise as far as I can tell - cannot see much above the reference noise.
So the mdacs may be better for drift like INL spot tests, where the adc runup parameters are perturbed.

The input leakage and average current from charge injection looks really good. Also the input inpedance / conductance looks really good: some 2-3 pA of change in the input current when going from -10 V to 10 V would be an input resistance in the 10 Tohm range and this is even with 1 PLC mode. It is cool to have some kind of self test for the input leakage.

For the sum test it would also be good  to include a 4 th measurement (BB) for the offsets. The BB rading would be subtraced from the result.  This way one has the low side at A and B twice each and the high side at B and C twice each and int the resut each point once positive and once negative. This should give a quite good compensation of offsets (e.g. from the protection part).

For the sum of 2 voltages one needs the test voltages to be floating to have the ability to connect the center point to the low side (GND) for 2 of the readings. This makes is tricky to use the same reference nad DAC. One would need some charge pump floating capacitor system (like the 10 µF film caps) or similar system with current source and series of resistors. One than still has the problem that the error can be from the ADC or the charge-pump (or current source output resistance). With the capacitor the issues are leakage, switch charge injection and also parasitic capacitance that can pump out some charge.

The result from the sum test still show quite some scattering. Part of this may be from drift in the battery voltages. At least I see this as a weak point with batteries. The dift can give a systematic error and just simple averaging is not enough. One can compensate at least for the linear drift part, by interpolation to the same time from more readings in a row.
Depending of the voltage reference used (especially a LM399) there can also be an error from popcorn type jumps in the reference voltage. Here just averaging over enough reading could help.

With the scattering and possible error from drift of the battery voltages it is hard to say what the results mean.


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