Electronics > Metrology

Analog frontends for DMMs approaching 8.5 digits - Discussions

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dietert1:
Some days ago i had a look at the TI ADS125 delta-sigma ADC datasheet. In the recommended application schematic fig. 98 they already show four 47 Ohm damping resistors for the SPI lines. Nowadays that many MCUs chips produce sub-nanosecond risetime signals this may be a good thing to do in mixed signal designs. Also depends on the trace lengths.
Imagine EMI suppression as an attenuator made of a low impedance close to the receiver and a high impedance close to the emitter.

Regards, Dieter

julian1:
I should add resistors for the the output of the isolators (it's a tradeoff with routing space). I think Imo made the same point.
They are modern low-voltage parts designed to switch as fast as possibe, since bandwidth is the usual criteria being looked for.

The nice points, are that one can choose either capacitve or magnetic parts.
And because they are fast, the adc counts are transferred quickly during pre-charge phase, or during a reset, when there is no measurement sampling.

I scanned the datasheets, but I am not sure if the internal data-encoding scheme means they are still switching/sending data continuosly across magnetic/isolation barrrier,
even if there are no changes to user-facing input/output state.

So I am a bit curious to find out if they are emi emitters.

CurtisSeizert:
I apologize ahead of time for the long post. I am still getting caught up on this thread, but I have some observations on EMI mitigation strategies from my nanovoltmeter project that may be helpful. Because the power source is a battery, it was necessary to generate the primary rails fed to LDOs with two buck converters and a Cuk. These went in on a daughter board with an Orbel Lazerlok shield over most of the PCB.  The bottom of the daughter board sits about 8 mm above the plane of the top of the main board. The shields on the main board are Laird BMI-S-210 (for the input stage) and BMI-S-230 (for the ADC and associated signal conditioning block). Both of these shields have non-perforated covers, and that was important in this application to be able to use them to mitigate air movement around sensitive nodes. I have also used shields with perforated covers when the sizes don't work out otherwise and put tape over the holes, but that looks a little how ya doin' (as Dave would say). Both of the shields on the mainboards have identical shields on the bottom side because both sides of the main board are populated. Only one side of the SMPS board has components on it (except for the TH connector). The shields on the main board have vias on each land to ensure a low inductance connection to the ground net.

Regarding the shields themselves, the Orbel shields are definitely much higher quality and are cut from thicker sheet. With the Lazerlok shields, there could be issues because they make contact all the way around. You could in theory change the footprint to be able to route signals on the layer with the shield, but that is putting some trust in the solder mask integrity as an insulator. They also cost a lot more than the Laird shields - about 5x as much with both the frame and cover costing $10-15. The covers are also stiffer and take some work to pry off without flexing the board. Between the two Laird shields, the BMI-S-230 is nicer, and the lid is pretty easy to snap off, which is a helpful feature on prototypes.

The performance of the shields on the boards is quite good. I have used a sniffer probe made with five turns of magnet wire amplified 25x with two ADA4896 stages (about 30 MHz bandwidth) to get a qualititative feel for EMI around the board. I could not detect any peaks due to the SMPS in the spectra I took with the cover on the ADC portion (which required some bending to get the probe in). I determined which peaks were due to the SMPS by comparing spectra with the board powered with the SMPS with spectra where the board was powered by a bench supply. The probe was located above U34 in the middle of that shield. There is quite a bit of noise directly under the SMPS board (probe was close to C20 at the upper right corner of the ADC shield). I think this is due to pulsating ground current from the switching of the Buck converters, and some of this current was likely flowing on the bottom layer.

Mains hum is not completely suppressed in measurements, with the size of the peak being dependent on the measurement conditions. With an internal short (from one of the relays in the top left), the peak is about 20 nV/rtHz. For the front panel connector, I switched from Pomona low thermal EMF lugs to LEMO 0S circular connectors with a shielded twisted pair cable, and that helped both for reducing mains hum and low frequency noise, the latter likely from transient thermal EMFs. I had some issues with intermodulation products between the mains hum and the chopper switching frequency aliasing down to low frequency with a simple block averaging filter, but I haven't implemented the feature to synchronize with powerline cycles. I was able to fix this without synchronization by changing to a cascaded integrator comb filter, which only required another six lines of code and a few 64-bit accumulators.

I placed the op amp and current sink for the input differential pair composite amplifier outside the shield because they are the biggest power dissipators, and this doesn't seem to be too problematic. The inputs of the op amp are are fairly high impedance nodes (about 70k each), so they are susceptible to electrical field coupling, but the discrete stage of the composite amp operates at very high gain in this design and the impedance of the inputs is balanced, so it is not too big a deal. I do see some switching residue in the analog outputs of the input stage, mostly from the ~10kHz burst mode operation of one of the LT8608S switchers.

There is some EMI from the MCU, but those peaks are not visible under the shields. All the fast switching lines like the SPI busses and UART have 33R resistors and 50 ohm traces (based on guesses about the output impedance of the driver circuitry). The digital section is all 1V8 to reduce power consumption, reduce EMI, and avoid level shifters with the ADC IO. With the STM32U575 drivers, the edge rates are not particularly fast at this voltage even with the HSLV bit enabled. There is a clear difference in rise time between the AD4030/AUC glue logic outputs and the MCU outputs on a 100 MHz scope, with the former being faster. There a number of signals to mod/demod switches that operate regularly during conversion with 100R resistors and thinner (but not 100 Ohm) traces. I don't see these as big EMI risks because they all switch during dead times in the conversion, which is presumably the case for all the designs in this thread with similar switches for autozeroing.

For the stackup, I used a 6-layer 1.2 mm board with the JLC2116 stackup. This was a compromise between keeping layers close together for low susceptibility to EMI and keeping them far enough apart to minimize parasitic capacitance on some feedback traces. Top and bottom were signal with some ground pours for thermal reasons, and layer 3 (In2) was power. All the others were ground. The 1.2 mm stackup keeps layers 3 and 4 relatively close (about 0.22 mm). I used 1 oz copper on all the inner layers to reduce the impact of any uncompensated ground currents.

Overall, this works pretty well. I do see some issues that seem to be from thermal gradients across the relays, but these are single digit nV effects at their worst and subnanovolt effects when conditions are well controlled. I would probably use a similar strategy for EMI mitigation if I were pursuing an 8.5 digit design with the inclusion of a guard shield between the case and the board (as Kleinstein suggested). I did not have room to include that and still fit everything (including 4x21700 batteries) in a Hammond 100x160 mm extruded Al case for my design, but I have considered the idea of changing cases if I were going to make a revision. I would also be using a lot of antialiasing filtering, something like a six or eight order Bessel filter with fc of about 0.1x the Nyquist limit with an AD4030. I think that a strategy like this (or using an integrating ADC of some description) would help with EMI-related woes because the cross-section of the circuit where it could prove problematic is much smaller. Oh, and one weird effect I noticed was despite powering the circuit with batteries, I needed a CM choke on the input to avoid odd behavior when connected to various sources, including a change in the offset voltage when the inputs are shorted internally. The case for my design is tied to PE through the USB shield during normal operation, so it is possible that an inner guard shield would mitigate such an effect.

I have a couple other general comments about things I saw elsewhere in this discussion. I agree with Kleinstein on the point of multiple parallel or series buried Zener references at this stage in the design cycle. It seems wasteful. For expensive components, I would prioritize good gain setting resistors because those will be crucial for achieving good linearity unless one is implementing some sort of continuous gain calibration faster than the thermal TC of the gain setting resistors or another way of dealing with power coefficient nonlinearity effects. I saw a reference earlier earlier to a substantial noise voltage using the JFE2140 JFET pair at the input. I have used a lot of these, and from what I can tell they have (probably) the lowest 1/f noise corner of any discrete JFET. I have attached a spectrum I took and a schematic showing the measurement conditions. The -3dB bandwidth was 13 mHz to 10 Hz. RMS noise for the DUT (uncorrected) from 0.1-10 Hz was 7.62 nVRMS with a capture of 4M samples at 200 SPS. The noise for each individual FET would be a factor of sqrt(2) less. I have a spectrum somewhere with the -3dB down to 10 mHz, and I think the NSD was about 25 nV/rtHz at the low end there. I spent some time investigating this, and the datasheet measurement setup for capturing noise spectra is pretty bad for low frequencies as the current noise of the OPA210 makes the 1/f corner appear higher than it should. I believe the gain also rolls off before 100 mHz in the datasheet setup. I have taken long captures of three parts for the JFE2140 like this, and there was almost no detectable scatter between parts. The LNA used to take this measurement actually uses 16 of them in parallel and gives a consistent SNR down to below 100 mHz, where input AC coupling filter noise noise (and some other sources) start to come into play. The SNR is near the theoretical 12 dB, so the parts I measured don't appear to be standouts. Another nice thing about this part is the gate leakage current is quite low. I use a Vds of 1.4V for my LNA with 400 uA drain current per FET and get a total of 2.7 pA, so <200 fA per FET.

I realize a lot of this information is anecdotal and qualitative, but I hope it can be helpful nonetheless.

julian1:
Hi Curtis, thank you very much for your detailed comments.

I wanted to ask, if you use COTS or custom RF cans and how you route the land vias, in the nanovolt thread, but didn't want to pollute the discussion with mundane detail.

In your research - did you find any makers of (fence and lid style) RF shields who can manage custom dimensions, in prototype quantities?
I should search on the manufacturers you list - Orbel, Lazerlok, Laird  to see if they offer custom services.

To improvise - I did a Freecad step/dxf model for 0.8mm mild-steel sheet, and had it fabricated to try to prove the concept.
This approach should be OK for the larger LF magnetic (and thermal) guard cover, but is the wrong thickness for a rf-can.
I found a source of pre-tinned (for solderability) mild-steel in 0.2mm and 0.3mm thickness, but need to find a (local) service who can cut and fold the thinner metal.
Being able to pop the lid for access is probably needed as you note.
At this point, there's a trade-off between money spent on custom fabrication, versus extra time routing the pcb to accomodate fixed dimensioned parts.
The simultaneous aspect of mechanical design is a challenge.


--- Quote from: CurtisSeizert on April 23, 2024, 05:43:14 pm ---The performance of the shields on the boards is quite good. I have used a sniffer probe made with five turns of magnet wire amplified 25x with two ADA4896 stages (about 30 MHz bandwidth) to get a qualititative feel for EMI around the board.

--- End quote ---

Using EMI sniffer probes and then doing experiments, switching between a bench supply and DC/DC converter is a really good idea.
Perhaps small electric and/or magnetic probes could be made a permanent (pcb) feature, that remain under the RF cans?
So the probes would route and present to a DUT connection header outside of the shield can.
I purchased a set of near field probes to try to get a bit familiar with doing EMI tests, but there's no way to use them with the cans fitted.


--- Quote from: CurtisSeizert on April 23, 2024, 05:43:14 pm ---For the stackup, I used a 6-layer 1.2 mm board with the JLC2116 stackup.

--- End quote ---

Are there advantages in using JLC2116 versus other stackups, or even a basic manufacturing stack-up?
It seems like a good thing, if everything is well defined from a manufacturing pov.
Perhaps routing the fast digital signals (spi, adc control) with controlled impedance might reduce radiated emi, even if there are no timing/reflection needs.
For the dmm board, there are inner and outer layer grounds to shield (capacitive, magnetic) mostly orthogonal traces.

For the amplifier there are soic-8 footprints for jfe2140, and lsk389.
There is also a footprint for if3602.
I noted your comments about the thermal wander of the if3602 from the DIY cascode jfet lna thread,
So there is a 4-cycle sample acquisition sequence, that can measure and compensate the amp gain, against a small reference-voltage.
But use of if3602 is more in view as an alternative configuration like HP 34420a, rather than a general DMM and is not a priority.
Following Kleinstein's suggestion, I did some Allan variance noise tests with the jfe2140, posted in this thread, but still need to do it for the other parts.

I don't remember the numbers, but in a separate LNA project that I modeled a lot after your initial discrete jfet LNA design, I found lsk389 to be lower noise than jfe2140, but higher leakage (to be expected).
But shielding really needs to be improved first to gain confidence.


For supplies - at least for a first pass - I want to see if the design can be managed without dc/dc converters - and AZ ops for that matter.

I believe Shahriar Shahramian uncovered issues with the DMM7510 - even with the super low-coupling transformer used in that design.
I suspect fast voltage transitions on the rectifiers are a problem.
Adding LC filtering after rectification re-introduces coupling capacitance on the inductors.
So power supply issues are pushed-out as separate scope.
As fallback, I have a simple open-loop fixed-freq. push-pull, and resonant llc with zcs to test on a board, but they are a bit basic.

So for a power supply at the moment - the board can run with a scavenged 34401a mains-transformer (power input headers are designed to match).
Although this transformer is inadequate - with higher than expected coupling-capacitance and lack of a proper screen guard.
I did an experiment stuffing a small sheet of copper, between the two bobbins of Bel signal transformer, as a makeshift guard.
And this already works to reduces coupling (3x reduction from memory) better than the 34401a transformer, so it may something to explore.

If EMI can be measured qualitatively following your approach - with some sniffer probes. then trying out different supplies should be more of an option.

Kleinstein:
For a normal DMM the noise of the JFE2140 should be well good enough.  There is often more noise from the protection part and other resistance. Another noise source are the gain setting resistors.
It is only for a nV meter with ranges below 20 mV that the JFET noise is really an issue.

Using a 3 or 4 conversion AZ cycle to also measure the amplifier / ADC gain for each cycle is possible and it is done with some meters (e.g. Keithly 19x). However the time lost for the extra steps adds to the noise / reduces the reading rate.  Good resistors for amplifier gain would make things easier. The resistance is a compromise between thermal effects and noise from the resistors.

For custom size shielding cans there is also the option to start with a standard size and cut and bend by hand to get a smaller size.

For the DMM the main point for EMI is a signal from the outside effecting the DMM circuit. Emissions may be an issue with the common mode part though. Here the old style 50/60 Hz transformer may not be that bad. With a low power design battery operation is an option too, even if this likely need some SMPS to get the different voltages.

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