Author Topic: Analog frontends for DMMs approaching 8.5 digits - Discussions  (Read 83577 times)

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Offline CurtisSeizert

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Re: Analog frontends for DMMs approaching 8.5 digits - Discussions
« Reply #275 on: April 24, 2024, 04:28:54 pm »
Julian - it is my pleasure. This is a very interesting project that all of you are putting a lot of effort into and doing a great job of documenting.

On routing the vias, I just put them in the pad itself and connect to the ground planes. With 6 layer, as you probably know, JLC fills the vias for free, which opens up via in pad as an option, which is nice. All the shields I used were stock at Digikey. I fully acknowledge that finding a stock part with the right dimensions to fit everything you want is a PITA. Also, I would say pollute away with seemingly mundane details because sometimes mundane just means consequential but easily overlooked.

I did not look into getting custom cut and bent sheet metal for RF shields. I could be wrong, but I would think that the cost of that would be unappealing for small order quantities. How much did your custom part cost? Another manufacturer to check out would be fotofab. I think they custom cut and dimple sheet metal, but their stock shields are already quite expensive (around $70 from Digikey, I believe). If I need a custom shield my plan would generally be to secure it with SMD shield clips (Harwin, I think). I would 3-D print a form with two locating holes for dowel pins, drill corresponding holes in the sheet, cut it as needed, and bend it around the form. By the way, if you do find yourself needing to drill sheet metal, try using brad-point (woodworking) bits. The drill doesn't wander, the point doesn't deform the sheet, and the hole comes out very clean. You might not be able to pull this off with 0.8 mm sheet, however. I was considering it for 0.25 mm stock.

The inclusion of probe features on the pcb itself is an interesting idea. I usually don't have much free room under shielding cans where that would be the most useful, but another way of learning what you need to know would simply to make a test board with the relevant features and sniffer footprints.

The reason I used the JLC2116 1.2 mm stackup was that it offered a good compromise between reasonably low width for 50 ohm controlled impedance traces and low(ish) capacitance to ground for places where that would be bad. One thing to be cognizant of in 6 layer designs is that signals on the top layer and the second inner layer may share a return on the ground plane on the first inner layer because the distance between the middle two layers can be comparatively rather large. I think it is a good idea to try to route fast digital signals as controlled impedance in a noise-sensitive design. I have heard Eric Bogatin say you are likely to get EMI problems long before you get signal integrity problems, by which I assume he means digital signal integrity. I take this to mean you are going to get issues with low level analog signals before you start seeing bit errors. I kept my SPI bus lines quite short, with the MCU pretty close to the ADC, so the time delay may not have been sufficient to justify. Sometimes, however, I think it is prudent when design resources are limited to overdesign by default rather than get away with as much as possible for everything because it takes time to figure out how much "as much as possible" is.

I tend to agree that it is easier to try to avoid DC-DC converters, and I didn't mean to imply that they were the right choice for your design. It was necessary to include them within the specific parameters of my NVM because of the whole battery power thing and the importance of keeping power dissipation nearly constant through a discharge cycle to avoid drift in the magnitude of parasitic thermocouples. The results from EMI probes are nice at the level I use them, but the ultimate question is whether a change impacts the quality and repeatability of measurements. When I was probing around, I was trying to understand whether the higher-than-expected noise density with shorted inputs to the ADC driver was caused by EMI, so I made what changes I could to assign the peaks in noise spectrum under normal operating conditions. The challenges, at least with my equipment and setup, were limited dynamic range and the potential for obscuring peaks in the background noise. Also, any experiments are, to some degree, non-representative of actual operating conditions, because the board cannot be in an enclosure. I was able to rule out the SMPS as a root cause for the specific issue I was investigating, but I did not ever get to a complete understanding of the problem. Actually, one of the most valuable debugging features I put on the NVM board was the analog out SMB jack after the input stage.

I should buy a few LSK389s and see how they come out for noise using the same setup I used for the JFE2140. I was aware they were lower noise, but I am interested to see where the 1/f corner is. I haven't used them before because they are more expensive than the JFE2140 and the matching specs are not as good. I would generally be inclined to parallel JFET pairs before using an IF3602 because the matching, capacitance, and leakage are so bad for the latter. The reason I added those details about the JFE2140 was because of some noise measurements you had posted maybe six months ago. It is sometimes difficult as a casual observer to know which issues have been solved.

By the way, have you posted a full schematic of the board? I don't believe I have seen one, but this thread is 11 pages long, so I might have missed it.

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