Analog frontends for DMMs approaching 8.5 digits - Discussions

[Echo88]

This thread continues the analog front end discussions from the HPM7177-Thread, so it wont get even more offtopic.
Basically this thread should focus on equipping very good ADCs like Kleinsteins Multislope-ADCs, the AD7177 or AD4030-24/4630-24 with suitable analog front ends (high impedance, protected...) that dont degrade the performance that can be achieved with said ADCs.
So far we discussed my approach to build a +-10V high impedance AFE for the AD7177.

To learn how to do it correctly im now studying the 3458A schematics and copied the DCV-path (simplified/omitted control ICs) up to the ADC in Kicad, to make it easier to understand/follow. Maybe its also of interest to other users.
Im thinking wether i should also include the current source/ohms measurement (ACV is another can of worms...) or if that´ll make it too crowded...

Do you think we should first go through the 3458A-DC to then derive a suitable schematic for the AD7177 or maybe also for your Multislope-ADC Kleinstein? I know that youre interested in applying ACAL with your ADC.
Im still having a lot of questions regarding the 3458A-schematic, maybe the more experienced 3458A-scholars know the answers?

Questions:

Is the 1V Signal at Q21 used to do the 1V-range ACAL?
Is the 1:100 HV divider RP7 used for the 0.1V-range ACAL?
Why are the switchable signals at the JFETs divided by Q12 into two signal-"trees":
-maybe one for positive "hot" signals and the other for "gnd"-like signals?
+CurrentShuntOut on one tree, -CurrentShuntOut on the other?
What do Q23/24 measure exactly with their resistors to gnd1?
How exactly are the jumpers JM201-207 on the bottom right page of the "Sentry Current Shunts" page compensating the
TC of the shunts (so ive heard)?
   
Regarding the HPM7177-frontend we discusses beforehand Kleinstein: Does a completely symmetrical AFE (till the ADC level-shifter/driver) like attempted for the HPM7177 have any advantages compared to the approach to just set one voltage input to ground directly?

Schematics for the HPM7177-approach and said 3458A-DCV-schematic are attached.

https://xdevs.com/doc/HP_Agilent_Keysight/3458A/doc/3458A%20CLIP.pdf

[dietert1]

For analog font ends (with their ADS125 24-bit ADC) TI recommend a different kind of multiplexer, with higher channel resistance and much less leakage than the ADG1408. Their recommended MUX36D08 is better than the MAX328 that i used to replace the JFET input MUX of the R6581T. Both of them are specified with leakage around 1 pA at 25 °C, except the TI part has 20x less channel resistance.

Regards, Dieter

[Kleinstein]

The R6581 input is not a good example: it lacks some kind of precharge phase and thus has quite some charge pulses from the auto zero cycle.  The way the JFET gate drive signals are generated is also not ideal.

It makes some sense to inlcude the additional input path(s) for the amps range in the concept. The other point with the current ranges is that they are also linked to the low side / COM terminal and they may effect the protection, if there is more than low side instead of 1 universal COM.

The AD7177 and other ADC chips are usually differential. This can make different front ends more practical. Instead of switching between the input an zero one can do the AZ cycle of a differential ADC by swapping the inputs. Another point can be 4 wire ohms, that could use a real differential input.

The 3458 like many old DMM use JFET switches. In many aspects the modern CMOS switches can make the life a lot easier, especially when it comes to multiplexers with many inputs and if there is no good guard signal from the input to drive the JFET gates.

A big decision to make is whether one wants to use zero drift amplifiers (often as OP-amps) or wants the auto zero switching directly at the input. Both ways are possible an have there pros and cons. The auto zero switching does produce switching spikes even with precharge. These are less frequent than with an AZ OP-amp, but with the variable voltage the spikes tend to be larger and more tricky to suppress.

[David Hess]

What do Q23/24 measure exactly with their resistors to gnd1?

My guess is that they are for measuring leakage current.

[Kleinstein]

Questions:
...
Is the 1:100 HV divider RP7 used for the 0.1V-range ACAL?

Why are the switchable signals at the JFETs divided by Q12 into two signal-"trees":
-maybe one for positive "hot" signals and the other for "gnd"-like signals?
+CurrentShuntOut on one tree, -CurrentShuntOut on the other?

The HV divider gives a 0.1 V signal that can be used for the 0.1 V ACAL step, though with a little extra noise and high impedance that would need some extra waiting time.
An alternative 0.1 V signal could be obtained from the current shunts, but this has also additional noise. The HV divider is likely the better signal.
Ideally one would have an extra 0.1 V signal from a lower impedance divider. For an improved accuracy and as an extra self test it even makes sense to have both positive and negative signals for ACAL.

Yes the separtion in 2 parts is for the Az cycle switching: one for the signal side and one for the more GND like.
The compensation for the switching spike is quite some effort (the extra DAC and OP-amps around this and in parts also the gurad amplifier for the boot signal). With the extra switch Q12 this is only needed once and not for multiple inputs separate.

[tszaboo]

The R6581 input is not a good example: it lacks some kind of precharge phase and thus has quite some charge pulses from the auto zero cycle.  The way the JFET gate drive signals are generated is also not ideal.

While I understand the purist point of view: In my experience the 34410A or the 34401A has quite a bit of charge injection to the measured circuit. You can easily measure it if you connect the DMM into a high impedance node, and measure the same node with an oscilloscope at the same time. I don't remember doing the same when I had access to a 3458A, so I cannot comment on that. My point is, it might be "good enough" because other maters are doing it as well (though they are 6.5 digit).

[Kleinstein]

Switching between inputs causes some charge spikes. It depends on the meters how much effort is used to reduce these:
The R6581T uses no precharge phase and in addition a not so good JFET switch gate drive from the output side, that can add to the charge pulse from the switching.
The 34401 uses a precharge phase, but not extra fine adjustment there. So expect the charge spike to be quite a bit better, though no individual trim.
The HP3456 uses precharge and an adjustement of a capacitive coupled part that is adjusted with a trimmer.
The HP3457 uses precharge and some offset adjustement for the precharge phase with a DAC, likely as a way to trim the charge spike.
The 3458 has precharge and additional capacitive coupled compensation that is adjusted via 2 DACs to reduce the charge peak.  So quite some extra effort to reduce the switching spikes.

The precharge part is relatively straight forward and in many cases one wants a buffer for a guard signal or bootstrapping some clamps anyway. The main part in mind here is the capacitance to ground at the amplifier and switched. Switching some 10 pF at some 25 Hz already is a noticable load (e.g. 10 Gohms range).

The question is a little if one needs an extra reduction of the current spikes beyond the pre-charge part, to compensate some of the charge injection (gate charge) of the switches itself. One tricky point here is that the charge injection usually depends on the voltage. The charge injection parameter found in the datasheets of CMOS switches is usually defined as the extra charge on switching off. With the AZ mode one has both the turn on and turn off phase.
The solution in the 3456 with a trimmer and capacitive coupled part is still relatively simple. These old circuits use JFET switches, things can be a little different with CMOS switches.

[MasterT]

I noticed, that some confusion comes from mixing up two different concept.
1. Old fashion dual/ multi slope, where processing mostly analog in nature, so problems with absorbtion & charge injection  was dificult to resolve.
2. Modern SD ADC, ad7177 etc (I'm experimenting with max11270 & mcp3562) - here we shoudn't care about injection & switching whatsever noise since it's much easier to throw  a sample taken rigth after switching and take another one after long enough settling period, 1 millisec or so. Counting to get 1 kHz sampling rate high just above most OPA +Voltage references   1 / f corners. So requirements to switching IC is close to non - any cd4043 is good.
 

[Kleinstein]

If one has control over the MS-ADC, there is also no problem adding waiting time. The problem is that external capacitance at the DUT can extend the time. So just a little waiting after AZ switching is not an universam solution. It can work for a more internal signal that can tolerate a current spike much better.  Much of the function switching is usually less critcal: one can usually accept additional waiting after a change of function or range.

The SD ADC chips usually already have very low drift to start with and may not need frequent switching. This makes it attractive to use also zero drift amplifiers in the front end, so that there is no or little need for an auto zero mode with switching at the input. Possible extra zero measurements may than be more rare cases and not alternating with the actual input.
The simple Auto zero cycle of alternating between the signal comes with a disadvantge: only half the time is spend on the input and this essentially doubles the noise bandwith.

The CD405x are limited to relatively low voltages (e.g. +-5 V). That may be good enough for the SD ADC diretly, but not really for directly the input with a +-10 or +-12 V range.
Also leakage can be an issue directly at the input. There can be parts that can use the cheap parts, but not all.

[MasterT]

If one has control over the MS-ADC, there is also no problem adding waiting time.

Control over, you mean another switch ?

Lets me put a few words on the primary topic, before my consiousness stretched over billions small details.

 HP was able to developed unprecendented precision level of theirs ADC in the 80's/90's due to the fact, that HP bought on black market  very sofisticated background re-calibration algoritm. Analog Front End in general play big role, but it's limited to 6 digit, microvolts scale level. It was not possible to get 8.5 digit at that time, intill they made a deal with KGB. Not even now.
 Disscussion may continue for another 100-pages, fruitlessly, wiki-pedia style - many words w/o any sense, like Kleinsteine talks (with all due respect).
 
  But precision at nanoVolts level MUST include continuosly running re-calibrarion,  more complex than AZ. It requires wide view on the design, including hardware and software.
PS: Calibration  Logic based on very old mathematics puzzle.

[iMo]

..HP was able to developed unprecendented precision level of theirs ADC in the 80's/90's due to the fact, that HP bought on black market  very sofisticated background re-calibration algoritm. Analog Front End in general play big role, but it's limited to 6 digit, microvolts scale level. It was not possible to get 8.5 digit at that time, intill they made a deal with KGB. Not even now.,

Could you elaborate on that a little bit? HP making deals with KGB on 8.5digits resolution algorithms sounds like a plot from a James Bond movie (I am a big fan of JB movies)..

[Kleinstein]

For the DMM there are 2 steps of "calibration" or automatic corrections that may or may not run in the background.
The more common part the auto zero function to correct for an offset error.
The 2nd point that was usually found in the older meters (e.g. HP3455 and Keithley 19x, Keithley 2001 ) is a correction for drift in the ADC gain and possibly amplifier gain. These meters from time to time or in every conversoin cycle also measure a stable reference voltage (e.g. the 7 V or a rather stable 2 V (e.g. 7 V/4 from PWM or charge pump).
Some of the newer meters like the HP3456, 3458 do no use the perodic check of the ADC gain. The 3458 only does this in the ACAL procedure that is called seprately.
The main point to get away with the extra regular gain calibration is from having very stable resistors, so that the gain does not drift that much.
It still makes sense to include the option to do an internal ADC gain calibration.

For the Multi-slope ADCs there is usually no secret extra linearity correction that is run in between or background. There may be some factory calibrations and maybe special tests to correct for some of the more prominent INL errors. This could be somerthing like seprate gain for the positive and negative side or maybe a small square term. The HP3458 ADC has a somewhat odd looking correction hardware for the zero - not sure how and if it is used at all, as it can be turned off too. My suspicion is that it would do more harm than good.

At least for my MS-ADC I don't need any extra numerical correction to get good INL. The only point is measuring the slow slope to fast slope ratio and auxiliary ADC scale in an extra mode. This does not have to repeated very often (more like 1 time or yearly) and it does not need extra hardware.

If one has control over the MS-ADC, there is also no problem adding waiting time.

Control over, you mean another switch ?

The MS-ADC does not need an extra switch to add a pause. By design there is a switch as part of the ADC to seprate the input from the integrator. If needed one can extend the rundown phase and add some waiting in the µs to ms range.

There is no real magic in the 3458 or other high performance multi-slope ADCs.  Much is a careful design to avoid mistakes that lead to avoidable noise and INL. There are several designs that got to the 8 digit level:  HP3458, Solartron 7081 (though a bit slow), R6581 (with some numerical corrections), Keithley 2002 (though barely 8 digit), Datron 1281 and follow up Fluke meters.
The DC front end of the 3458 is not that much different from the 3456,  mainly better parts and a more sophisticated reduction of the switching spikes.

There are mainly 2 types of front end options:  AZ switching all the way at the input (3458, R6581) with a 1 stage amplifier  or some kind of chopper stabilized amplifier at the front and switching auto zero only after that (K2002, Datron1281) with 2 amplifier/buffer stages. The difficulty with the HP like 1 stage design is keeping the switching spike small. So the charge injection is more than a small detail.
The difficulty with the chopper stabilized way is keeping the bias current and current noise low. The lowest noise AZ OP-amps have a rather high bias. Switching of the chopper amplifier part is more frequent, but with the advantage that it is between 2 voltages that are very close together.

[MasterT]

..HP was able to developed unprecendented precision level of theirs ADC in the 80's/90's due to the fact, that HP bought on black market  very sofisticated background re-calibration algoritm. Analog Front End in general play big role, but it's limited to 6 digit, microvolts scale level. It was not possible to get 8.5 digit at that time, intill they made a deal with KGB. Not even now.,

Could you elaborate on that a little bit? HP making deals with KGB on 8.5digits resolution algorithms sounds like a plot from a James Bond movie (I am a big fan of JB movies)..

I already say too much.
Truth is that ADC, DAC strictly patented and guard by Big corporation located in the West. Royalty is payed out of each single IC produced.
 But enormous number of patents based on stolen or bought dirty cheap inventions come from the East. List is long, I know for sure only about AZ aplifiers, Composite amp, PCM179X DAC's, S/H circuits.
Is recent cheap shortage crissis related to patent war? Who knows.

 Turning back to the topic, disput about AFE w/o knowing Logic reminds me
https://en.wikipedia.org/wiki/Blind_men_and_an_elephant
 
 Just ask yourself, how  comes that backgroung recalibration never published, more over never mentioned.
 
 Schematics are useless w/o knowing what compromises were made at each elements level. Those decisions, vary with  progress in analog /OPA technology, because a lot of stuff that was necessary to implement in the past already integrated inside modern OPA. What is not touched by time is a Logic. Hidden in the dark. Guarded as a rocket science.
 

[julian1]

The question is a little if one needs an extra reduction of the current spikes beyond the pre-charge part, to compensate some of the charge injection (gate charge) of the switches itself. One tricky point here is that the charge injection usually depends on the voltage.

The potential charge injection/current spike at the AZ switch depends on parameters such as - gate voltage, gate/rails headroom, signal input voltage, and is maybe constant for aperture.

Rather than a capacitively coupled dac offset - why couldn't a simple post-facto software correction be used instead? For instance, a 20 point INL like correction delta (dependent on input voltage) for use in AZ mode. And with values determined at the factory with reference to a non AZ calibration.

[David Hess]

Rather than a capacitively coupled dac offset - why couldn't a simple post-facto software correction be used instead? For instance, a 20 point INL like correction delta (dependent on input voltage) for use in AZ mode. And with values determined at the factory with reference to a non AZ calibration.

Software correction does not know how the source impedance responds to the charge pumping.

[julian1]

Hare-brain scheme;

For the AZ switching, alternate between using one channel of a mux, and two channels of a mux.

That yields raw measurements with 1x and 2x switch charge injection riding on top of the input node voltage (The voltage magnitude difference depends on input impedance). Then do software correction/two-point interpolation - to estimate voltage for no charge.

The disadvantage is the extra data being thrown away. Alternatively the data could help derive the offset needed to use for a dac + capacitor compensatory approach.

[Kleinstein]

One can reasonably well compensate for the charge spike from the gate charge, at least for a constant voltage. Essentially all CMOS swtich chips already have some compensation from using N and P channel in parallel and some additional compensation.  It is however not always clear if the chips are more optimized for low charge spike,  low change in on_resistance or maybe a compromise.

One could get around the variable voltage problem by having 2 switching stages in series and have the supply for the first (towards the input) switch bootstrapped to the input voltage. So the first switch gets a supply following the input and is switching between the direct input and a buffered input signal (precharge / gurad signal). The first switch would thus see an essentially constant voltage (relative to its supply) on both sides (except for maybe mV level offset). The switching between the signal and zero and other signals would than follow in a 2nd MUX.
It is some extra effort for the extra bootstrapped supply and level shifting the switch signal - still not that bad compared to the DACs in the HP3458. Other signals may need separate amplifiers for guard signals.  As the extra switch at the input only sees low voltage a moderate supply (e.g. +-2 V) is needed - the exact voltage could be choosen to get minimal charge injection. Chances are a CMOS chip would be easier than 2 JFETs with drivers.

The residual current spike at the input should contain mainly high frequencies, e.g. from residual delays between the switches and compensation (if needed). One should be able to filter out the higher frequency part with acceptable small capacitors / resistors / inductors that may be wanted for EMI reasons anyway.

[David Hess]

The LTC1043 datasheet and application notes discuss the limitations of charge pump compensation and how it is affected by input voltage.  As Kleinstein suggests, a discrete design should be able to provide compensation over a wide input voltage range.

Most circuits do not care about it, but it does come up when the source has its own charge pumping going on and the frequencies are close.  The result can be a  slowly varying offset voltage.  Most often I see it when trying to measure the input resistance of one multimeter with another multimeter, in which case I may break out one of my old multimeters which use a linear input stage with no charge pumping to make the measurement.

This is the same problem that early and some modern chopper stabilized amplifiers have when dealing with AC signals close to their chopping frequency.

[julian1]

Bootstrapping the switch(s), to manage charge-injection over variation of signal input looks clever and elegant. 

A useful first step would probably be to characterize switch charge injection, for modern jfet versus cmos mux, and maybe even discrete n+p fet switch options.

Parts like adum/isolators that might ease doing controllable gate drive wrt the floating signal input.

[Kleinstein]

Discrete MOSFETs tend to be rather low resitance and relatively high gate capacitance. There are hardly any tiny discrete MOSFETs available - excepts maybe RF types, which are usually dual gate ones.
For the JFET way a relatively small (more RF type like mmbfj211) would be a sensible choice, as low capacitance is wanted. For the initial test the large types like J113 / 2N4393 may be easier to measure and the principle should not change much.
For CMOS chips the choice of the chip would be relevant, as much of the gate charge compensation is inside the chip. The trim for minimal current pulse would likely be from the supply (or common mode voltage). A difficulty is that the leakage specs are usually quite loose and not tested. The lower voltage chips tend to be mostly relatively low resistance and not low leakage. For a test I may consider the 74LV4053 with a 3-5 V supply.

The RF or magnetic based isolators tend to need quite some current also on the receive side. The control signal does not have to be very fast of accurate timed. So one can use rather conventional optocouplers or just a current signal via a current mirror. 1 signal to control a SPDT switch would be sufficient.

[David Hess]

Discrete MOSFETs tend to be rather low resitance and relatively high gate capacitance. There are hardly any tiny discrete MOSFETs available - excepts maybe RF types, which are usually dual gate ones.

In theory Calogic and Linear Integrated Systems have 4 lead small signal MOSFETs available which are ideal for this.

http://calogic.net/products/mosfets/
https://www.linearsystems.com/product.html?category=dmoshss
https://www.linearsystems.com/product.html?category=mosfets

Signetics used to sell 4 lead small signal MOSFETs which were just the transistors off of their integrated MOS IC process.  Their performance was amazing and became the SD series.

[opa627bm]

Hi All,
Anyone here can help explain How Q001 Q002 Q003 and Q004 works?
why Source and drain are shorted and not connected to anything ?
Regards,
Li

[MegaVolt]

Hi All,
Anyone here can help explain How Q001 Q002 Q003 and Q004 works?
why Source and drain are shorted and not connected to anything ?
Regards,
Li

With this connection, the transistor operates as a diode with very low leakage in the reverse connection. These diodes are for protection.

[David Hess]

Anyone here can help explain How Q001 Q002 Q003 and Q004 works?
why Source and drain are shorted and not connected to anything ?

With this connection, the transistor operates as a diode with very low leakage in the reverse connection. These diodes are for protection.

To expand on that, low leakage diodes *are* available, however they come with a high price premium because of the required extra testing.  JFETs are routinely tested for gate leakage, so they are usually or always less expensive than a tested low leakage diode.  The 2N4117A/2N4118A/2N4119A low leakage JFET is typically used for this with a tested maximum gate leakage of 1 picoamp at 25C and 20 volts.  The non-A versions have a tested maximum gate leakage of 10 picoamps.

[Kleinstein]

Here is a possible way for the input switching an protection. The 2 parts are in principle independent though they share the OP-amp (U3) for bootstrapping and guarding.
The ESD protection is not yet 100%, so this is more like for careful use in a lab and for low noise, not so much a rugged design. The idea of the protection with MOSFETs and photovoltaic gate driver is borrowed from the Keithley meters like K2000 or K2001.

The switching is relatively fast, so that the current spikes are rather short, though higher peak current. The idea is to get more effective filtering and this way less external charge pulse.
In comparison the HP3458 uses rather slow switching (a slew rate of some 5 V/µs and thus some 1-4 µs for the transients), likely because of the limited speed of the DACs used to trim the charge compensation. Not sure if they use a fixed setting or make it voltage dependent to compensate for the nonlinear gate capacitance.

The fast switching makes digital trim hard and thus the old style variable cap.
The adjustment of the gate charge compensation via C5  could be a bit tricky for 2 reasons:
1) it may not be easy to measure the small transients - ideally not much reaches the input.
2) the capacitance for C5 is quite small and parasitic capacitance adds to it. There are not many trimmers in this range.
In the simulation C5 wants a value of around 0.55 pf for J201 FETs.
The adjustment, the delay from C7 and filtering (values of C4 and C6) effect the transient charge pulses and also the input current pumping. So if way off it can contribute to the input bias current.
Chances are some resistors / capacitors would have to be adjusted on real world hardware, because of parasitice capacitance and similar effects.

The filter capacitors C4 and C6 are towards the guard / bootstrapped signal, because the charge pulse from the gate drive also comes from there. So the OP-amp does not have to drive the fast spikes.
Because of these capacitors noise from U3 could contribute a little to the current noise, though mainly the higher higher frequency part.  So it may be worth using a low noise amplifier for U3.

The CMOS mux at the end is just an example type.  If really needed a 2nd channel (e.g. high side ohms sense) could use a similar precharge scheme.
For a high voltage divider I would consider an extra AZ op-amp as a buffer. This way one avoids the auto zero switching spikes and the switches are less critical.

[julian1]

The schematic helps clarify that the signal/precharge switch works as an independent module. And that it can be switched independently of the signal/zero switch if needed for testing purpose.  Also how a current mirror and common base pnp, can work for the floating switch control.

The cap for the complementary driven charge compensation is tiny. which is very promising. It seems like a real advantage of jfets (versus muxes) if charge-injection can be simulated.

The adjustment of the gate charge compensation via C5  could be a bit tricky for 2 reasons:
1) it may not be easy to measure the small transients - ideally not much reaches the input.

Presumably one could check the effect and perform trim with reference to AZ/no precharge measurements - with some averaging over time - due to extra flicker noise without the AZ switching?

A general question about jfets - do the two actions of turn-on/pinch-off when performed in sequence tend to cancel the gate charge injection?

Possibly the complementary trimmer cap approach could also be applied to a cmos mux, to provide fine trim.  I noted, the ltc1043 datasheet states that the chip is trimmed so internal nmos and pmos charges balance when signal input is at 50% of VDD.

This suggests there might be a general possibility to trim nmos/pmos relative contribution in a cmos mux  -  by trimming/offseting the bootstrap VDD slightly to the signal (eg. probably signal near 50% of VDD or near GND)

[Kleinstein]

Many of the CMOS switches are internally compensated for a small charge spike. The gate capacitance for both JFETs and MOSFETs is somewhat nonlinear and the compensation is thus often only good at a fixed voltage. The more practical way to trim the charge compensation for a CMOS switch in this application would be via the supply relative to the signal. At which voltage the charge injection is near zero depends on the chips - it can be in the center or at one end (often the neg. side).
3 possible candidate chips would be be ADG633 and TMUX1134, maybe max4053. 1/3 of 74LV4053 may work, but the leakage specs are very loose - so testing / selection needed.
I am not sure if a CMOS of JFET solution is better. For the CMOS switches I found it surprisingly difficult to find suitable ones with low leakage, low charge injection at the same time. Especiallly single switches tend to be rather low resistance and thus higher leakage and charge injection.  Availablity is another problem.  With a suitable chip the CMOS solution would be likely easier, with less extra trim needed.

The charges for the turn on and turn off with a JFET should compensate. However the impedance on both sides of the switch determines on how the charge is split to the 2 sides. Another point is that the charge pulse somewhat (the gate resistor helps a little) follows the nonlinear capacitance: on turn off there tends to be more current at the start of the transition and on turn on there is more current near the end. So for the point between the 2 JFETs the overall charge can compensate but there is still first current flowing out from turn off and then later current in the other direction. So even with well adjusted compensation there are transient with charge flowing in and out, even if the sum is zero.

For testing one can use a much more frequent switching (e.g. kHz range instead of some 2-25 Hz for usual AZ cycle), especially for the current. This initially confused me in the simulation, as there I had a much higher frequency and thus more current. For the individual spikes a test point with less filtering may help, though is can also acts back and effect the current.

[dietert1]

Kleinstein, concerning the schematic you posted for input protection: Do you have measurements on thermal EMF offsets generated by the mosfet pair? Probably the mount/geometry makes some difference. Maybe board cut-outs to reduce temperature gradients?
Also i remember another schematic from you with additional bipolar transistors to speed up turn-off (faster than through optocoupler). Is there a reason they disappeared in the current proposal?

Regards, Dieter

[Kleinstein]

The circuit without the extra BJTs is too keep it simpler, but one could add them. Under normal conditions the BJTs I have on my PCB do not engage. They are more like a back-up plan, if the optokoppler is a bit slow. Ideally there is some LC filtering (thus the relative large inductor at the input - this one should allow a high peak voltage) to slow down very fast transients.

With my PCB I have the same circuit 2 times: one paths shows a little thermal EMF effect (some 300 nV AFAIR) and the other shows not detectable extra delayed offset (e.g. < 20 nV AFAIR). Chances are the layout and maybe the way the fets are soldered cause the difference. Currently my FETs are TO252 parts soldered as THT. The 2 paths are a bit different later on (a JFET switch vs a CMOS switch), but I don't think this is the relevant difference.

This is still without extra cut outs. A slight difficulty is the position of the photovoltaic couplers: they should resonable close to the MOSFETs to keep the leakage paths and parasitic capacitance small but as a heat source it should also be a bit away from the MOSFETs to avoid temperature gradients. For highest performance some cut-outs and a little more distance would make sense.
With my PCB I have the resistors for the PV couplers close to the couplers and thus additional heat .

AFAIK the Keithly 2182 nV meter uses a similar circuit for the protection (AFAIK no extra BJTs), but with quite some distance between the FETs and PV coupler.

Another point to consider is that if an input is inactive, it could help to actually pull the input close to ground. An open input can pick up stray signals (e.g. leakage through the MOSFETs). Via non ideal isolation (could be just capacitive) the guard signal could effect the active input. A frist step would be a switch parallel to the zener diodes to at least limit the voltage.

[julian1]

The same approach to jfets may work for Linear Systems dmos sd5400 switches. With slightly high capacitance (2pF versus 0.4pF for j201)  needed to compensate, when switching into a high-z input (like the signal/zero switch + op buffer).

I think the trimmer cap required for such small capacitance values might be tricky.  Mouser has manual trimmers at low values, but they are expensive, and need a (plastic trimmer tool). I found a digital one, PE64904C-Z but it 'only' goes down to 0.6pF. trimmers in series will add extra parasitic capacitance. Simulating using complementary trimmer caps gives odd results.

According to http://www.signalpro.biz/calculators/pcbcapacitance.htm, a 0.5mm trace is around 0.77pF / cm.

It would be good to compare with a cmos mux. It should be possible to boostrap the mux with a trimmable offset relative to the input signal, using an extra op amp/ or discrete bootstrap circuit.

[Kleinstein]

The SD5400 would be a option, though a bit more difficult to get. The higher capacitance is natural with lower on resistance. The 4 pin MOSFETs may allow to use the substrate voltage for the fine trim instead of the capacitance.

If needed one can reduce the voltage of the compensation signal with a resistive divider and than use a larger capacitor (e.g. 1/3 the voltage and 3 times the capacitance). As there is anyway a capacitors to the "ground side", one could also use a capacitve divider. The HP3456 uses a fixed capacitor and a trimmer at the divider.   For fast switching this can still be a bit tricky because of parasitic capacitance at the resistors.

The digital trimmable caps have added ESD protection, that could add leakage. In addition one would need to bring an I2C or similar signal to the floating part.
The size of the gate drive signal could also be used for fine trim, as the gate capacitance is nonlinear. This would also apply the the JFETs.

1 pC of charge injection corresponds to 0.2 pF*5 V control signal. So the specs for the charge injection for good CMOS switches are somewhat comparable to what can be expected from a manual trim. The nice thing is that the gate drive is internal and thus no external inverter and delay. The CMOS chips in question (max4053, adg633, TMUX1133) are mainly available as TSSOP or similar, so quite fine pin pitch. This is not ideal for leakage.

[julian1]

Thank you for your insights, and options for dealing with small capacitance values.
Very good point about leakage for the inputs,
Driven guards should be a feature for unbuffered inputs.
Routing pcb guards for soic and sot23 pins is ok, but there's no chance for tssop.

Package options for cmos muxes
    adg633 and TMUX1133 tssop16,
    max4053             qsop16 (tssop) and soic
    sn74LV4053          tssop and soic

For soic mux, that limits part choices,

max4053
    guaranteed off leakage 0.1nA.  (A version )

sn74LV4053
    datasheet states, off leakage 1uA.  but needs to be tested.

[Kleinstein]

I have the 74LV4053 in the ADC and the leakage there is pretty low (some 10 pA for 3 switches and 2 OP-amps). It is a cheap part, and thus very loose test limits.
This kind of a common picture with most CMOS switches. The limiting specs are pretty loose. Even with JFETs there are only few parts really tested to very low leakage, though the typical specs are OK.
One may have to design with the typical specs here and than select or take chances.

In the actual use case there is very little voltage across the switches and the gate voltage is also more moderate. So the conditions are not as bad as most of the specs (e.g. -15 V gate votlage for JFETs or near full voltage across CMOS switches).

The pinout is so that the pins 3,4,5 ( the 3rd switch) could be used for the switch and pins 2 and 6 could be GND of the chip.  So there is at least guarding to the outside, just not between the switch elements itself. One end of the switch is essentially the guard and than there is one switch enabled.  So no extra guard needed between the 3 pins of the switch.

[julian1]

The pinout is so that the pins 3,4,5 ( the 3rd switch) could be used for the switch and pins 2 and 6 could be GND of the chip.  So there is at least guarding to the outside, just not between the switch elements itself. One end of the switch is essentially the guard and than there is one switch enabled.  So no extra guard needed between the 3 pins of the switch.

That is a fiendishly clever guard strategy, and keeps the choice of tssop open.

[julian1]

For the discrete jfet or dmos option, it may be possible to use a spdt switch to drive the part at the floated signal levels.

[Kleinstein]

Using a CMOS switch chip to control the gates would work, but has 2 down-sides:
1) The charge injection from that chip would couple to the guard signal and this way may add a little to the switching pules. Because of the charge injetion part one may even need some extra protection / clamps, especially for the DMOS chip, that may be a bit sensitive.  With the floating HC14 chip the fast transients are local to the floating part.

2) In the current supply situation the CMOS switches add another part that may have a long lead time or is hard to get.

[julian1]

Thanks. I considered that a non-floating cmos switch would contribute it's own charge injection (varying with input voltage) putting small DC offsets on the gate and compensation drive.  But overlooked they would capacitively couple across to the jfet/dmos.

[julian1]

Here is some data for TI LV4053 v MAX4053A, for a signal conditioning precharge switch.

The switch is driven at a high frequency to try to reveal the bias of the charge injection at different bootstrap rail offsets, and with difference source signal impedances.

And hopefully avoids capturing anything else like the ctrl signal being modulated onto the high-impedance source due to poor PSRR.

There is an issue that the Vos of the op paths is different, and when testing with a DMM we sample continuously - which includes both precharge and unbuffered signal, via the buffer. A real implementation would only sample the signal. But I think it is ok for demonstration, because the op Vos differences get overwhelmed by switch parasitics when switching quickly. 

Code: [Select]


90/10  duty cycle sig/charge
Values are mV.

bootstrap VSS rail          freq
relative to Signal.

                   off     100Hz      1kHz      5kHz

SN74LV4053ATDRQ1 soic

   0V     100k    -0.009    0.013      0.035     0.123
           1M     -0.006    0.036      0.230     0.574
          10M      0.019    0.27       0.23    -6.75

-0.5V     100k    -0.009    0.014      0.050     0.210
           1M     -0.014    0.035      0.375     1.55
          10M     -0.06     0.280      2.17     5.55

  -1V     100k    -0.009    0.014      0.056     0.247
           1M     -0.017    0.042      0.45      2.07
          10M     -0.08     0.33       3.50     14.0

  -2V     100k    -0.011    0.012      0.048     0.212
           1M     -0.19     0.032      0.039     2.23
          10M     -0.102    0.24       4.75     27.4

  -3V     100k    -0.011    0.011      0.031     0.124
           1M     -0.020    0.014      0.230     2.06
          10M     -0.011    0.05       5.66     41.5

  -4V     100k    -0.009    0.008      0.005     0.006
           1M     -0.020   -0.012     -0.012     1.50
          10M     -0.125   -0.215      5.88     52.4


MAX4053AESE soic

   0V     100k    -0.042   -0.029     -0.075    -0.303  (reads a bit high due to op amp temp drift from soldering)
           1M     -0.036   -0.023     -0.071    -0.300
          10M     -0.033   -0.020     -0.068    -0.297

-0.5V     100k    -0.029   -0.069     -0.580    -2.867
           1M     -0.135(?)-0.672     -5.709   -28.43
          10M     -1.049   -6.466    -57.40   -279.0

  -1V     100k    -0.020   -0.099     -0.945    -4.717
           1M     -0.075   -0.981     -9.305   -47.365
          10M     -0.56    -9.267    -84.121  -482.02

  -2V     100k    -0.018   -0.148     -1.473    -7.366
           1M     -0.056   -1.479    -14.451   -72.79
          10M     -0.41   -10.91    -100.17   -716.84

  -3V     100k    -0.016   -0.189     -1.900    -9.512
           1M     -0.043   -1.882    -18.596   -92.042
          10M     -0.300  -10.88    -105.99   -886.7






identical board setup (dual soic/tssop footprint) as previous two tests .

                   off      100Hz       1kHz     5kHz
ADG633  tssop

    0V   100k     -0.005   -0.012     -0.190    -0.987
           1M     -0.005   -0.184     -1.915    -8.746
          10M     -0.005   -1.88     -15.41    -61.5

  -100mV 100k     -0.006   -0.073     -0.778    -3.977
           1M     -0.006   -0.774     -7.681   -38.39
          10M     -0.009   -6.89     -69.24   -354.

  -1V    100k     -0.013   -0.536     -5.3     -26.                                        dec 29. 2022.
          1M      -0.014   -3.090    -30.9    -252.
         10M      -0.020  -14.4     -497.     2417.






[Kleinstein]

An interesting test.  As expected the extra charge injection is best for a low offset in the supply, so close to the negative supply at the switch chip. So one may get away without the extra shift or only have a small shift of a few 100 mV.

The input currents seems to be reasonable low: some 3 pA  with the 4053. The max4053 case may be effected from drift but still looks OK, but somewhat uncertain, as the offset could be different for the 100 K / 1 M /10 M case.

The charge injection caused extra current still looks OK: e.g. some 30-40 pA for the LV4053 at 100 Hz  , so 0.3-0.4 pC of net charge injection. Actual use for DC measurements would be more like 25 Hz (1 PLC). For the max4053 it looks even lower (e.g. 30 pA range at 1 kHz) - but a bit unclear if still drifting.
With relatively little capacitance at the input the charge pulses may cause more of a charge peak that the DMM averages.

So far both switches look acceptable for a DMM input. I would still prefer the max4053 because of better characterization.

There is a chance to get coupling from the control signal. I would not worry so much about PSRR and coupling to the supply, but more about capacitive coupling to the input. With a 5 V jump in the voltage it only takes a fraction of a pF to get pC charge pulses.

Instead of a resistive input, one may check a capacitor (e.g. some 10 nF PP or PS) at the input. The input bias / charge puslses would that slowly charge the capacitor and translate to a drift rate.
This would also smooth out the charge pulses. A full front end would likely have some filtering capacitance (e.g. 20-200 pF range) to ground, also to help with ESD and EMI protection.

[julian1]

Added some data points for tssop adg633, under identical test setup - leakage is perhaps better, but charge-injection worse.

I have another board with a bootstrap variation to trim in both directions (positive to a few 100mV). It may be interesting, now its established that the negative supply is the point of interest (even just for data). More care is needed around board soldering, cleaning, drying before tests.

Agree that some capacitance on the input is needed, the switching is quite spikey, and the bootstrap follows the input, so I could see bandwidth coupled effects.

The suggestion for a cap to accumulate charge instead of input resistors is a great idea, and means that more realistic AZ cycle speeds can be used.

[Kleinstein]

As a last resort one could also shift the voltage used for the precharge. This is done with the HP3457 and 3458 via a DAC.
The charge injection is small and it does not need much shift (e.g. 10-100 mV range depending on the capacitance at the amplifier) to get some 1 pC.
Getting a slight positive shift should be easy.

Capacitance on the input and output side can also effect the charge injection. The actual charge pulse is quite short and the impedance on both sides of the switch can have quite some effect on how the gate charge distributs.  This effect can also be seem with AZ OP-amps:  about equal impedance/capacitance on both inputs can lower the input bias and possibly also the offset.

I first found it strange to have the extra amplifier for the bootstrapped supply (for the switch). Because of the current to the control signal this may indeed make sense.
To reduce at least the fast part of the control current, one could add a RC series element from the raw control signal to the bootstrapped supply. This could compensate much of the fast current part.

[julian1]

The extra op amp was the simplest way I could see to do the circuit. Although I did have in mind the idea of a sum junction for dac control. But it's also possible no adjustment function is required, and just using 0V might be sufficient. Not sure if the boostrap should track tightly (no extra op), or be slowed with RC from the input.


Added a 2k on the output of the switch before the amplifier (R505), to match the input resistor.

Using a 10nF PP cap, to accumulate offset, over a fixed 10sec time period.
Values in mV.
LV4053

Code: [Select]

rail offset     20Hz.       50Hz        100Hz
to signal.

-100mV          -8, -10     -1.8, -7    -2.5, -1.9
-25mV           -4.5        -9          -1, -0.8
0V              2, 1        2.5         2.5
+25             15, 18      13          19
+100            480         500         480

Maybe I am doing something wrong -
But when comparing 50Hz v 100Hz one would expect to see twice the accumulated offset from charge injection with higher switch cycle count.
But that's not apparent from the measurements.
So I think switch leakage (or pcb leakage or something else) dominates at more typical AZ frequencies.

Testing with switch held in fixed state - either Off or On for 10seconds, shows similar bias and magnitude for different bootstrap offsets.

Code: [Select]

                off             on
-100mV          -9, -8          -13, -12
-25             -4.5, -4.7      -7
0               -0.5, -2.5      -0.5, -2
+25             8, 9            18
+100            280             520

The sweet spot seems to be right around 0V.

I can see how to calculate charge injection per cycle - eg. a 30mV range (+19- -9), with 10nF is 300pC of charge.  10 secs * 50Hz == 500 cycles. = 0.6pC / switch.

Is it possible to calculate the inferred current (from leakage or charge injection) from the accumulated charge on the cap?

I still have the 10M/100k paths and can use the voltage drop for leakage current, but a calculaton from the acumulated cap charge may be better.

[Kleinstein]

With 10 nF and a 10 s intervall to look at, 1 mV corresponds to 10 pC. The average current is just the charge divided by the time interva, so 1 pA for 1 mV of drift over the 10 seconds.
The choice of 10 nF and 10s makes it easy to convert to current.

The leakage current from the switch seems to be more important than the net charge injection. There is relatively little difference between the switching frequencies.
The +100 mV case may already see leakage from the substrate diodes.

The net charge injection measured in this experiment is measuring the sum over the turn on and turn off part and for both sides combined.
This is different from the usual charge injection specs in the data sheets. This is only for the turn off part and only the drain side. The charge injetion specs are only a hint on the actual performce in this circuit.

The sweet spot really seems to be close to 0 V. Not just for the switching effect but also for the net leakage.
With the low leakage and switching induced current there may not be a need to have an adjustment of the supply offset.
For just the switch chip the bootstrapped supply can directly follow the input, though it could still be a good idea to keep the short switching spike away from the bootstrapped voltage.

If the bootstrapping is also used for the amplifier than a slow down is usually needed to get stability. The amplifier would normally need both a positive and negative suppply (e.g. +-2.5 V), while the switch is more like +4 V or so. A bootstrapped amplifier would allow for something like the OPA376/OPA377 (or even MCP6286) as a somewhat cheaper and lower bias alternative to the OPA140.
For the switch filtering should not be absolutely needed, but it still makes sense to have some filtering to keep the fast switching spike away from the supply. For just the switch and 0 V offset the buffer for the guard/pre-charge signal could also directly drive the negative side of the switch supply.

[julian1]

Without going too far down a rabbit hole, getting reasonably complete data is useful for part evaluation.
For max4053 and adg633, charge injection is more detectable at lower (typ AZ) frequencies.

Code: [Select]

Accumulated charge on 10nF cap after 10secs in mV.
   
           off      on     25Hz     50Hz     100Hz      1kHz
lv4053.
 
-100mV      -7     -10      -5       -1       -1        +85
-25mV       -3      -7      -2       -2       -2        +55
0V           0       0      -4       +2       +4        +49
+25mV       +9      21      17       20       23        +61
+100mV     270     510

max4053

-100mV      -3      -4      -43      -74    -150      -1500
-25mV       -4      -3      -26      -37     -67       -620
0V          -4      -2      -15      -24     -35       -333
+25mV       -4      -3      -6        +2      -7        -38
+100mV       0       0      +21       41      87        880

adg633

-100mV      -2      -1      -192    -380    -800      -7000
-25mV       -2      -1       -71    -150    -280      -2800
0V          -1       0       -34     -67    -121      -1210
+25mV        0       1       +21     +23     +54       +500
+100mV      29      26       180     330     579       5600


A quick test of the discrete jfet switch approach shows very good leakage.
With J201 and VGS -5V, the offset can be very low. one test got 0.1mV over 30 secs or so..

But the polarity of the switching compensation doesn't match expectation, or ltspcie.
Layout is ok but there is still an unbuffered signal trace near ctrl lines,
So the chance is that parasitic board capacitance is enough to shift the initial bias direction.

Code: [Select]

For discrete jfet circuit with two J201.

varcap not populated
     
           off      on     25Hz     50Hz     100Hz      1kHz
            -1      -1      -18      -33     -55       -520

varcap added (only did 1kHz test)

CCW / barrel screw up                                  -780         
CW / barrel screw down                                 -810         

Adding a 10pF TH (smallest cap I have) bodged on the inverted control signal fixes it. And the polarity is shifted in the desired direction from -90uV to +250uV drop on the 100k at 1kHz.  So the better approach is probably to add small fixed caps to compensate parasitic capacitance in board layout, and then use a varcap for fine trim.

[Kleinstein]

For the JFET circuit the use of the HC02 add a short phase with both fets off. This sounds reasonable, but also effects the charge injection, as the compensation pulses may no longer line up perfectly.
This would be at least different from my simulations. There the gates are used to compensate the delay and get near simulataneous switching assuming a threshold of less than 2.5 V.

With the extra amplifier for the BS supply the capacitors C504 and C514 are going to the supply of the logic chip. So the fast gate charge current would still go through OP-amp3.
At the high speed (some 10 ns range pulses) the amplifiers output is not that low in impedance.
The extra buffer for the BS supply looks like it help reducing the load to OP-amp3, bit I think it makes things a bit worse. With just 1 amplifier the fast part is local to the floating supply.
However parasitic capacitance (e.g. from the logic signals) to ground, can still cause current spikes to the amplifier. So the layout and possible shielding (e.g. with the guard amplfier potential) could have an effect.


Besides the net charge injection and thus the bias current another point is also the size of the charge / voltage pulses visible at the input, especially with relatively little filtering. The smaller the pulse the less filtering / less capacitance may be sufficient. With a good DSO one can likely see the pulse at the input (remove the 10 nF of cause). It may need averaging mode (boxcar integrator mode) to see also small pulses. Getting the pulses small is likely the more tricky part. Ideally small pulses should also cause low net charge injection.

When not using the 10 nF capacitors, but 100 K or 1 M to GND the capacitance at the input may still habe an effect. Chances are it needs a little more filtering there.
For a DMM one usually wants the input offset and bias to be not effected by capacitance (or extra small series impedance) at the input. For this one usually needs some filtering between the switches and the input. The filtering is needed to prevent the switching pulse to get out the input and possibly come back to cause an effect of the charge injection.

The new data with the LV4053 look very good. If the pulse at the input is small enough this would be a good choice (may still need extra testing for low leakage).
It would at least be the simplest solution.

The JFET version is more effort, but possibly less leakage and more options to tweak / trim.

[julian1]

another point is also the size of the charge / voltage pulses visible at the input, especially with relatively little filtering. The smaller the pulse the less filtering / less capacitance may be sufficient. With a good DSO one can likely see the pulse at the input (remove the 10 nF of cause). 

I did look briefly at the input with a scope for the 4053 board.
And then bodged in 100p to gnd, following your suggestion of 20p-200p, in the place of 10M to gnd (R503).

The 100p was removed before starting with the 10n cap tests, since it was 0805 COG and not film, and I was worried about leakage.

In a real implementation, I suppose this cap really needs to be through-hole and PP film

I ordered panasonic 0805 ECH PPS film 100p/50V, but it probably needs testing for leakage. And perhaps higher voltage for ESD/overvoltage events.

--
Edit. Looking at other input filter scheme examples,

3458a    uses RC=5k/82p repeated twice for DCV.
34401a  uses RC=6*1.3k / 470p followed by 2x1.3k/220p.
3457a    uses RC=51k*2/220p for DCV
DVM_input  LC= 1mH/47p * 2

When I get the film cap, I will change the circuit around with better filtering.

[julian1]

Here's a combined schematic with Kleinstein's DVM_input/4053 precharge with DCV ranging, for comment.

Points of interest,

- For 10M impedance and HV divider, Caddock 9.9M/100k 2ppm/C are available (USVD2-B10M-010-02 ).

- Input filtering using two hv through-hole resistors looks neater than a DFM daisy-chain of resistors. Through-hole metal film (RR03J5K1TB)  and PP caps (MKP1839110631) are available at needed voltages.

- For relay choice, agn210 v g6su. agn series are gold plated for better contact at low currents.

- The 1V ref for acal, is only needed temporarily during transfer cal of divider and gain ranges, and doesn't require particularly good (temp,drift) stability. It's not clear if bipolar +-1V is needed for acal.

Pain points,

- 1x/10x,100x gain divider. 34401a, 3458a and Keithley use custom networks.  cern/Reps 8.5 uses custom Vishay v5x5v15x.
      2ppm/C without acal is a good figure to aim for.
      - Caddock 1776-C6815 is 1k/9k/90k can configure as 1k/99k or 10k/90k. but 5ppm/C not 2ppm, and hv is unnecessary.
      - Vishay VTF330SUF  is 1k/9k/90k has datasheet TCR track 2ppm/C. but unknown noise.
      - a total resistance closer to 50k (isntead of 100k) is preferred for 10x gain (and maybe 100x), for lower noise.
      - VSMP foil placed together should be enough.
      - Is there a better solution?

- The DCV filter needs to withstand 1000V when caught on the wrong input range. This is managed with a resistive divider, so that the first filter cap only sees half the excursion voltage. The additional optocoupler switched b2b fets will switch a lot faster than the relay, and help keep voltages and currents manageable quickly. But perhaps a standalone relay switching is enough?

- I am not quite sure about impedance matching the 4053 precharge switch input/output for equal distrubtion of charge injection.  should resistors be placed immediately on each side of the switch? eg. see addition of R518.

- Grounds are hard. i think the main distinction should be between gnds that carry current (resistive-impedance divider/ gain divider), and gnds that have no DC currents (eg. input filtering, mux lo to input amplifier).

- Should the amplifier bootstap be driven with an extra op, for improved CMRR/linearity.

[Andreas]

The additional optocoupler switched b2b fets will switch a lot faster than the relay,

Hello,

I would never put any semiconductors before the RF filter.
(otherwise you may get offsets by rectified RF input signals).

besides this: I do not see how you switch them "ON" without a auxilliary floating voltage referenced to sources of the FETs.

with best regards

Andreas

[Kleinstein]

The FETs driven by an PV optcouplers should be relatively insensitive to RF interference as they are either all the way off or all the way on.
The PV optocouplers provide a floating supply to drive the fets. This is essentially the circuit inside of Photomos relays, just with the parts separated, so that the heat from the LEDs can be a little separate from the signal path and possible thermal EMF effects.

The relay K502 schould not be that critical - it is even optional. The MOSFET stage for the protection can also be used as a switch. K502 would be more to reduce the leakage. Even when off the FETs 503/504 can still have a resistance in the GOhm range.

For the relay K501 one can use 2 contacts in series if needed. This is not so much for the path from the input to the divider, but from the divider to the ACAL signals.

For the first test / proof of pronciple I would consider limiting the voltage a little to get away with simpler / smaller relays. MOSFETs for more than 1000 V also get expensive and sometimes tricky to get.

To keep fast spikes from ESD away from the MOSFET there should be some series inductance (e.g. 100 µH, maybe more) and ideally also some capacitance to ground already before the FETs.
THT resistors for R501 and maybe R502 can make sense - they don't have to be metal film or low noise. The point is only low thermal EMF.  With respect to thermal EMF effects resistos vary a lot and not much data are found, except for good shunt resistors.

Having both a positive and negative signal for ACAL is not much extra effort - the much for the low voltage signals can be a HC4051 or simular. It can help with averaging over 2 points and this way get less effect of the ADCs INL and it gives an extra check in the self test. So I would consider it worth the little extra effort.
Chances are one would need more input paths in MUX. I would consider a 4051 for low voltage signals (+-1 V, +-100 mV, Temperature sensor, optional shunts for current ranges). Another MUX (e.g. DG408 or ADG1208) could be used for less critical signals like the ACAL signal for the divider, buffered signals (e.g. ohm sense L, low current TIA). The sepration to a 2nd / 3 rd mux also has the advantage to allow better isolation from open, unused inputs that would pick up hum.  Depending on how current ranges are implemented there may not be many spare input left.

For the gain setting resistors I would not really consider the Caddock HV arrays. They are quite expensive and may be noisy as they are thick film.
The VTF330 looks good and noise wise should very likely be good or at least good enough.  If really needed to get a lower resistance one could have 2 such arrays in parallel as an option.
The total resistance is a compromose between nonlinearity from self heating and noise. This would mainly effect the 1 V range, though not that much: In the current plan R501 and R502 already give 10 K of resistance that contributes to the noise.

There is one more option for the gain setting resistors: one could use a larger number of equal resistors.  With  10 in series, 1 and 9 in parallel one get a 100:10:1 ratio. 20 equal thin film resistors are not too bad, though the matching is usually not specified, but usually good. The TC specs for the resistors are usually for a quite large range and the performance is the more relevant 20-40 C range is usually quite a lot better. This also applies to the VTF330.

Chances are the 4053 should have about matching capacitors on both the input and output side. One could use somewhat different values to trim / shift the charge injection a little. So there should definitely be footprints, even if one may not be used later. I doubt that R518 would be of any use. If at all a resistor for the C1 input may be useful.

To keep the currents to C503 and the charge injetion at the 4053 local to the floating level, I would prefer to not have an extra OP-amp for the bootstrapped supply. So U501 would directly drive the ground side of the 4053. To reduce the AC current from the control signal on could use a series RC from the 4053 GND to the raw control signal (TP501). R506 should be the same as R509 - probably more 100 K may be 47 K. This way U501 should not see relevant fast current spikes and the charge spikes should stay mainly local.

For the ground the distinction in power ground, signal ground without current and signal ground with current makes sense. Even than one should compensate the ground current if possibly (e.g. for the current from the gain setting resistors).

For the main amplifier the OPA140 may not be good enough with the linearity.  I have not tested the OPA140, but for the slower brother OPA145 I have seen around 1-2 µV of output cross over error when used as a buffer. When used with gain this error would be way to high.  One could reduce this output cross over error in a compound amplifier with a 2nd OP to drive the ouput, though this is a bit tricky with the rather fast OPA140. The other point is the limited CMRR: the specs are only 140 dB typical / 126 dB min and would not guarantee better than 0.1 ppm INL. It may still be Ok as the linear part of the CMRR would not cause an INL error, but just a marginal change in the gain. The problem is that we can't be shure that the OPA140 is linear enough.
When used with a CMOS MUX to switch the gain, the parasitic capacitance to ground can cause stability problems. So one would likely need extra capacitors at the gain setting resistors to compensate.

I have looked at the amplifier circuit used in the 3458.  The advantage there is that bootstrapping the input JFETs is relatively easy (compared to a bootstrapped OP-amp). The extra input stage adds overall DC gain and allows to compensate for more if the linearity errors like the output stage cross over. The part with the inductors at the JFETs is unusual, but it makes sense, at least for a gain of 1 and just boarderline for a gain of 10. It reduces the gain for the highest frequency and this way helps with stabilty (need need for 100 MHz range GBW). However I still don't understand stability with a gain of 100 here the simple analysis show a tendency to oscillation. Maybe the capacitane of the JFETs used for gain switching save the day.

[dobsonr741]

On the mosfet/pv/opto input protection: Kleinstein, what transient behavior are you expecting? Both turn on and off time wise. Is it expected to restrict linearly only to limit the voltage to a max value, or lock and shut down the input completely to zero voltage hitting the ADC? Asking as if an autorange algorithm is working off of the ADC output its better to have full-scale readout when in an underrange position.

[julian1]

Thank you very much for the detailed review and comments. To focus on the amplifier, as perhaps a major weakness.
I understand that bootstrapping jfets is conceptually equivalent to bootstrapping an op, while adding extra gain, and opening up options for suitable larger jfets.
JFE2140 are available. Leakage has the same spec as opa140 Ib - 10pA max.
How does one calculate the voltage gain/ CMRR contribution of the long tail pair stage?
And with parallel inductors across the source resistors, do the jfets become source followers, and gain collapse to 1 at DC? the jfets are in a common source configuration, with high voltage gain regardless.
Edit.

Scratch that. It's possible to simulate gain in ltspice in cascode configuration by removing the op and feedback, and inputting a small differential offset. 100uV. -> 13.15 - 12.98 V. == (13.15 - 12.98)  / 0.0001 == 1699x gain.

[Kleinstein]

The protection part ideally limiting the current in a linear way. So on overload there will be an essentially constant current, just enough to act against the rather small current (e.g. 5-10 µA range) from the PV OK.  At least in my setup it is not oscillating. The turn on speed should not be critical, I expect some 100 µs or so depending on the gate capacitance. The turn of part can be faster with some overshoot iin the current. Essentilly like discharging 2-3 x the gate charge. So far my plan is to detect overflow at the output of the main amplifier with a pair of comparators or similar (fast ADC in the µC in window comparator mode).

Calculating the CMRR for the JFET stage is a bit tricky. I see mainly 3 contributions for common mode gain:
1) The source side current source may not be ideal. A change in the current would translate to a small change in the offset due the mismatch in transconductance of the FETs.
    Chances are the matching in transconductance is good when the overall offset is matched.
2) Due to the Early effect in the BJTs the gain changes with there CE voltage. The difference of this effect between the 2 transistors will set overall effect. I still don't think one would really need the special LM394 matched transistors.
3) with a change in input voltage the power dissipation of the current source and the BJTs for bootstrapping will change. This can have secondary effects. In the sum the power would stay constant - so ideally these transistors could be kind of coupled and a bit seprate from the rest.

The long tail pair gain is relevant as transconductance gain, not so much as DC voltage gain. Here the bootstrapping part has essentially no effect. The transconductance should be  1 / (1/g_fet + R_s).
The GBW of the amplifier with the OP-amp is than set from the transconductance and feedback capacitance.
For details (e.g. the effect of parasitic capacitance and unequal capacitance on both sides a simulation is a good idea).
The inductors in parallel to the source resistors give extra gain for lower frequencies. 1 K and 680 µH gives a cross over frequency of some 230 kHz. This can help in getting faster settling without an overall super high GBW for the amplifier. It sould also help to get a high slew rate. The downside with inductors is that they tend to be non ideal and they may pick up hum - the use of 2 inductors could be to reduce the hum pickup if they are in opposing orientation.


The OP-amp after the JFET stage does not have to be low noise. There is plenty of voltage gain from the JFET stage. So in principle a TL071 should work. For a higher slew rate a TLE2071 may be a candidate. It helps if the OP-amp can work near the positive supply, as the CM voltage for the OP-amp is something like 1-3 V from the upper rail.

For the voltmeter part there is no real need for super low noise of the amplifier. The protection and other resistors aready give quite some noise. It would mainly be current shunts that can use a low noise of the amplifier. So noise wise there is no need to use the JFET2140. Because of good matching ( <5 mV is otherwise the premium grade) and low offset this could still be an option. Compared to other dual JFETs they are still relatively cheap, though there are other cheap ones too (e.g. SK2145).

[David Hess]

Scratch that. It's possible to simulate gain in ltspice in cascode configuration by removing the op and feedback, and inputting a small differential offset. 100uV. -> 13.15 - 12.98 V. == (13.15 - 12.98)  / 0.0001 == 1699x gain.

Simulation will not actually work to determine gain in a precision integrated design.  The open loop gain is limited by thermal feedback into the input differential pair, which is what distinguishes precision design, and why precision operational amplifier are not intended to drive heavy loads.  The highest precision designs even unload the output of the precision operational amplifier with some kind of buffer.

This is also why precision designs where thermal feedback would limit open loop gain sometimes elected to use a discrete precision input pair even though it seems like better integrated parts should have been available.

[julian1]

I think it's enough to get an idea/intuition of open-loop gain within an order of magnitude, based on the transconductance of the jfets and cascode npns (should use 1uV delta though, and compensate for circuit bias).
Output loading is just the jfet inputs of the op-amp.
With that said, I don't think open-loop gain is actually a useful figure, without feedback to tame non-linearity.
More important is CMRR, which if I understand Kleinstein's comment correctly is almost entirely determined by the up-front cascode stage (same for noise), and where temperature dependent non-linearity will come into play.

A suspicion is that some of the design complexity around the 3458a amplifier can be relaxed, if the fast sample/settle capability is not being optimized for - inductors and the variable current sink (more current, faster presumably).
Linearity can be partly checked with turn-over tests, and configuring with gain to also amplify non-linearities, and performing checks with low test voltages.

It is quite tempting to see what would be possible  with just dual/quad sot bjts, and thin-film resistors.
But perhaps a substitute footprint for SSM2212 as a modern matched dual npn would be useful.
I have never tried an ac analysis/bode plots in ltspice.

[julian1]

I have used a weak PV optocoupler to switch b2b dpak nfet gates at 500us/1ms. A bjt optocoupler has current gain and low base capacitance, so I could imagine an order of magnitude quicker response to short the fet gates (turn-off).

A question is whether the optocoupler b2b fet protection scheme could also be adapted to protect the ohms current source.

Positive OVC is handled by a diode. For high negative OVC, the common HP style is a chain of pnp bjts, with voltage drop across resistors used for turn off, but that becomes messy with discrete transistors. The output pmos fet of the current source is the part most exposed.

[Kleinstein]

Some of the Keitley (2001 and 2002) meters use PV Ok and a high voltage MOSFET in the current source.  Chances are one could use a similar circuit (maybe dep. MOSFETs ?) also for just the protection.
I don't see a big problem with the way HP uses the chain of PNPs for the protection.  The main down side is a somewhat larger voltage loss at higher current. With low currents in the low µA mauch of the current can bypass the transistors and less voltage is lost. A relatively high voltage is only really needed for low currents / high DUT resistance. So the voltage loss is not that critical as it may look at first.
With higher test currents like 1 mA and up it helps if the actual current from the source is reduced when the protection engages. Otherwise it take sizable transisors (maybe even TO220 case) to get a sufficient SOA.

Ideally current sources are made different for different ranges. The DMMs usually have quite a large current rance (e.g. some 0.3 µA for large resistors to some 1 mA or 10 mA for low resistors). This makes it somewhat challenging to get that with the same basic circuit, just swiching a few resistors voltages. So ideally one would split the current source to at least 2.
The parts to adapt are the switches and the OP-amp used in the regulation. The HP3458 for example useds an expensive DiFet type, that is good for very small currents, but not really good for the higher currents due to drift and LF noise.
The 34401 use a AD706 as a kind of compromise - not super accurate (especiall with low voltage across the current setting resistor) and also not great with sub µA currents.
Today there is the additinal option to use zero drift amplifiers in this place. They at least keep the drift part low, though they are not ideal for high resistance.

I have shown a reasonable well working current source in another thread. For the current source somewhat better resistors may be a good idea, but the basic circuit looks OK, a bit more optimised for higher currents, but still OK also for low current. For the switching much of the bias and leakage current can be seen as part of the source current. What matters is only the drift of these currents, not the current itself.
The 34401 type circuit is not that bad either. It allows for more voltage, but is a bit more sensitive the switch leakage.

How good the BJT matching needs to be is hard to tell. In the first approximation I get an about linear effect (e.g. CMRR on the order of 120 dB, about linear for 10% of  Beta*Va*Gm matching) from the early effect. So in that approximation only something like an 1 ppm effect on the gain, but not yet nonlinear. Chances are the nonlinear part is not that relevant as only a small fraction of it.
Another point is that the matching would be combined of the BJTs and FETs and resistors at the current mirror. Chances are the FET matching ( transconductance at a fixed current) would be the limiting part and not the BJTs. A similar, maybe worse effect could come from the PNP to provide the base current.

P.s. For the part of an linear effect from the early effect, I goofed up: I only calculated the linear part and thus only got a linear result  .  I think one would get another factor of 2/Va for the 2nd derivative, so something on the order of 0.01 ppm/V.  Still the calculation is crude and the model for the Early effect used ( beta = beta_0 (1+V/va) ) is not that accurately describing the real world.

[julian1]

For the pnps, HP use a dual canned pnp for the legs of the mirror, and a separate (would have poor temp tracking) canned pnp for the middle leg / npn bias.
It is such a useful/good mirror design (good for a discrete LNA also), that tests might be worthwhile.

[Kleinstein]

The 2 PNPs is the current mirror should not be relevant. They operate with an essentially constant voltage and current. The possibly problematic PNP is the 3rd one, that is in the extra can. Thermal coupling shoudl not be the big deal. The early effect of that transistor would give a modulation of the current to the long tailed pair. The current is not very high here, so less effect of a variation in the gain and also usually less early effect for low currents (this part is no included in the normal models/equations but known and visibe in the curves). On the other side there is no more effect of matching.

The effect is like this: with a more positice CM voltage the PNP sees less voltage and this way a reduced gain. The current source/mirror part keeps the emitter current constant and the base current is thus lost. So with the higher CM voltage less current is flowing through the PNP and thus more current for the JFETs. In addition the bootstrapping transistors need slightly more base current and thus an additional effect here too.
For the current source (if a BJT is used) there can be a similar effect: higher CM voltage leads to higher gain and thus higher output current. Here it could help to build the current source with a FET and thus no base current.

The amplifier in the R6581 uses a somewhat similar form of bootstrapping the JFETs drain voltage, but with an extra PNP as emiterfollower and thus slightly less loading of the source side. The effect should be comparable to the PNP at the upper current source, just from the other side and the base current directly. So nothing gained and possibly worse with a relatively high current.

Probably not because of the CM effect (but it could still help) the HP34420 uses a darlington circuit for the bootstrapping part and otherwise a similar configuration to the 3458.

The HP3456 and 3457 use JFETs for bootstrapping. Here at least matching can help. Dual JFETs with a higher threshold ( ~3-4 V) are rare - so one may have to use 2 selected singles here. So no early effect there, but an effect from the drain voltage to cause a small variation in the DS voltage for the main JFETs.

Some test or at least simulations could be worth it. Things get a bit tricky to calculate the old way.
There may be some similar research already done for highly linear audio (though many don't go to such details) or operational amplifiers.
A highly linear amplifier seems to be more tricky than originally thought.

[julian1]

How much is the magnitude of the channel effect in response to BC/CM voltage change, reduced by lowering current generally?
Are there any disadvantages in the darlington approach used by the 34420a - combined with a fet for the sink as you suggest?
I can see that it would not improve the centre leg bias to the npns but that source is already low current.
There are a lot of moving parts, it seems like more data would be useful to make sense of it all. 3458a seems to have done ok, without getting too complicated.

[Kleinstein]

The darlington approach could be a bit on the slow side, as it would ideally operate with rather low currents (even less than the 5.x µA in the 3458) at the input. It may still work OK with integrated darlingtons and thus small input side transistors. One loosed 0.6 V of headroom, which is probably still acceptable. I think somewhat reduced speed may not be that bad and I have an idea to make up some of it, at least for the cases with gain.

How much the early effect changes with lower current - I don't know. AFAIK the usual theory / models don't include this part, but they accnowledge that it gets better with relatively low current for the transistors. The spice models may in clude a slightly better approximation, but the quality may vary.  The known trend is that higher gain BJTs show more early effect. The relevant combination should be beta times Va (or could be Va² for the nonlinear part) and here I don't know. So it is not that clear if a higher or lower gain transistor would be more linear. From audio amplifiers there are sometimes arguments calling for not too high gain. 

The effect from the PNP and NPN pair should add up, both for the linear and square part. The current source part should add up for the linear part, but I think it may compensate for the square part, as here the collector voltage gets large when the CM voltage gets larger. It is still tricky with a NPN and PNP transistor working on quite different currents. Also I am not that sure the simple equation for the early effect is that accurate. So I have the feeling the BJT at the current source is a good idea because of that compensation.

The part that I initially thought of, is from the difference in the early effect in the NPN pair combined with the gm of the JFETs is only one part. A hard to estimate point is how good the BJTs (and JFETs) are matched.
Others are the low current PNP,  NPN at the current source and NPN pair base current. They give an additional change in the current to the differential pair. Changing the current to a differential pair changes the gain of the differential pair, but this would only be a change in the final speed and we don't care about ppm changes in the GBW.  A change to the amplifier DC response comes from the current effeting the offset and this is current change (that can be slightly nonlinear) times the difference in 1/gm for the FETs.  So this path also includes a matching part.

[Kleinstein]

I did a few simulations on the CMRR, to see how much the different transistors can contribut.
The idea with the simulations is to only look the the discrete build stage, loading it with a relatively small resistor. So no OP-amp and feedback.
The output signal is the current through that extra resistor (R1 in the plan)
With the current output one can use the JFET stage without the external feedback and this way easy apply a common mode signal (both JFET gates get the same signal)
This differential drive case gives the differential mode transconductance gain  (in my case some -50 dB).
The ideallized baseline configuration uses a P-MOSFET  instead of the PNP for the BS stage current. This eliminated most of the asymetry, though it may not be practical in real life.
The current source is with a N-mosfet. To include JFET asymmetry the right side gets a 10 ohm source resistor. I would consider this relatively large mismatch ( ~ 10% current and thus ~ 5% in g).
The ideallized baseline circuit gets a very good -202 dB CM gain and thus -152 dB of CMRR (difference to the -50 dB differential gain).
Tests are than done with one at the time PNP at the top, NPN at the current source and mismatch in the cascode pair.
With a 2N3906 for the PNP and 2N3904 for the NPN I get more CM gain for the BJT in the current source than for the PNP on the top ( -187 / -179 dB CM gain).  The size of the CM gain depends on the asymmetry in the JFETs - without the asymmetry (resistors) there is essentially no CM gain.
As already guessed both parts have the same phase for the linear part and opposite sign for the nonlinear part. So there could be some compensation, but not much as the effect of the current source seems to be quite a bit larger.  For the nonlinear part the CM gain at different offsets (+-5 V) is used.

The effect of mismatch of the cascode transistors can be relatively large, and it also happens without mismatch in the JFETs (2x5 ohm resistors) for the 2N3904 / BC547B pairing the CM gain reaches -164 db and thus SMRR of some -114 dB only. The effect is also DC voltage dependent and thus nonlinear.  A pair of same type transistors is likely better than the 2 different models which causes 18 mV in emitter voltage difference.  It still makes sense to get reasonable good matching in the 2 transistors.

In the old simulation file from Julian I found a rather slow response due to a likely faulty (GBW ~100kHz) model for the ADA4625. My LTSPice version is not up to date, so it could be fixed meanwhile.

[julian1]

The 152dB CMRR figure looks rather marvelous!

Using fets for the centre mirror and source, eliminates Early voltage effects modulating to the bias of npns with CM differences - compared with the bjt equivalent. And it eliminates the unbalanced current from the base of the middle pnp.

But I am not clear what the implications are for Early voltages on the other pnp collector currents. Maybe they are less important to the circuit?
 
The sensitivity to asymmetry can be helped with matching. If one can add resistors to unbalance the jfets for a simulation, then one could presumably add them to trim threshold mismatch in real life.

Ltspice incorporates Early Voltage in its BJT model, using the "vaf" parameter. Does the bjt model incorporate non-linear contributions derived from this variable also, eg. VA^2 ?

[Kleinstein]

The 2 PNPs in the current mirror see an essentially constant voltage (some 1.2 V collector to emitter). So the early effect is not an issue there.

The resistor works for simulating a mismatch for the JFETs because the simulation is open loop and not including the OP for the feedback. This way the resistor or a threshold difference causes a different current in the FETs and this than gives the mismatch in g.  For the CMRR it is not the threshold, but the g matching that would matter. In the closed loop case the resistor would only cause an offset for the input as the current mirror forces equal currents and the resistor could not compensate unequal g of the jfets. Source resistors a commonly used to trim the offset.

One could however trim the resistors at the current mirror to get / compensate for some asymmetry in the FETs.  There is however the problem for such an adjustment in the real world: the simulation has not problem with -200 dB of gain, a real world measurement has. It is hard to measure very low levels of CMRR, though it is possible (amplifier in x 1 mode and use a floating meter to measure the input to output difference).
The part for the JFET asymmetry the test is still relatively easy: change the the current (e.g. jumper at the current source, e.g. for a 10% higher current) and check for a change in the offset.

I know that the spice BJT models include the Early effect, but I don't know the exact shape used. The transistors operate with not much variation in current and it thus does not matter how the early effect depends on the current. This is more a thing for selecting the transistors, e.g. choice of BC847 (100mA) versus BCX54 (1 A) with maybe the hope for better performance of the large one. The nonlinear part of the CMRR is not because the curve (gain vs voltage)  for the early effect is nonlinear. Even a perfectly linear curve of the early effect would cause nonlinear parts in the CMRR, e.g. from 1/gain parts. So exact details of the early effect are not that relevant, the linear curve in the simple models is a good enough an approximation.

A P-mosfet for the current mirror base current is nice, especially for the simulation. In real world one would loose about another 2-3 V of headroom or need 2-3 V more of supply. Small low threshold p mosfets are not that common. It would still be an option. At least in the simulation the effect of the PNP transistor was not that large (137 CMRR) and it gets better with better JFET matching. I would expect the JFE2140 to have better than 5% g matching, maybe another factor or 10.
The current source seems to be worse, but here it is easy to use a FET with no obvious disadvantage.  With well matched JFETs a NPN can also be good enough.

[Kleinstein]

I did a quick simulation with JFETs instead of the NPN pair for the cascode. So a bit like in the HP3456.  This also works and does not look that bad. The nice point is that there is no more need for the Zener and extra current to the source side - at least not in the simple form.  A voltage shift could still make sense, as lower threshold JFETs may have better properties (less effect of the drain voltage) and are easier to get as duals.

It is just hard to tell how good the JFETs are matched when it comes to parameters like the output conductance, which is kind of corresponding to the early effect for a BJT.  Maybe worth a real world build of a buffer amplifier or test circuit to get an idea one how good the matching is.

[julian1]

  It is hard to measure very low levels of CMRR, though it is possible (amplifier in x 1 mode and use a floating meter to measure the input to output difference).

I am trying to think of an arrangement that would make it easy to test.
Perhaps having an adjacent battery powered chopper to amplify the input and output of the amplifier configured as buffer would be useful.
At least to a level where the 100mV range of a DMM could read it?
Then one just needs a way to sweep/offset the CM voltage.
Being able to trim the jfets (parallel resistors to the mirror resistors) to a low Vos would allow lots of gain to be added which might help.

 

[David Hess]

  It is hard to measure very low levels of CMRR, though it is possible (amplifier in x 1 mode and use a floating meter to measure the input to output difference).

I am trying to think of an arrangement that would make it easy to test.
Perhaps having an adjacent battery powered chopper to amplify the input and output of the amplifier configured as buffer would be useful.
At least to a level where the 100mV range of a DMM could read it?
Then one just needs a way to sweep/offset the CM voltage.
Being able to trim the jfets (parallel resistors to the mirror resistors) to a low Vos would allow lots of gain to be added which might help.

I have done it using a multimeter with microvolt resolution but Bob Pease discussed measurement of CMRR and Analog Devices published this application note.

[Kleinstein]

For just the offset of the JFETs a source resistor is better suited. The current mirror part would also effect the TC. So ideally one would avoid it. The JFE2140 starts with a low offset and likely no adjustment needed. Just for the JFET asymmetry the simple jump in current would be a good starting point, though this only effect some of CM gain contributions.

I checked the simulation for a NPN darlington pair too, with a little surprise. There is still an effect from the early effect, though the input base current is too small to cause this. It looks like the model used in spice not only has an effect on the base current, but also an effect of the collector voltage on the base - emitter voltage at a constant emitter current. So the change to a darlington pair does not help and more makes things worse, adding the 2 voltage effects. It only helps with the base current part.

The Early effect can be quite different for different transistor types. The general tendency seems to be that it gets smaller (Va larger) for  lower gain, higher voltage rating and higher CE saturation voltage.
A problem is that very few datasheets give the early voltage.  Some simple theories get a constant product of gain and Va for a given process (doping ?).
The SSM2212 has low saturation and rather high gain and may thus show large Early effect, though good matching.
If single transistors are used one may want to have gain matching to get matching in the early effect.

The bob pease article is interesting. One may consider adding parts to do the CM test with an extra FB setting. If the gain is set with an DG409 or similar one would have one more setting free and could use this for the test mode ( bob pease like).

[dietert1]

While looking at a Keithley 2182A nanovoltmeter i modded that 2182A with 5 to 12 Ohm source resistors to improve symmetry and stability against oscillation. The circuit is very similar to the schematic above, except it has four JFETs.
Then i ordered a bunch of JFE2140 to characterize them and make pairs of dual JFETs similar to the Keithley 2182A, with less than 50 uV offset voltage. Selected pairs should be a good method for near zero offset.

Regards, Dieter

[julian1]

Yes, the CMRR test function with FB gain, can be merged with normal amplifier operation function. Just need to jumper/break the supplies.

[Kleinstein]

I had some reading the effectiveness of the JFETs for the cascode part. The idea is that the FETs attenuate the variations in the drain voltage be a factor for g_m/g_os. The data are a bitt scattering but the factor seems to be around 200-500. At first sight this looks OK with the JFE2140 that calls for a rather small effect of variations in the drain voltage (graph with ~0.1 mV for 5-40 V VDS). This would suggest an CMRR of some 110 dB even without cascode. The problem is that much of this is from matching and when using less well matched JFETs for the cascode the matching no longer works that well.

So I kind of understand why HP swiched from the easy  2xJFET cascode to the more complicated BJT+JFET cascode. The BJTs have usually better matching  A few transistors directly give the parameter h12 = dV_BE/dV_CE and thus directly the attenuation factor for the drain/collector voltage. The BC847A gets some 0.00015 and thus 10-20 time bit better than for JFETs. In addion I would expect less scattering than with JFETs.  Besides the effect on the voltage there is also the more obvious early effect on the base current. Here the change in the base current depends on  gain times Early voltage and this combination seems to be much less scattering for transistors made by the same process. So the base current part can to a large part compensate. It still helps to have gain matching to indirectly get Va matching.

There are no direct data on the Early voltage of the SSM2212, but there is some information on h12, as Offset Voltage Change vs. VCB  (10 µV typ and 50 µV max) and this indicates very good matching. The high gain and good gain matching makes the current part also small. So the SSM2212 looks very good. The question is more if a cheaper transistor pair may work too. The JFET alone should have an attenuation of some 200 (tendency is better with low threshold) and the BJT about a factor of 5000. So this would allow 120 dB CMRR even without matching / compensation. With matched gain another 20-40 dB seems plausible. Just any transistor may not be good enough though.

Another effect similar to the Early effect is thermal nature: higher voltage causes more power and thus higher temperature and thus causes more transistor gain. Thus superimposed effect may explain why the data on the Early effect are not that commonly found in datasheets.  As a positive point one could thermally couple the BJT part for the cascode to the NPN or FET of the current source. The sum of the power consumption of the 3 parts stays approximately constant. So tight coupling would reduce the thermal effect quite a bit. Anyway the 3 should be a bit separate from the jfet pair.  The DMM7510 seems to have a SSM2212 outside the case with the JFET pair that is very likely used for the amplifier. Similar the Keithley 2182 has the LM394 outside of the shilding box.  With thermal coupling to the current source I would expect to get away with less distance.
To keep the thermal effects small, I would consider a slightly smaller current than in the 3458. The noise should still be OK / good enough.  A change in the current is anyway easy even later.

[David Hess]

The Early effect can be quite different for different transistor types. The general tendency seems to be that it gets smaller (Va larger) for  lower gain, higher voltage rating and higher CE saturation voltage.

Bob Pease also discussed the correlation between high Early voltage and low hfe.  It is not always desirable to have the highest hfe transistors.

[julian1]

The high gain and good gain matching makes the current part also small. So the SSM2212 looks very good. The question is more if a cheaper transistor pair may work too.

From a practical standpoint, there may be less benefit to cost-optimize the BOM at the margins, when costs are already dominated by hv divider and ref.
But having alternate footprints for baseline comparison tests and a minimal functional setup, with less dependence on part availability is definitely good idea.

There is a reasonable selection of npns for sot-23-6 duals.  HN1C01F (Ic=150mA), cmmx3904, cmx2222a, DSS4160DS (Ic=1A continuous) most of which I have in a parts bin.     
Two sot-23 in separate packages would be worse thermally, but might make picking pairs for gain matching easier.

The placement and cutouts for SSM2212 and LSK389 in the DMM7510 are weird.

[Kleinstein]

The choice of SMD duals is quite large, but only a few offer matching. For singles I would even consider TO92 with bend pins soldered to the SOIC8 footprint.
Some of the matched cheap ones come with odd pin out (FMBM5551 and similar) or tiny case (NST65011). The xxx5551 ones could offer a low Va due to the high voltage rating and relatively high saturation voltage. One extra foot-print could still make sense, as leakage at that point should not be that critical.

For the thermals I think it would be really worth it t couple the dual NPNs to the the current source transistor.

Some distance (well more than between the dual NPN and current source) between the SSM2212 and the JFETs makes absolutely sense, though I don't think it would need that much shield and cuts as in the DMM7511.

The really good matching of the SSM2212 mainly makes sense if the JFETs are also well matched. In many aspects individual matching alone helps relatively little. So the SSM2212 can not really compensate for poor FET matching and to a lesser degree the other way around.  The FET matching would likely be for gm at essentially the same current. Different from the threshold this may not no be that bad for JFETs of the same type. Similar some the BJT matching is about  gain * Va, and this combination also varies relatively little in a series.  Especially for the nonlinear part (the linear part is not that bad) it should be Va to the power or 2 and higher that enters. So good transistors to start with can do quite a bit, possibly even without matching. For the linear part is can be gain * Va that enters - so the choice of gain is less important, but for the nonlinear part less transistor gain and higher Va would be good.

Especially for the start there is no need to include the expensive divider and LTZ1000 (or comparable reference). Still  some $10 for the SSM2212 is not that bad if it avoids selecting parts.

[julian1]

TO92 directly on soic is a good for higher breakdown voltage. BCM847 are matched and inexpensive and follow the typical pinout. I ordered some a while ago but got sot-363 (very small!) by mistake instead of sot23.  But a sot-23-6 version is available,


  BCM847        VBE1−VBE2  VBE matching   2mV max.  (Ic=2mA) (nexperia)  (BS=sot363, DS=sc74/sot-26).  Vceo=45V.
  SSM2212      VOS 10uV typ,  100 μV max,  BVCEO=40V
  FMBM5551    VBE(on)(Die1) - VBE(on)(Die2)   -8mV  to  +8mV (atypical pinout).  Vceo=165V

[julian1]

Thinking about current measurement designs,

For input protection, 34401a and 3457a use a bootstrapped diode bridge to clamp current to ground during overload condition.
3458a is similar, except the top bridge diodes get replaced by switchable BC tied bjts, and there is an additional relay path to disable the shorting path.
I suspect this is to support a higher voltage/burden drop on the sense-resistors than two PN junctions would permit - in order to do ACAL 10:1 transfers between sense resistors.

[edit]
The other feature of the 3458a current section is the use of bootstrapped jfets across the higher value resistors.
So range selection is performed by shorting resistors to the input source side.
The jfet dRDS(on)/dDS is constant when on (shorted) because Vs=Vd=Vg=BOOT is constant.
The approach could also work using a bootstrapped cmos switch (eg. lv4053 + lm339 for control) if desired.

The more common ranging strategy, is to short to gnd the tap points between resistors to select ranges.
Perhaps the disadvantage here is the many open switches with voltage potentials creating opportunity for leakage - when selecting lower-current/higher resistor ranges where leakage matters.

[Kleinstein]

For the BJTs there is no real need for tight VBE matching. So some +-10 mV should be OK and not effect the JFETs very much. The more relevant matching is gain matching and this way indirectly likely Va matching as beta*Va is about constant. The BC847 (at least the lower gain ones) seem to be OK though not great for the Va.
The sot363 is indeed tiny, but if really need one may still fit it to a SoT23-6 footprint

For the current ranges the easy way would be using relays for steering the current. Even good FETs have a hard time to beat the leakage specs, especially for higher currents.
I have a design for the current ranges that should be OK - maybe use a bit more powerful relay at the input and better shunts: the idea is using a classical chain of shunts and sensing from the top for the higher currents (down to some 1 mA FS range). The shunt resistance is still low enough to not add significant noise. The lower currents than uses an TIA amplifier. This way a single resistor / shunt can cover a wider range (fewer ACAL steps needed). So far this misses a bit on the low currents. If needed a 2nd TIA would be possible to than cover really low currents (this part is not really working on my PCB).
In my case the diode bridge does not need to be removed, as a 100 Ohm shunt is not working well with 10 mA anyway due to self heating.
The HP3458 has quite a lot of shunts in series to the sense path that add to the noise. This is not ideal for the higher currents.
The BJTs instead of diodes could be for lower leakage, but the difference is likely not very large.

[iMo]

My AD7177, LTC2500-32, ADS1263 together with the ADR1001 are nervously waiting in my drawer (not in my junkbox, of course) for the final AFE design you are elaborating here! Hopefully you will do it open source at the end! 

[David Hess]

For the BJTs there is no real need for tight VBE matching. So some +-10 mV should be OK and not effect the JFETs very much. The more relevant matching is gain matching and this way indirectly likely Va matching as beta*Va is about constant. The BC847 (at least the lower gain ones) seem to be OK though not great for the Va.

If Va matters why not add cascode transistors to make the collector voltage constant?

Also for what it is worth, I have found that for the same transistor and production run, the emitter-base voltage correlates pretty well with the hfe.

For the current ranges the easy way would be using relays for steering the current. Even good FETs have a hard time to beat the leakage specs, especially for higher currents.

My solution to MOSFET leakage in switching applications was to add another MOSFET in series to disconnect the drain or source and then drive the gate and disconnected drain or source to enforce zero volts across the MOSFET.  They do not leak very much with zero volts across them.  I did this in a high temperature application where a relay had to be replaced by MOSFETs.

[Kleinstein]

If MOSFETs are used for current stearing in for the current ranges, they don't see very much voltage anyway. Usually less than 150 mV spread over the 2 back to back fets.
With modern MOSFETs there is usually some protection for the gate voltage, from a zener diodes to source. This can lead to gate leakage - probably OK for many types, but the specs are usually quite loose. So one may have to check. Similar the low voltage leakage is expected to be good, but usually no sensible specs for this.  It probably works, as other DMMs (e.g. Keithley 2001 , 2002) use MOSFETs for range switching for the current ranges. A relatively large dynamic range for the current (e.g. 1 A at the upper end and some 10 µA full scale at the lower end) makes the switching quite a challange. It is not as bad as it seems at first, much of the leakage from the large MOSFETs for the high current would go the low value shunt.
I would consider the realy way just the simpler way.  Autoranging with current is anyway a bit tricky. One could also combine both ways nd used FETs for some of the smaller/intermediate ranges (e.g. 100 / 10 and 1 mA) only.  Using a TIA for the low currents also saves on the number of switches / relays needed, as a TIA could replace 2 or 3 normal shunt ranges.

The amplifier already use a cascode. Adding a 2nd cascode stage would be possible, but it would also come with downsides. The main one is that one would need another 3-4  V of higher supply and the OP-amp would have to work with that supply (maybe drop some 1 V). In the current, 1 stage cascode the positive supply already is at some 18-20 V to get good linearity up to +10-12 V. Together with some -15 V to get enough output range this is 35 V for the OP-amp. The TLE2071 / LF356 are somewhat limited in the supply. Even without a 2nd cascode stage, just a little more CE / DS voltage for the transistors can improve things.

Part of the problem is also from the base current - here a 2nd stage cascode would not make things better. An extra JFET stage would solve the current part problem, but at the const of reduced matching.
With BJTs to start one would still get the variable base current. Chances are the current part is the weak point.
From my estimates / simulation the combination of SSM2212 and JFE2140 should work OK with no problems - more like overkill from very good matching on both parts.
Here an extra cascode stage may even make things worse, disturbing the good matching.

For more normal BJTs and the JFE2140 things are not that clear, as the advanatge of maching gets reduced for both stages.
Similar SSM2212 and 2 separate not that well matched JFETs could also be tricky as some of the matching advantage is also lost - I don't known how much the parameters vary on non matched parts.
With just standard BJTs (e.g. dual BC547a) and JFETs (e.g. SK2145) it is not that sure one would get to the better than 0.1 ppm INL range for the amplifier.  With high Va transistors (the 5551 type or MJE340 may be candidates, though a bit large for my taste) it may work.

There is still the thermal part, but I think this would be OK, as the main part to worry is loosing the matching between the BJTs and these 2 also get equal power. A somewhat lower current would reduce the thermal effect (could be used for tests). The JFE2140 JFETs are quite low in noise - so even with a lower (e.g. half) current than in the 3458 amplifier one could still get comparable noise.

If one does not need super low noise, there would still be the option to bootstrap a full OP-amp instead of discrete FETs. In this case I would prefer the slower OPA145 (instead of OPA140 as initial amplifier idea)  to make things with stability a little easier. I have such a system with an AD8628 in my DMM version - it works, but the stability part is already a bit tricky and needs  pF range caps at the gain setting dividers. Extra protection may also add a little noise and maybe a few pA bias. I slight problem could be the settling speed.

[julian1]

For the amplifier, the basic function appears to test ok. Some notes,

- The protection schottky is removed. Since there is not enough drop for jfe2140 VGS at working current (0.74V). The ESD protection of the jfe2140 is used, with hi and lo are tied across the zener.

- The 100R across the cascode collectors/ op-amp input, indicated in the ltspice model,  is needed to keep voltages at the op input manageable.
    Otherwise the circuit locks up/latches at startup, and the op-amp output will saturate (probably through the ESD protection of the jfe2140).
    There is a question about loading the cascode collectors/op input with the 100R.
    the voltage difference is small and will equal the Vos of the op amp.
    But there will still be some current.  eg. op Vos=1mV, 100R, => Ir=10uA.  Albeit gain has already been added by this point.
    A future board revsion will add the option for ordinary anti-parallel diodes to the inputs.

- The extra startup current source is not needed for mirror start/ doesn't influence the lockup behavior, with or without the 100R.

- A pnp (3906) also fits the pmos (bss84) footprint for the centre-leg of the mirror.
    this makes it easy to test and compare bjt and fet approaches to the current mirror.

- Tested with lf411 and tl071a for op-amps.

  mirror pfet    bss84 -50V pmos.  60V.  have  smaller modern pfets but they are 30V.
  source nfet    bss138 nmos.   50V.
  cascode        bcm847 npn  . Ic=100mA,   VCEO=45V. (ssm2212 not tried yet.)
  voltage ref    soic-8 footprint. currently lt1021/5V with 10k/10k divider. can remove the divider when obtain a 2.5V ref (lt1019, max6190 etc).

  1.33V on mirror emitters.  1.95V on centre source resistor pfet.
  3.26V across the zener. (it's a 5.1V zener).

  1.31V Vgs on mirror pfet
  1.24V Vgs on source nmos

  Vos of jfets 7.3mV with lf411 (weird - very poor Vos or Ib of lf411 ?).
  4.6mV jfet Vos with tl071a and pnp for mirror.
  4.9mV jfet Vos with tl071a and pfet for mirror.

- it would be nice to have a scope with integrated sig-gen for automated bode plots. With amplifier configured a buffer, and a square wave input, there's an overshoot that is corrected in around 5us.   

For cmrr test, the plan was to use a +-18V bench supply for the amplifier, and power the board and auxillary op-amp, with a spare 34401a transformer + regulation.
lm78xx/79xx were chosen for regulation which are rated to 35VDC input.
But the 34401A transformer outputs 37-38VDC after rectification/filtering (Should have measured it, before committing to a design!).
lm317/lm337 could be bodged, but a new board will fix some other issues also.


The optocoupler/ b2b fet protection scheme looks ok. At least for +-100V over-voltage, using 200V to-247 fets, the fets shut off in around 500us-1ms.
There's a pcb routing error with a hv trace cross, with only pcb prepreg separation, rather than using the full pcb core thickness, which needs to be corrected.

[julian1]

Hmmm, I am now thinking the measured voltage across the zener is wrong, and it should match the rated voltage.

Edit. scratch that. A 5.1V bzx84 zener at 22uA (6.3V/over 220k) drops around 3.7V, so the in circuit value of 3.26V looks about right for 8.7uA. (2V drop on 230k source resistor).

But perhaps a zener with better temp stability should be preferred. ie. 1n750 for ltspice model.

[Kleinstein]

A relatively low votlage for the zener is normal and wanted. A weak point of the cascode amplifier is that one needs quite a bit of voltage headroom. It makes sense to get the voltage over the JFETs down to some 2 V, not to loose too much voltage there. A voltage higher than some 4-5 V may also increase the JFETs 1/f noise. Less heat from the JFETs is also a good thing.
The lower TC zener diodes are for a higher voltage, usually some 5 V for a bare zener and more for the compensated. If used with a much lowe than normal current and than a lower voltage even the low TC zener diode would show a negative TC. A negative TC in the -2 mV/K range (to compensate the casode transistors) would not be bad, but porobably also not critical. After all the JFETs are matched and could suppress a slow change in the drain voltage and this would only effect the offset drift. Some 3.3 V for the zener looks reasonable, slightly on the high side, but perfectly OK for a first test.


I don't see a reason for loading the OP-amp input with a resistor. This would invite a stronger effect of the OP-amp offset. So with a resistor an effect of the OP-amps offset would be no longer surprising.
If at all one could consider an RC series element as an option to trim the frequency response.

A relatively large effect of the OP-amp on the offset is surprising. The OP-amps offset should not have a significant effect on the current balance. This would be only rather indirect via the early effect on the transistors (mainly the current mirror).

The rather large TO247 case for the protection MOSFETs would mainly make sense for the creepage distance, but hardly with 200 V MOSFETs. The more obvious choice are relatively small (e.g. TO251,TO252) case MOSFETs for some 1000 V  (e.g. STU2N105). Small FETs also help to speed up the turn off part and keep leakage low. 500 µs looks like rather slow for the protection to engage.

[julian1]

I made a mistake with the inductors in the initial ltspice model - at least in reference to the way the 3458a amplifier does it.

The inductors don't parallel the source resistors of the jfets and tie at the common zener anode. Instead the inductors are in series (ie. behaves as a single inductor) and it shorts the two jfet sources directly at DC.

I suspect that by always keeping a voltage drop over the jfet source resistors even at DC, there is a better local negative feedback effect (like an emitter degenerator).

Temporarily removing the inductors cures the instability/startup issues I was having. The amplifier now starts and is stable -10to+10V and from DC to 1Mhz at unity gain.

It is curious that the 34420a has an analog switch placed to short the jfet sources in a similar way - although I suspect the reason there is more for cal/offset adjustment/ thermal walk.

For the optocoupler/b2b fets, I was using DPAK, but then noticed the VAC spec of the 3458a, and thought it might be interesting to try for as an experiment. But, I now realize there's not enough amplifier headroom for Vpp, anyway after the hv divider. So reverting back to DPAK is reasonable.

During a hv excursion there is plenty of current through the opto driver leds. It's more a case of being fast enough to stay under the instantaneous/non-continuous led current handling specs of the optocoupler.
So probably a higher output current is needed, rather than gain, for faster fet switch off.
I've changed to use a small bridge rectifier to allow for a uni-directional darlington optocoupler, and also added the option for an extra discrete bjt.

[julian1]

The amplifier is also stable with a 1mH (replacing two series 680uH) placed at the two jfet source pins (before the source resistors) following the approach of the 3458 schem.

[Kleinstein]

There is not much difference whether the 2 inductors are directly connected to the source resistors or not. It is mainly about having the source resistors in series to the current source. So the slight unclear point in the 3458 schematics (is there a dot / connection or not) should not make much difference. My assumption fur using 2 x 680 µF instead of 1.5 mH is that with 2 inductors oriented the opposite way one could reduce the sensitivity to an external magentic field (e.g. mains hum).
For the inductors the details (resistance, Q factor, self resonance) could make a difference - inductors are often not that ideal.

The switch parallel to the source resistors in the 34420 is there to change the input stage gain with the overall gain. With the switch closed the input stage gain (tranconductance) is high and the noise is reduced. However with this the amplifier has too much GBW to be stable at low gain. So with an low gain (1 and likely also 10) the switch is opend. The additional noise is not yet a problem at low gain. Slowing it down all the time (larger capacitor at the OP-amp) would have slowed down the cases with high gain (e.g. 10000) too much.

For the input protection using smaller MOSFETs results in a lower gate capacitance and thus less time needed to turn off. Another point could also be the current used to drive the PV optocoupler. Here one may want to keep the current low and maybe have a series resistor, as the photodiode can store charge similar to the reverse recovery effect of a very slow diode. A photodiode wants a long storage time to get good efficiency. I have not actually tested my protection very much and I am a bit reluctant for a hard stress test, as the input amplifier has so little input bias.

edit:
 I did a quick check on the time needed for the protection to engage: With a rectangular signal of -10V / -20 V the protection needed some 2-3 µs to engage. It is a bit unclear how much the additional transistors contribute. Chances are the transistor part can be even faster and the 2 µs is than the point when the optocoupler part takes over.

[julian1]

The use of series resistance to create a drop across a bjt emitter, to pull the fet gate gates, looks like a superior design.
The advantage being that it can engage before the optocoupler.
A resistor to reduce the PV capacitance seen by the bjts/optos also looks like a sensible addition.
 
https://www.eevblog.com/forum/metrology/diy-high-resolution-multi-slope-converter/msg3827432/#msg3827432
https://www.eevblog.com/forum/metrology/diy-high-resolution-multi-slope-converter/?action=dlattach;attach=1328909

[dietert1]

Better make a separate test setup for the protection circuit - i mean with a load representing the amplifier input (e,g, clipping diodes plus capacitor). You will see that the original circuit with a current limiting resistor and two additional npn transistors works better to quickly discharge the gates. Each npn transistor should get a 1K resistor in front of its base in order to limit base current at some mA.

Regards, Dieter

[Kleinstein]

I totally agree that it would help to have the extra transistors. They may speed up things with rather fast transients and they would add a fall back option in case the opto-coupler would fail.
For the base reistors 1 K would be rather high, as the voltage should be rather low - maybe more like 100 Ohm.
Ideally the inductor on the input side should slow down transients at least a little. 1 mH and 1000 V would still give 1 A/µs.

A separate test setup for the protection is a good idea - not to damage / stress the amplifier and also to have a better way to measure the current on the clamp side .

[julian1]

Thanks for the comments. The way board makers now provide several boards per order makes it easy to selectively populate a dedicated pcb to test bits in isolation. I've done that already, for the very modest basic function test.

I previously made an assumption, that a small latching relay can switch beyond rated max voltages (eg. EE2-3SNU-L  220 VDC, 250 VAC), so long as it switches (open or close) into a high-z node (such as the 10Meg divider, or turned off p2p fets) and there is no carry-current.

And that this is one of the advantages of using the b2b fet scheme - one can use smaller relays, because the b2b fets work as a second switch that can be sequenced with the relay.
 
But I am now wondering if that is correct. A previous schematic revision used hv coto 5503, in parallel with a small gold lead relay for a low thermal/thermocouple offset. But the Coto is big and unwieldy, and it needs a lot of current, something like 100mA from memory even if it only needs to be turned on temporarily, before the smaller relay is engaged. A parallel b2b fet/ssr cannot replace the relay, following this scheme because of leakage.

Is anything known about using latching relays outside their maximum switching voltage - when the relay is just switching into another switch/ or high-z resistor?

[julian1]

Actually Meder  SHV05  andLI05-1A85, hv reed relays are a better form-factor than Coto 5503 for the initial hv contact make or break. That is, iflower-rated latching relays cannot be used directly with restricted condition.

[Kleinstein]

I don't see a probelm with using a relay with a lower voltage rating in series with a electronic switch (e.g. b2b MOSFETs with PV drive or a photomos switch, which is essentially the same in 1 case). The capacitance and high resistance (Gohm range) of the open electronic switch do not allow for the contact voltage to rise very fast. So for the short time to actually open the contact the voltage will be low and later on the open contact to contact rating would be relavant, no longer the switching voltage rating. When closing the relay it is only the relatively limited capacitance (a few 10 pF) to discharge. Even with the path to the 10 M divider, the current is limited by the resistor and I see no chance for a standing discharge with 10 M in series. In addition, at least in my version I have 2 contacts in series for the divider.

Especially for the initial version and tests a high resolution DMM would not be made for a harsh environment with large spikes and aiming for a CAT 3 or even just a CAT 2 600 V rating.
There are compromises between input protection and noise. Additional protection elements (e.g. PTC) may also add thermal EMF. In my relatively crude test a PTC did not show significant thermal EMF, actually better than some resistors.

AFAIK the impit protection of the Keithley 2002 uses a likely fusible relatively large form factor resistor and 2 back to back MOSFETs (no extra BJTs for an extra turn off) and the same clamping to an optocoupler idea. For some reason there are 2 added diodes and what looks like a zener diode. I don't know for what reason, as most modern MOSFETs include a zener diode for the gate and the PV optocoupler can also sink current (~16 forward biased diodes in series) when the voltage goes higher than some 12 V.

[David Hess]

A relatively low votlage for the zener is normal and wanted. A weak point of the cascode amplifier is that one needs quite a bit of voltage headroom. It makes sense to get the voltage over the JFETs down to some 2 V, not to loose too much voltage there. A voltage higher than some 4-5 V may also increase the JFETs 1/f noise. Less heat from the JFETs is also a good thing.

Robert Pease mentioned discovering that high drain voltage also increases gate leakage.  He initially thought it was something new but it was a previously known albeit obscure issue, caused by impact ionization?

The lower TC zener diodes are for a higher voltage, usually some 5 V for a bare zener and more for the compensated. If used with a much lowe than normal current and than a lower voltage even the low TC zener diode would show a negative TC. A negative TC in the -2 mV/K range (to compensate the casode transistors) would not be bad, but porobably also not critical. After all the JFETs are matched and could suppress a slow change in the drain voltage and this would only effect the offset drift. Some 3.3 V for the zener looks reasonable, slightly on the high side, but perfectly OK for a first test.

I am sure I have seen some bootstrapped JFET designs where a constant current through a resistor was used to bias the bootstrap transistor to follow the JFET source.

[Kleinstein]

The dependence of the gate leakage current on the drain voltage is shown in some data-sheets. I would not consider this an obscure property, more a point that is not very often relevent as the current is still small. Impact ionization or hot electron effects (electrons with higher than normal energy, so not in thermal equilibrium with the crystal) are definitely candidates for the extra gate current and also for the 1/f noise.

A simple resistor to set the voltage for the bootstrapped cascode is definitely possible - the typical circuit aready has a relatively constant current. There is still a small change from the early effect at the current source / current mirror.  For highest linearity one tries to keep the voltage constant. A simple zener diode is not much more effort than a resistor, but reduces the variations a little, even if the zener at a few 10 µA is far from perfect.

[Ole]

Hi there,
I was looking up different op amps to use as the primary op amp in the input amplifier here are some of my options:
OPA140(with asymetric supply voltage)
AD4625
MC34081
OP-27
What are your opinions/recommendations for the primary op amp?

Edit: I looked into the ADHV4702-1 and I think its interesting...

[Kleinstein]

The amplifier after the JFET front end is not that critcal anymore, as there is gain from the JFET part. So the noise and offset drift are not that critical.  It helps if the amplifier has a common mode range that extends relatively far up, as the output signal is relatively close to the upper supply (e.g. some 1-2 V from the positive supply).
So the OPA140 and AD4625 are not needed and the somewhat limited common mode range is not good.  The OP27 could be OK (though limited SR), but more overkill and also not good with the common mode range. AFAIK the MC34081 is obsolete.  I would consider an TLE2071 / TLE2081 if a high slew rate and GBW is wanted.

If the amplifier uses an additional stage for the output, to make it an compound amplifier, one could also get away with a slower amplifier, like TL071 / LF353. The output stage would than give the extra speed for the cases with gain. 

[Ole]

Over the last few days Ive looked around and found two candidates
that have significantly lower noise and could fit even into the front end of the 34420A:
The ADA 4099 and
The ADHV4702

In my case the 4099 would be supplied with +24V/-18V and the 4702 would be supplied with +-40V (I happen to have these on hand)

Cheers, Ole

[julian1]

Here's an initial Bode plot for the discrete amplifier without any inductors.

The amplitude is 20dB down, due to a 10x probe used for the DUT output.
I cannot see how to configure it from 1x to 10x in the Bode analysis menu, or even if it's possible.

Using 1x loading (minigrabbers into bnc) the amplifier oscillates, presumably due to capacitive loading of the op-amp output.
There is a 500R at the non-inverting jfet input. I should probably match it with another 500R after the op-amp, to simulate the RDS(on) of the feedback gain switch. Then the DUT/op-amp could be probed after the 500R.

The only compensation is a 100p for the tl071 op-amp. Need to review this again - can possibly be removed, or reduce to 20p.

Edit. Ok figured out how to setup the 10x probe.

[julian1]

Ok, 22p is not enough and the tl071 wants 100p compensation for stability. There are footprints for series RC to the inputs, that could be tried for compensation. But a faster op with more phase-margin might be interesting to try.

Here's two plots, first without an inductor, and second with 1000u in the same fashion as the 3458a. I goofed up the footprint for the inductors, which so the pads extend into the guard (they worked fine with silkscreen). 

 

[Kleinstein]

It is strange to see a litle more gain at the higher frequencies with the inductor.  I would have expected the inductor to reduce the gain at higher frequency. That is if a short is used instead of the inductor. Compared to just the inductor not polulated the added inductor would add gain at low frequencies.

The drop in the gain already at some 50 kHz is anyway strange.
Normally the compensation needs 2 capacitors: one to the postive supply (or ground)  and one in the OP-amps feedback.
Can you post a schematics for the circuit used ?

[julian1]

The amplifier has a 0R at C508 to test with unity gain. Only a single 1000u inductor is used (connected as indicated in schematic without junction).

[Kleinstein]

One would normally need C504 or C524 too for the compensation, not just C525. One can argue to have C504 at the same or twice the value of C525.

[julian1]

Maintaining a ratio between the capacitors for op-amp output to inverting input, and the non-inverting input to gnd, has a logic to it. 
Using 33p/68p it is stable at DC.
Although not stable enough to probe jfet Vos with a multimeter without oscillating. I can increase the cap values, but might wait to see if it's more stable when configured with more gain.

I have swapped scope probes, calibrated them, and reorganized so all measurement is done at the DUT.
Bode plots look about the same, without or without the inductor. I think it's not in the GBW region for the inductor to matter much.
Output tendency at higher freq is to slew like an integrator.

[Kleinstein]

The closed loop performance is not very sensitive to compensation and amplifier details. That is the point of a an amplifier with feedback. At the high frequency end (e.g. > 500 kHz) the inductor is expected to have little effect. The inductor adds additional gain and reduces the noise (reduce the noise of the source resistors) for the low frequency part. Without the inductor the source resistors would be the major noise source for the amplifier.

It would be more in a high gain case that one should see the effect of the inductor. For a test of the amplifer it could make sense to do a test with very high gain (e.g. 1000 or 10000 if the DC offset allows). The higher frequency end is then close to the open loop response and this can help to check / understand the compensation part.

The TL071 is known to be a bit sensitive to capacitive loading. So one may have to use a series resistor at the output for things like a DMM. This could be an issue already with the gain switching CMOS mux. The times 1 case may need a little series resistance before the mux.

[iMo]

Mind your inductor has some self-resonance (due to its parasitic capacitance)..

[julian1]

Mind your inductor has some self-resonance (due to its parasitic capacitance)..

The frequency of inductor self-resonance, will be max impedance, and thus reduced amplifier gain. I think it will be above 500kHz-1MHz where it doesn't matter though.
But it would be interesting to confirm for a specific inductor choice for reference.
One thing I saw when investigating looking at Bode/DSA plots, is the capability/hack for impedance plots by using an injection transformer, in a with a sense-resistor to measure both voltage and current. 
It's something to try, at some point.

[julian1]

With amplifier configured for 1000x non-inverting gain (47.5k/47.5R), and input tied to gnd, output reads -1.420V.
This should correspond to a 1.4mV jfet Vos


After adding a second op-amp U505 (with 1000x gain), on independent supplies (for controllable CM offset and cmrr test), the main amplifier oscillates.

The second op is too slow (with high-gain) to be included as part of the feedback loop.
Adding 100p at C508, as a fast bypass, doesn't seem to help.
I can try a faster op-amp with better GBW (tried opa202, then mc33172 ).
Edit. second op has no local gain, so it may help to increase its compensation (C513).

Alternatively I am not certain the second op-amp actually needs to be part of the feedback loop of the main amplifier for a CMRR test.
Instead, it should be possible to just use the second amplifier to amplify the main-amplifier (configured as buffer) to a useful value to be sampled with a DMM.

[Kleinstein]

The test with high gain would be to see the JFET offset, maybe look at the noise/drift and to get an idea of the open loop response of the amplifier to judge the compensation. So this test should be done with only a single OP-amp.

The idea of using the compound amplifier configuration with a 2nd OP-amp in the loop is to get more speed for the cases with high gain, especially a gain of 100.
This way the gain of 1 no longer needs to be 100 x faster than the gain of 100.
The 2 amplifiers can than share the gain in a way that the 2nd amplifier is still well faster (e.g. 2 x the BW).
With a realistic speed (e.g. 10 MHz GBW) the 2nd OP-amp would not take all the gain, but only a part, like half the gain, maybe a little more.
For a gain of 1 the 2nd amplifier would also have a gain of 1.
For a gain of 10 the 2nd amplifier should also have a gain of about 5. So the BW in x10 mode could still be 50% of the x1 case.
For a gain of 100 the 2nd amplifier should also have a gain of about 10-20. So the BW in x100 mode could be 10-20% of the x1 case.
This should still be fast enough to get resonable fast settling even with the gain of 100.

The 2nd OP-amp is optional (the 3458 does not have it). Especially for the start a somewhat slower response at gain 100 is OK.
I don't think the final use with a high resolution ADC would need a gain of 1000. In that case the 2nd OP amp would however make sense as a BW of only some 2 kHz wpuld be a bit on the low side.

The CMRR test would normally be done with a gain of 1. So no need for the 2nd OP-amp.

[julian1]

Ok, that makes a lot of sense. I wasn't sure why a compound op might be preferred versus just dropping in a faster op.
Equalizing the bandwidth to be more independent of gain is definitely a nice property - even without adding extra gain ranges.
But it re-raises the question of resistor part choices.
And gnd current compensation with two resistor dividers is more complicated - ie. 34420a.
Rather than one divider there are two, so we have to sum their currents (by summing output voltages) I think.

[Kleinstein]

The GND current compensation is not that bad: the first OP-amp has essentially no current to ground. Both gain divider chains are driven from the output side, so just the higher current. Even if there are multiple independent dividers to ground it is easy to add the contributions at the inverter for the compensation. It is just another resistor.

The 2 step FB divider in the 34420 is for different purposes. The main point is likely the internal calibration check / calibration of the highest gain. There are different ways to get the medium high gain settings and this allow a calibration of the 1 mV range from 100 mV ref source. So no need for a special calibration sources.
The other point could be getting a little less noise from the FB divider. The 2 stages allow for a little lower resistance and thus noise in the FB path. I still don't hink that is the main part here. It can be an issue for even lower noise.
In my oppinion a compound amplifier would have made some sense for the 34420, because of the quite large gain. The high gain is slow, but the noise anyway makes very fast measurements less attractive. The source resistor switching provides some adaption in the GBW, but no extra DC gain.

The frequency compensation at the FB dividers itself gets a bit tricky though. It gets tricky if the 2nd stage has a not so flat frequency response. So there should be suitable capacitors to compensate for the capacitance of the switches. It does not need to be as good as for a scope or AC measurement, but still reasonable (e.g. +-30%) accurate. So the choice of the mux chip for the gain could effect the small capacitors.

For the parts choice the 2nd OP-amp should be resonable fast, but it does not need to have the input CM range all the way to the positive side. In my DMM front end I have an TLE2071 (had it at hand). I would also consider a OPA1677 or OPA197 or about any reasonable low power, 32 V capable OP-amp with some 8-20 MHz GBW. A reasonable good slew rate can also help.
The more tricky choice is the 1st OP-amp, as one wants it to work well (many rail to rail OP-amps fail just in the relevent range or 0.5-3 V from the rail) near the positive supply. So the reasonable choices are TL071, TL071H, TLE2071 and similar. I don't consider the GBW that critical, it is more about having no too much complications in the phase response up to some 3 MHz.
I consider the current speed fast enough - the point of not going much slower is avoiding a larger inductance.

[julian1]

I think it makes sense to properly characterise and test the one op-amp amplifier in priority.
With that said, the extra op-amp (meant for cmrr) is provocatively almost  in a compound configuration (DP adg1209 could work in SP adg1208 footprint).

The frequency compensation at the FB dividers itself gets a bit tricky though. It gets tricky if the 2nd stage has a not so flat frequency response. So there should be suitable capacitors to compensate for the capacitance of the switches. It does not need to be as good as for a scope or AC measurement, but still reasonable (e.g. +-30%) accurate. So the choice of the mux chip for the gain could effect the small capacitors.

For reference, how are you choosing or calculating values for switch compensation values?
   
I see the following,
      10p across 60k         
      22p across 100k.   
      39p across 4.7k   

Perhaps independent resistor dividers for each ratio instead of a ladder, would make it easier.
That way each divider could get a dedicated value capacitor.

[Kleinstein]

I totally agree to first sort out the 1 OP-amp version. The 2 OP amp version is mainly to speed up the x 100 case somewhat and make the front end part work more like the x 10 case. So it still needs the 1 OP-amp version to work properly. The compensation at the FB divider should be about the same even with the 2nd OP amp added for more speed. The 2nd OP amp is more like making the compensation of the JFET + inductor part a little easier as that parts no longer sees such a large variation in the effective gain.

Even if just using the 1 OP amp version it would help to use the ADG1209 and not the ADG1208 - just because of a lower capacitance. I already see little need for a 4th gain setting.

Choosing the compensation is tricky. The values shown in my plan are the current state that I got. Part of the capacitors are bodged on, a bit in a try and error way. I currently have a few more small capacitors on there to improve a bit on the stability, but it is still not great. There is also added complication from the driven low side and an intentionally a bit slow response is not too bad for me.

It is tricky to calculate with quite some capacitance from the switches that changes with the gain setting. So the more theoretical way would be from a simulation with a kind of try and error to find a reasonable compromise. A single divider chain would not get a perfect solution, but only some compromise. The best one could get is kind of swamping the switch capacitance with quite some parallel capacitance and than get the same divider ratio for the resistive and capacitive part. Still large capacitors add to the capacitive loading of the op-amp which is not good either.
It is not that bad as in a first approximation for the gains of 1:10:100 without the switch capacitance one would have capacitors in about a 1 :10: 90 ratio, so not too much capacitance to the input.
So one could start with something like 3 pF / 22 pF/ 180 pF. The switch capacitance adds especially the the 2nd capacitor and thus a little larger capacitor at the start. The time constant would still be in the 300 ns range and thus fast enough to get good settling.

Separate divider would make things a lot easier but cause more ground current / capacitance. One could than calculare suitable compensation with a theoretical near perfect result.
One might just accept that the x 10 case gets a bit slower and use only 2 gain settings for the 2nd stage: x 1 for an overall gain of 1 and 10 and than a gain of some 10 for the x 100 overall gain. This would leave the simpler case of only 2 settings for the 2nd stage and thus easy compensation there. 

For my circuit with the input amplifier supply bootstraped this option would not work because of the limited (5 V) supply and output range of the AZ amplifier. The gain of the 2nd stage is also needed get the full output swing. The extra speed is more like a secondary nice to have part. So I don't have that option and need the gain of the 2nd stage relatively high. On the other side I don't care so much about fast settling. So it is a little different situation.

[julian1]

 
One might just accept that the x 10 case gets a bit slower and use only 2 gain settings for the 2nd stage: x 1 for an overall gain of 1 and 10 and than a gain of some 10 for the x 100 overall gain. This would leave the simpler case of only 2 settings for the 2nd stage and thus easy compensation there. 
 

So both op-amp stages would be the same - with selectable 1x and 10x,  to combine for (1x,10x and 100x ranges)?

This is less ideal than combining multiple gain stages to better equalize bandwidth across ranges.
But a 10 to 1 variation is a big win/improvement over 100 to 1 bandwidth reduction.
Only two identical (simple) resistor dividers are needed.
And the capacitor compensation can be chosen specifically.
This seems like a useful compromise point.

[Ole]

Hello there,
does anyone have experience with using an op amp such as the ADHV4702 or ADA4099 for the main amplifier?

Cheers
Ole

[julian1]

The choice of gnd current compensation resistor for the ref board of the 3458a is difficult to understand.

R419, -15V / 2.67k == - 5.6 mA.

But the constant part of the ref current draw is much lower. The lt1013 datasheet current per op is 0.5mA max. And the op-amp only drives two 70k resistors and the 15k temp-set divider.

The ref heater is the largest source of variation in current - although change is slow, per the control loop.

The heater gnd gets its own board header pin/ return path which makes sense.

But the reference board also pulls out a separate +18V heater supply pin, separate from the +18V for the lt1013 (perhaps to ease instrumention/measurement, or else to keep the design open to using a separate secondary winding for the heater).

The lm399 heater is nicer, given one can just divert the variable heater return path to the negative supply rail.

[Kleinstein]

I don't see an obvious problem with the ground current. The current to compensate is the zener current, the 2 paths with the 70 K resistors, the 15+1 K divider and the LT1013 neg. supply current.
I have not checked the numbers in detail, but I don't see a big difference.  There would be a slight chance that HP has a mix of versions and R419 may change depending on the revision (e.g.different set temperature). The LT1013 supply current may also vary a bit. So ideally one would adjust the ground current compensation (e.g. with a 2nd resistor in parallel for fine trim).

Compensating the ground current from the rather high -15 V supply is not ideal, but the 3458 design is not really made for low power.

Because of the possible variations the heater current is separate and thus no need to compensate that current, just a separate ground path to the supply star ground.

Is there a plan to include a LTZ1000 circuit with the DMM PCB ?
Ideally it would be nice to also have a 2nd 7 V reference to at least detect sudden / large drift (e.g. like with Datron 1281, 1271, 4950).

[julian1]

You're right, I think forgot the ref zener current. 0.7V / 120R ~= 5mA

[julian1]

A second ref for artifact calibration, and additional checks is a good idea.
Calibrating against the same ref used to derive ADC reference currents doesn't make a lot of sense. 
I don't think anything changes much for ACAL which is all transfer orientated.

[Kleinstein]

For the ACAL part, to check the amplifier and divider gain it absolutely makes sense to use the same reference for the ADC and the test points. This takes out much of the reference noise and the ACAL part can be relatively fast. Similar for the ADC gain the same reference is a good choice.

The main reason for a 2nd reference is to also check for drift or jumps in the reference. It is not very likely to see jumps or strong drift, but there is a small chance to have a misbehaving part (e.g. a bad joint, contamination, leaking metal can). For a test board having space for 2 types of reference would also allow to start with the simper reference for the first tests. Just for the frist tests the 2nd ref. is not such a big deal - this would be more a thing for more reliable / longer cal intervals. If really needed the 2nd ref. could also be external.

Another point that can make sense for the ACAL part and with CMOS switches it is also not that much effort is to have test points with both polarities. So the high voltage divider would be tested with +10 V and -10 V. One would get two results for the divider ratio, that ideally should be the same. This adds a kind linearity and plausibility test and the average of the 2 ways can also reduce the INL effect on the result. Similar the amplifier gain could also use 2 test points. Due to the low effort it is definitely a part to add. An external signal would be more problematic due to the reference noise.

[julian1]

There is already a lt1021/7V (5ppm/C, 1ppm pp 0.1-10Hz) as a direct substitute for the primary ltz1000. It is included as a low-fuss path to do functional tests, without needing to mess with the ltz1000 circuit.

If a second (third) reference was added, then perhaps another lt1021/7V would be enough for basic sanity checking? I like the lt1021 because it is 7V and an uncomplicated soic-8, and there's no need to mess with heater currents like the lm399.

Datron 4950 and 1271 use ltz1000 + lm399 (0.5ppm/C, 7uV pp 0.1-10Hz ?) according to Marco Reps' recent teardown. (Edit). While Datron 1281 has two ltz1000.

There's enough board space, and I experimented with adding a second ltz1000 ref, on the basis that the opportunity-cost in terms of time/cost/complexity is low - since it can be left bare if not wanted.

But I am now thinking it is still overkill and to remove it in favor of a second lt1021/7V. The extra confidence guarantees (long term drift?, noise checks?) and convenience are marginal. And an external ltz1000 ref board (or several) would perform better for calibration-like validation/tests.

[julian1]

The bipolar 10V/1V DC source was added a while back, because of the possibility of an INL-like test. The divider ratios should be preserved because the bipolar voltages are muxed through the same divider (even if the bipolar voltages do not invert around 0V).
So it's really useful - apart from enabling a transfer cal of the HV divider.

[julian1]

It feels like going off into the weeds, and a bit unnecessary. But several configurations are possible with lowish effort (eg. pick your poison).

- lt1021/7V as primary, for quick setup and tests and avoid a complex ltz1000 circuit completely (most useful).
- ltz1000 as primary, and lt1021 as optional plausibility/check reference (like Datron 4950/ 1271) (easy, given lt1021 already available).
- 2x ltz1000 (like Datron 1281). (aid to identify drift/divergence, possibly valuable)

[Kleinstein]

For the start I would not worry too much about a 2nd reference.  It is pretty low on the priority list, especially not needed for the 1st test. There it is more about having the option to start with less than an LTZ reference for the 1st tests.  Besides the boad space it would also be about having a free channel at one of the MUX. With only a voltmeter there are likely some free input paths anyway. With a full DMM with current ranges it depends.

[iMo]

I would not recommend the 1021 soic.. It is a low cost vref (good for 4 digits imho), with potentially large hysteresis in epoxy, etc. With your high-end front end and your 8+digits goal there are two "cheaper" vrefs I would think of only - the ADR1001 (you get 7V, 5V (-5V), 10V out of it without messing with any expensive resistors, planned release Q4/2023 afaik) and the 399/1399 as the "second" reference. The expensive LTZ1000A solution as your external ultra stable reference..

[julian1]

I managed to do a board with sufficiently few silly mistakes, to make it worthwhile to add components and do some tests,

Some waveform pics of precharge/AZ switching running in a state-machine -

first pic - uses a contrived sin-wave as signal input.  And shows the digital pre-charge switch ctrl-line level shifted to the signal/boot voltage. It seems to work quite well over the +-10V input rage.
second pic - shows a test modulation of the precharge / AZ switching scheme.  the precharge-switch selects the signal for the hi-sample, and then switches to boot to shield/protect the signal, when the AZ mux switches to take the lo sample.

The mux organization is changed a bit to handle all the inputs.
The two hi-mux's select the continuous signal of interest, then follows the pre-charge to select signal or boot, then the AZ muxes between the precharge-output and lo/zero signal.

I want to add a mode to test the pre-charge switching to reveal charge-injection bias in the same fashion as the previous tests done with the standalone '4053.
To do this a charge-capacitor (depicted on U402) can be switched onto the signal, so that AZ/PC switching can accumulate a charge, to be measured after a fixed duration/number of cycles.
This would form a useful self-diagnostic test, to run without any operator action.
The DC-source could also generate the signal inputs with a DC bias (eg. -10V,0V,+10V) to validate.

I chose to try surface copper-fills for soic-8 guarding rather than ring traces. At BOOT potential for hi muxes/precharge swtich, and gnd for az switch.
This is simpler due to how related signals get grouped by the 1ofN muxes, compared with discrete jfets placed about the board.
But it can be changed if needed.
I don't think the extra capactance due to the increased copper surface area is an issue. R405 can unload the BOOT driver output if needed.
The trick is to route signal placement carefully, to avoid any capacitive-coupling to the wrong copper fill.

Some schematic comments are more self-notes and are not reliable.

[Kleinstein]

The scope waveforms look good so far.
The signal switching still does not look ideal: there are quite some CMOS switches in the critical signal path and thus possibly a higher leakage current than needed. Instead of parallel MUX chips and using the OE pin one could better cascade them, so that the less critical signals (e.g. the ref. levels, temperature,..) go through one more chip and only 1 mux chip for the leakage critical paths.

With the MUX before the precharge circuit and bootstrapp buffer the bottstrapping of the zener clamps is only working when the DCV input is actually selected. With a different input selected the input could see a little extra input current. It is not ideal, but also not too bad as the input can be isolared via the FETs from the protection and the extra relay

It is a bit strange to have 2 x PV coupler in series. Most of the PV couplers give some 6-9 V out and thus sufficient to turn on the FETs. The voltage is already limited by the forward direction of the photodiodes.
The ohms sense inputs should have something like fusible resistors at the input, before the GDTs. So in case the GDTs conduct the resistors act as a fuse.

Connecting the ACAL signals directly to the input is nice to include all the protection, but it kind of defeats the protection. So ACAL would need the user to isolate the input.
For the ACAL part for the divder (+-10 V or GND to the divider) one could use the same relay as to connect the divider. So the divider would either see the input or the ACAL signal.
The ACAL signals for the normal input already have a path through the CMOS mux chips.
The Ohms ACAL signal would go directly to the amps part - so the relay K401 is not absolutely needed. It can still help to avoid the leakage to the FETs effecting the input inpedance.
The capacitor at the input to check for input bias current is a good idea. One may not need than much capacitance. To measure up to some 100 pA a capacitance of some 1-10 nF is sufficient.

[julian1]

The signal switching still does not look ideal: there are quite some CMOS switches in the critical signal path and thus possibly a higher leakage current than needed. Instead of parallel MUX chips and using the OE pin one could better cascade them, so that the less critical signals (e.g. the ref. levels, temperature,..) go through one more chip and only 1 mux chip for the leakage critical paths.

I debated whether to have the two muxes in series or parallel.  My feeling was that keeping the input series-resistance the same for the various inputs (even if dedicated to secondary importance signals) was the lesser evil. Particularly as it might affect the distribution of charge-balance during PC switching.   Although thinking some more, the secondary-importance signals will be lower-impedance inputs anyway (refs, TIA, TEMP etc) so it matters less.   

3458a has many parallel jfets for input muxing, although that probably reflects the component choices available at design time (no low leakage/multiple-throw switches) .

If the parallel hi-mux organization was kept, an additional relay could work to switch between them. This would remove all potential leakage from secondary inputs, unless actually selected.

max328 should probably be used for the muxes. But their price is annoying, and couldn't be justified for initial tests

It's not clear if a charge-cap for charge-injection tests, or leakage tests as you suggest, could work without another parallel mux/relay. .

With the MUX before the precharge circuit and bootstrapp buffer the bottstrapping of the zener clamps is only working when the DCV input is actually selected. With a different input selected the input could see a little extra input current.
It is not ideal, but also not too bad as the input can be isolated via the FETs from the protection and the extra relay

I hadn't considered this. DCV could be at +-11V from user terminal input, with the selected mux input at 0V and BOOT at the same voltage.
That isn't very good for leakage.
Even with the protection fets switched off, fet leakage is in the order of nA, so they won't help much.

It is a bit strange to have 2 x PV coupler in series. Most of the PV couplers give some 6-9 V out and thus sufficient to turn on the FETs. The voltage is already limited by the forward direction of the photodiodes.

I found the measured PV voltages to be a bit on the low-side - around 6V with a single opto-coupler.
From memory, I made a judgement to use two, based on an actual RDS(on) measurement of the fets at the driven gate voltage, but don't remember the detail.  Cost of the extra part is marginal, although maybe it looks too unorthodox.

Connecting the ACAL signals directly to the input is nice to include all the protection, but it kind of defeats the protection. So ACAL would need the user to isolate the input.

Yes. I really like the idea of feeding in signals right at the front. And am not sure about duplicating them again at the input muxes. Being able to run ACAL/diagnostics without the user having to worry about the state of terminal connections would be nice.  So perhaps more relays are justified.

For the ACAL part for the divder (+-10 V or GND to the divider) one could use the same relay as to connect the divider. So the divider would either see the input or the ACAL signal.

This means one doesn't get the DC-source (+-10V, GND) right at the input, that could be useful calibrate/do self-diagnostic tests for the protection/fet leakage. But it frees a relay that could isolate the input terminals to keep protection active, and so the operator doesn't have to do it, during acal.

And it could isolate the terminal input, when non-DCV inputs are selected via the muxes.

schematic pic added for clarity. 

[julian1]

With user functions, acal, and test-diagnotics there are a lot of mode combinations.

It is tempting to err on the side of caution, and add extra relays as needed, not to screw something up. On the other hand perhaps this relay arrangement might achieve a similar result, with one less relay.

Does this schematic match what is being proposed?

[Kleinstein]

The PCB may not be perfect, but it could still be usable and good enough for tests. If looks like it is porpulated to a large part already. A possibly new version would be a bit later.
Chances are there will be more points to learn from the 1st prototype.

I agree that the max328 is a bit expensive. The  mux508 or ADG1208 should be OK for the tests.
The leakage specs with the CMOS switches (and MOSFETs) are to a large part test limits. Especially for a prototype / test version the typical values are more relevant.

The 3458 has quite some JFETs for switching, but when doing the critical measurements, there are not that many that are relevant as there is 2 stage switching (Q15) for the less critical signals.


Connecting the divider to the +-10 V ref signal when not in use does not interfere with using the signal for other purposes. The 10 M load has some effect on the voltage, but it would be connected in essentially all uses of the reference. I found it usefull to have a separate, less critical MUX (e.g. DG408) for the ref signals (e.g. +-10 V, +-1 V, +-100 mV, GND,... ). This way the cascaded structure for the input switching comes naturally.

For the protection MOSFETs 6 V gate voltage should be good enough. There is no need to switch them on really hard. A few more ohms of Ron are not an issue and this helps to speed up the turn off.

The last sugested relay circuit looks more like what I would suggested.  Not so sure about the ACAL part with K404 though. This would be OK to link to the current part to do ACAL on the ohm sources.
The plan as shown does not include a direct path the voltage ACAL to the input (one may get away with this). The main point may be a check with a short directly at the input to include all thermal EMF, including the 1st relay.
Another point may be using both available contacts in series in some places to get a higher withstand voltage.

[julian1]

I did some DC hi-pot experiments with the passive side of the input protection.

The IXTY1R4N120PHV  DPAK fets are ranted at 1.20kV. With a trip-current of 250uA,  VDS breakdown was measured at 1.25kV with a slow 20sec. ramp.
Pretty much as expected.

GDT are Bourns 2039-110-BT1LF.  They have a rated DC Sparkover at 1.1 kV. The value was chosen to be low enough to protect the fets, while still permitting/withstanding a 1kV potential, with some margin for tolerance.

The GDT are surprisingly small - smaller than some low-voltage 75V TDK ones I have. And they also don't light up on discharge unlike the TDK which I find a bit odd.
One example measured a sparkover at 0.94kV
a second example measured 0.95kV.
Quite a bit less than the rated 1.1kV, so this looks funny.

To rule-out issues with the hipot tester, I measured the output set for 1kV with a Fluke handheld DMM, and got a reading of 1.04kV, a 40V difference.
A bit out of calibration, but not that bad.
The current measurement looks right at 103uA, which would correspond to 1.04kV on on the Fluke 10M.

The MOVs B72214S2621K101, are rated at 825 VDC, varistor voltage 1kV, and clamping voltage 1.65kV.
In practice with a trip current set to 250uA, I measure 0.94kV / 285uA leakage.


When put in a circuit configuration, the MOV leakage and resistors should hold the base of the inductor/GDT at GND potential, when not under over-voltage condition.
When GDT sparks, its withstand/resistance drops as the discharge becomes and arc/plasma, and then the MOV withstand-voltage becomes relevant to disipate the current.

After putting parts on the board, I expected the GDT to spark-over at the same voltage (0.94kV), as tested in isolation.
But it actually withstands a measured 1kV output which I find quite odd.

Above 1.1kV there is some noise under the high voltage tension, like the GDT is temporarily/partially firing.
And at 1.3kV the hipot trips for a higher current (5mA ).

[julian1]

I should have looked more closely at the GDT datasheet, they are not precision devices!.

Bourns 2039 DC Sparkover ±20 % @ 100 V/s .
https://au.mouser.com/datasheet/2/54/BOUR_S_A0009095386_1-2539056.pdf

I will also experiment with a lower voltage MOV, so that when the GDT sparks, the MOV will take more of the current. 

[julian1]

I looked at a few GDT datasheets. 
Most parts seem to be +-20% tolerance.
To support a 1kV input, a GDT with rated spark-over of 1.2kV (or a bit more) would be needed.
And to avoid avalanche mode, the fets would need a VDSS of 1.4kV/1.5kV, to withstand GDT part tolerance on the positive side.
But these are a bit rare in DPAK, and a package change may be needed.

Furthermore, some GDT datasheets give more information for faster HV discharge events, for 100V/us, as well as more commonly quoted 100V/s figure,
The faster voltage event has a higher spark-over voltage. eg.

                                 100V/s  100V/us.
GTCA28-122M-R03 1200V    1900V

So I think this is also a nudge toward using larger fets.

I am somewhat confident the optocoupler gate drive can drive larger fet gates.
The most recent test showed a <=1us engagement with only 20V OVC, achieved by removing some (silly ) RC left before the zener clamps,
and by directly probing the isolated fet gate to source.

The zeners themselves will clamp the voltage Ok to protect the inputs on the fast time-scales.
But the possibility of damage to the fets exists if voltages exceed datasheet maxes. 

[Kleinstein]

Getting protection to 1 kV and ideally also higher transients is hard when one also wants very low leakage and very low noise (not too much resistance). One may have to compromise a little between protection and noise / precision.

One point I find odd is the inductor in series to the GDT - the inductor makes more sense in the input path, possibly behind the GDT, to slow down the very fast transients and reduce EMI. Extra impedance in the path with the FETs limits the peak current, at least for the time until the GDT fires. Most MOSFETs can withstand some transient break through with limited energy.
As FETs may fail short it would be a good idea to have some secondary protection as backup, something like PTC or fusible resistor (or both). Still more elements in series add potential thermal EMF. So it is a compromise between protection and precision.
The Keithley 2001 uses 2 FET pairs in series for the protection to get better protection. The K2002 and 2000 use only 1 pair.

The PV optocoupler should also be OK with a larger FET gate. They can usually deliver a few µA and the gate current is more in the nA range, possibly more from the protection zener than the actual gate.
The FET case is anyway a bit tricky, as the pins are often too close togehter to really reliably isolate the high voltage.

I used the small DPAK for convenience and in my circuit accepted a lower maximum voltage.  A reduced design voltage make things a bit easier with the protection and also the relays.

[David Hess]

Getting protection to 1 kV and ideally also higher transients is hard when one also wants very low leakage and very low noise (not too much resistance). One may have to compromise a little between protection and noise / precision.

Oscilloscopes use like a 470k series resistor before the shunt protection and then control noise by bypassing it with about 1000 picofarads of capacitance.  This sort of thing is also common on multimeters, but of course the noise is still a problem at low frequencies.

For moderate voltages, a small high voltage (120VAC) incandescent lamp can operate as both a series PTC thermister and fuse having the advantage of low resistance when there is no overload.  Very sensitive oscilloscope inputs may also use this method.

The least common method I have seen is a pair of anti-series high voltage depletion mode MOSFETs to limit the current before the shunt network.  Like the lamp this has the advantage of low series resistance until overload occurs.

Electrometer designs have high supply voltages available for bootstrapping their input buffer, and this can also be used to bootstrap the input protection to remove leakage through the shunt protection.

[julian1]

I did some reading around fets and over-voltages, and the avalanche figure and 'avalanche rating' are the interesting figures/parameters.  It is a topic of interest to smps design. 
The series inductors to the fets, indicated with 100u (may need 1000u) will limit current rates.

Perhaps the GDT series inductors (1u) were intended to ensure that once the GDT goes active, they stay on for a period.
They appear dropped from later HP designs.

From a practical standpoint, I realized DPAK will fit in DPAK2 footprints. So part choice can be defered to assembly, rather than be baked into the pcb.
Although the smaller DPAK footprints part tidier.

There are some quite small and PTC devices, but thew are only low-voltages.

[iMo]

....,,
..Perhaps the GDT series inductors (1u) were intended to ensure that once the GDT goes active, they stay on for a period.
They appear dropped from later HP designs..

I think putting any L in series with a protection device wired in parallel with the input wire will simply cause the rising edge of the transient will propagate into the input and not fire up the protection device (as the L will block the rising edge from entering the protection device)..

[julian1]

....,,
..Perhaps the GDT series inductors (1u) were intended to ensure that once the GDT goes active, they stay on for a period.
They appear dropped from later HP designs..

I think putting any L in series with a protection device wired in parallel with the input wire will simply cause the rising edge of the transient will propagate into the input and not fire up the protection device (as the L will block the rising edge from entering the protection device)..

Yes, they should be omitted.

[julian1]

I just noticed max328 (octal 1ofN) switch is not available in 'normal' narrow soic-16, so I can't easily test it.

Instead, the footprint options are - wide-body soic-16 which are huge and don't support substitutes/swapping, DIP, and narrow pin-pitch footprints that do not allow pin guarding.     
It would be nice to avoid the design being pushed into using legacy-like footprints.
Some alternatives for muxing the three main critical inputs (dcv, 4w-hi, other) are -

- use 4x spst. max326, that comes in normal soic-16. and which I already have.
- use dg508, adg1208, in normal soic-16, that promise 'low' but not 'ultra' low leakage.
- use jfets. easy availability, and lots of part choices,  mmbfj201, mmbf4117 etc.
- use relays. two small agn200 relays, can mux the three inputs (dcv,4w-hi,other).
- MUX36S08 is narrow pitch only.

Probably the AZ switch itself, is also a candidate for using max326, or jfets. although leakage there is likely to be linear with the single hi input signal.

Perhaps there is some other stand-out consideration that might influence part choice?

I couldn't find much real-world data on leakage, so I have made some simple prototype pcbs for quick tests for cmos versus jfet choices.

[julian1]

Another possibility would be adding a single low-leakage series jfet placed between two series CMOS muxes. 
This would prevent lekage currents from secondary-importance signals switched by the first mux, finding their way to the primary hi-mux for dcv,4w-hi.

[Kleinstein]

Leakage data are tricky. There is often a big difference between the spec limits (= test limits) and the typical / real world leakage. Tight tests seem to be expensive as it just needs time (so that DA can settle) to measure pA range currents. So cheap parts often have loose specs. This applies to CMOS and JFETs as well.

Separating the singls into critical low leakage signals and less critical ones is a good idea. There are usually only a few critical signals and thus only few (e.g. 3 -5) really low leakage switches needed. The less sensitive signals (e.g. the ACAL levels, shunt signals, buffered signals,...) can than use normal / cheap CMOS switches like DG408 / DG211 or even HC4051 for some signals.

JFETs should have essentially no leakage when on, as there is essentially no gate voltage. They still need more effort with the extra gate signal and things like a LM339 as driver. When off the leakage is expected to be an about constant current, with little dependence on the voltage.  CMOS may be a bit lower leakage when off, but can have gate leakage when on. In addition there are the protection diodes.

Some of the leakage current can also compensate. In some cases DMMs have additional JFETs for clamping towards the positive supply, that also compensate some of the current.

The bootstrapped pre-charge circuit should give an essentially fixed leakage current, as the supply for the chips is bootstrapped and thus fixed conditions. So far the leakage I have seen was low ( ~ 5-10 pA), though the specs for the LV4053 are not tight at all and allow much higher leakage. Of cause the leakage can vary.

In my concept I have 2 points to reduce the switching a little:
1) I have not MUX befrore the precharge part and thus 2 seprate precharge parts for different sources ( voltage inputs).
2) The high voltage divider has a seprate AZ amplifier as buffer and thus changes form a rather sensitive signal to a non critical one for switching.

[julian1]

My plan was to use MAX328 as the obvious lowest-leakage/convenient form-factor part, and call it done.

But it's probably worth taking a step back and considering the design principle,

It's a good point about the bootstrap precharge/ switch leakage. This circuit really determines the order of/budget for permissible leakage for anything else built around it.
I will test it again, since the previous isolated tests were more for charge-injection
Probably both input and output leakage tests are needed, to include gate,supply/cross switch leakage.

And then test some analog switches/jfets, to see how they compare.

For critical signals - the hv divider, and DCI/current for low-current ranges if no TIA is used should probably be included.
With the effort put into the AZ front-end, it probably makes sense to use that in preference to adding AZ op-amps,

Modern DPDT relays have the possibility to mux both sides of a signal, into the AZ mux eg,
  - 4W hi, and 4W lo on one relay.
  - DCV  and LO. on another.
  - DCI-HI and DCI-LO on another relay.

And this might help cancel thermal/EMF offsets on the disjoint metals used in relay construction.
Although the input selection path already includes single-ended relays and a terminal gang-switch, so it's not clear if there is an advantage.

Including an input-path - with only semi-conductors - to be able to measure the thermocouple offsets of mechasnical components - as you already pointed out is a good idea.

[julian1]

Actually I think the front/rear gang-switch is double-ended (switches hi and lo) so (potential) thermal-couple effects should be cancelled, provided no strong board temp gradients.  And for current it doesn't matter.

[Kleinstein]

With latching relays I would not expect much thermal EMF from the contracts, as the thermal gradients are expected to be small. It is also not at all clear if the 2 contacts see a similar gradient / difference and thus could provide compensation. Compensation works nice with 2A type reed relays (e.g. input of the 34401, 3458).

Using an AZ op amp as a buffer for the divider is relatively easy and comes with a nice side effect.  An AZ buffer can be quite easy, in my case an MCP6V76 and TL061 and a current source. The buffer is not replacing the main amplifier, but an alterternative to critical switches and the pre-charge part (if used individual per input). The divider (e.g. 100 K resistance or more for a smaller divider ratio) already has quite some noise. So there is no problem in having a buffer with a noise in the 20-30 nV/SQH range. The non standard option that one has with a buffer is to use not just a classical divider, but a kind of hybrid with an inverting amplifier / active divider. The output of the buffer is inverted with a not so critical inverter and the divider is than not towards ground be towards to inverted signal. This way one gets a positive and inverted output signal and effectively doubles the range for the signal input. In addition the input is sampled essentially all the time even in the AZ mode. This allows for a lower noise (some 30% less) even with the same divider (e.g. 1 :100) and even more (50% range) with an adaped (e.g. 1:50) divider to make use of the large signal range.

For the bootstraped precharge part the through the switch leakage should not be critical. The 2 switches there see essentially no differential voltage (only the offset of the buffer). Bias on the output side of cause is part of the input bias.

[julian1]

I did some stand-alone switch leakage tests.
Current leakage to gnd of the analog-switch (adg1208, dg508) output was measured while applying a high-z, +10, -10V voltage to an (open/off) input pin.
The results are quite good,

adg1208
measured rds(on) 111R
fixed  leakage, around 0.5pA .  (copper guard was left floating, so leakage from board pwr/ctrl pins to guard is possibility, not just internal fet gate/protection diode/substrate leakage),
+-10V on input gives +-0.5pA. change in output current after allowing maybe 20sec for settle time.

The behavior is the same - whether all ctrl pins are lo - or if EN is hi and an unused input pin is made active.
This indicates the EN pin works as logic only, and doesn't control some global extra internal isolation fet.


dg508. maxim/AD.
measured rds(on)=295R.
around 1pA fixed leakage (guard left floating, so leakage from board pwr/ctrl pins is possibility),
and +-10V, gives maybe +-0.1pA current diff on output. very hard to measure.

I have max328, but probably won't test it, as it would require a better setup / DUT shielding, and automated/scripted operation.

But, I think it is enough information to favor usinig them versus or jfets/relays, given that -
Ib of the guard buffer is already expected to be around 1pA.
And the floating pre-charge switch leakage is expected to be higher still.

The input relay muxing has been reorganized for improved terminal isolation during ACAL function.
This has the added benefit of reducing leakage/non-linear affects of leakage into the critical hi-mux.

Currently when a specific DMM function/mode is *not* active - the signal present on the input pin corresponding to that function is held high-z, at boot potential, or else attenuated.
   
Currently -
- when DCV is not used, input relay k405 is open, and output is held at boot potential by the input protection (via bootstrapped clamp diodes).
- when secondary-importance/buffered signals (refs, voltage-source, tia) signals are not used, the second mux output is held at boot potential (by muxing BOOT on its input).
- when DCI-HI is not used, the current input/protection/acal relay is open (K702, and ohms-source-relay) and output is high-z.
- when DCV-DIV is not used, K402 is open and output is high-z. exception if using DCV with 10M input impedance - then DCV-DIV is 100x attenuated at the mux.
- when 4W-hi is not used - ohms current source relay is off. exception if operator leaves 4W cabling attached to DUT while in 2W or DCV omde, then the measured voltage is duplicated on two mux input pins . but that is probably an ok edge case.


- A question exists - if the non-active/unused input pin voltage should be switch from the guard buffer voltage to agnd/0V.

So, the DCV could be held at AGND/0V (via the bootstrapped clamp diodes) during current measurement mode - instead of following the guard-buffer for DCI-HI .
Likewise for the secondary-importanace hi-mux, which could be follow AGND/0V, instead of boot.
Even just as a test/diagnostic I think this would be useful.

- There is already some guard switching for current ranges - eg. on shunt-ranges boot/guard follows the shunt voltage, but if TIA is engaged it follows agnd/0V.

[julian1]

To summarize, and try to reduce scope a little, a good simplifying change - would be to at least make the bootstrap voltage on the clamping zeners switchable when the dcv input is unused.
So that the corresponding pin of the hi-mux could be held at agnd potential to reduce leakage effects.
And then similar treatment for the secondary hi-mux, that can mux agnd on input, to keep the corresponding pin of the hi-mux at agnd, when unused.
Most of the other inputs are already high-z when in-active due to switching relays.

[Kleinstein]

If one really cares about super low leakage and use with very high impedance signals it would make sense to pull at least the zener clamps to GND for the unused inputs. Depending on the diodes (Si or IR diodes of an optocoupler) used for the final clamping step this would limit the residual voltage so some +-0.5 to 1 V. I somewhat doubt one would need to really pull the input to GND. Some signals like the divider would be at essentially GND anyway. So it would be mainly 1 or 2 inputs. to worry about.

For the secondary mux one could choose a signal close to GND (e.g. low shunt or 100 mV ref level) to get at least a fixed amount of leakage.

Leakage currents in the 1 pA range looks really good. I don't think this should give problems for a more normal DMM input. After all this is not an electrometer input.

[miro123]

I noticed, that some confusion comes from mixing up two different concept.
1. Old fashion dual/ multi slope, where processing mostly analog in nature, so problems with absorbtion & charge injection  was dificult to resolve.
2. Modern SD ADC, ad7177 etc (I'm experimenting with max11270 & mcp3562) - here we shoudn't care about injection & switching whatsever noise since it's much easier to throw  a sample taken rigth after switching and take another one after long enough settling period, 1 millisec or so. Counting to get 1 kHz sampling rate high just above most OPA +Voltage references   1 / f corners. So requirements to switching IC is close to non - any cd4043 is good.

I've read the whole thread 6 pages. My short summary "Echo88" started this thread giving  an solution related to your second point (modern SD ADC). The whole thread went in cogently other direction as topic starter (old fashion DMMs)

My question is does somebody works on AFE for modern SD converters?
My epxeriance in this areea so far.
1. Build AFE based on PGA280 coupled to ADS1256 - that was good first time experience, but I run to the limitation of this simple design
2. Evaluated ADS125H02
3. Looking to do  AFE based on HPM7177. Idea look straightforward, but I don't like two thinks
  - Using 8 of precisions resistors - yes some of them cancel the TC effects, but still a lot of dependency /cross correlations.
  -Applying raw power to solve TC issues - It is great solution for CERN, they run in lab environment, no huge ambient temperature deviation. Peltier oven works fine for them
4. Using THS4551 or THS4561 LTC6363- They have limited  DC perforce in single IC AFE configuration, but they delivery the BW needed to drive modern ADCs.
  Questions
- How can I create outer DC stable loop around those FDAs/THS4551,4561,ltc6363/? Can I reduce the number of precisions resistors used by HPM7177 design
- Do I need to start separate thread - related to AFE for modern ADC?
Greetings,
Miro

[Kleinstein]

The front ends for a SD ADC chip and old style multi-slope ADC are indeed different. It is not so much about switching / charge injection, but the voltage range. MS-ADCs are usually build to work with some +-10 V input range relative to a ground. The SD chips usually have a differential input and some types need true differential drive to use the full range (e.g. +-5 V). Even if not needed for other ADC chips, differential drive may help with linearity.  There are a few common points with the protection and input switching, but it is more like a separate topic and maybe worth a seprate thread.
Another point needed is the ADC drive part - which is not easy and can effect the INL.

The PGA280 looks nice for a relatively simple solution with maybe 6 digits, but there are some limitations with the input bias and linearity to really reach the high end.

There are alternatives to the HPM7177 design and some should get away with fewer precision resistors. The number of precision resistors needed by itself is not that bad - the question is here if there are of the shelf suitable resistor arrays available. The HPM7177 design is with a signle range - with additional gain settings things I see more complications.
My DMM design with an AZ amplifier at the input is somewhat suitable to a differential ADC, but it would not add attenuation. So the range would be the same of smaller than the ADC input, so +-5 V (and smaller ranges) for the AD7177 or similar. On the upside there are no critical resistors for gain 1.

DC stabilizing a fully differential amplifier could be tricky - at least I don't see a simple way. The typical differential gain circuit with low input impedance is anyway a bit limited for high precision and they need 4 precision resistors for 1 amplifier.

[Echo88]

The number of precision resistors in the HPM7177 is rather low: 2x PTF56 + 3x S102K for the LTZ1000 and some networks for the input divider and ref divider. In my case TDP1603 are used instead of Vishay PRND.
I havent yet tested my version fully and it will take a while.
I also dont really know a way to use the THS/LTC6363 in a composite design, i rather use the proven drivers from the HPM7177.
Wether a new thread about modern ADC frontends makes sense or not i cant judge.
I assume that this stuff gets rolling again after a proven design gets available as open source for multiple people to test.
Attached is a suggestion from my side, based on the 3458A JFET-frontend with added gain selection based on TDP1603 and ADC-drivers based on HPM7177. Due to two unknown Dual BJT/JFET used in the 3458A-frontend one needs to find some available ones that fit the spec.
Its not complete, does anyone notice obvious flaws or things to improve?

Edit:
Changed guarddriver to lower biascurrent one MAX9945 instead of OPA140 (LMC662 supply range not suitable).
Added 3458A Black Edition original used AFE-transistors.

Heres are the datasheets for most of the transistors used in the AFE: https://edesign.astutegroup.com/wp-content/uploads/sites/2/2022/03/2022DataBook-Linear-Systems.pdf

[Kleinstein]

For the JFETs for a discrete build low noise amplifier the TI JFE2140 should be a pretty good choice now: The offset, input bias and noise are pretty low and it is reasonable available and priced. Chances are one can get away without an extra offset trim, maybe a single resistor to choose, if one wants very low thermal drift. I see no need the the DAC to adjust the offset, especially not with the low offset JFE24140.

The suggested plan has a few odd points: The extra buffer with U5 U9 does not help and only adds noise and possibly a tiny bit of drift. A similar argument applies to U3+U6.
There are AZ amplifiers also at point's where they are not really needed: e.g. U8 for the GND current compensation and the U12/U13 buffer for the 2 nd divider. Here a more simple buffer (e.g. OPA141) would be better (less bias an the first divider).
A suitable substitute for the MC34081 would be the TLE2071 - it also has a common mode range extending to the positive supply, which may be an issue here.

The divider with RN2 for the 100 mV range is rather high resistance. If one is after low noise one would use smaller resistors (maybe 500 Ohm ?) here.

It is not good to use a 1:8 MUX for the gain settings as the unused channels add extra leakage and capacitance. A 1:4 MUX would be the more obvious choice.
The switch capacitance can be tricky and may require at least some compensation capacitors.

The AD8065 with a +-12 V supply should have a resistor at the input for protection in case the stage before goes higher than +-12 V.

A current of 4 mA for the JFET amplifier is way to high for a precision amplifier. This has a good chance to cause thermal nonlinear effects. 4 mA may be OK for a more nV meter. A large range linear amplifier would be more like 200 µA to 500 µA.

The way the circuit is shown the initial part could be the same as for a multi slope ADC. So not really a separate thread for this.
However this way there is no range with no gain/divider before the ADC. So the stabilty of the TDP divider network RN6 would be overall gain quite a bit in all ranges. There is a good reason the HPM7177 uses the expensive custom resistor arrays for the divider stage.
A front end planded directly for the ADC chip would have a 5 V range with no gain / dividers and then maybe a 12 or 20 V range with divider and maybe 500 mV and some 100 mV with gain, but no divider. This would than be a different type of front end. So not so much inspired by the 3458, but maybe more like the SDM3065.

[iMo]

Would be great to design, as a POC, a simple +/-12V input front-end only (capable say 7.5digits). It will satisfy 90% people here, as most of us want to measure their references only. After some practical evaluation by the experts here, the next step could be adding more ranges, and other functionality, etc.
A rather complex design with many exotic parts might end-up as a single prototype gathering dust, as people will not be able to reproduce it..

[branadic]

Would be great to design, as a POC, a simple +/-12V input front-end only (capable say 7.5digits). It will satisfy 90% people here, as most of us want to measure their references only.

If that's the way you are comparing references against each other you're doing it wrong, as you completely rely on your meter, its reference, input path and linearity. Measuring the difference between two references in the lowest range of your meter is way more sufficient.

-branadic-

[iMo]

You do not need to have a 7+ digits capable meter for comparing two references. A single opamp null meter will do it  Anyhow, the first thing people need is to measure the references absolute voltage, imho
And people do it as you may see from the graphs published for example in this section..

..Measuring the difference between two references in the lowest range of your meter is way more sufficient.

[Echo88]

All good points Kleinstein.

Offset/Bias-compensation might be not neccesary here as you point out when using a low offset JFET, thats why it was so only added as suggestion.
Youre right about U5/9/3/6 being unnecessary.
I kept U9 behind the TLE2081 (the 3458A Black Edition uses it, good guess with the TLE2071  ) to avoid thermal load feedback of the TLE2081 to its input transistors, though the 3458A apparently works just fine without it.
The TLE2081/AD8065-stage might need correction.
GND-Compensation-OP can indeed be generic.
U12/13: 125pA bias * 5kR = ~10nV, i dont know if id trade that with the offset drift of the OPA141...
Changed RN2 to lower resistance 460R variant, which is also available. 1k might also be useable, id need to calculate noise contribution.
Can you suggest a 4:1 low leakage Mux? Seems to me alternatives like TMUX6111/TMUX6136 arent much better?
Good point on the limiting resistor in the composite OP stages, was a little worried about them before.
Changed JFET-stage current to the original value from 3458A: 1.78k which equates to 1.4mA and therefore 0.7mA through each JFET/BJT.
I added the changes and suggestions which JFETs/BJTs were assumed used in the 3458A black edition, these details/photos are also available on xdevs as linked in the schematic

Can you expand on your reasoning why the RN6-network isnt suitable compared to PRND? Are we talking about an influencing power coefficient here or other errors?

I wont go for a 5V-range with this design.
While it will benefit from gain-stage-avoidance and therefore have very good specs, it still feels half assed.
If the gain stage really needs better networks than TDP1603 im willing to go that way if necessary, i just want to avoid such costly stuff were its not necessary.

I attached the revised schematic.

[miro123]

It is nice to look at open source HW development
Everyone has the freedom to choose own architecture design en implementation.
Here my remarks over current schematics
1. Cascaded opamps has no purpose here. They are used to mitigate HF ADC SC spikes. 
2. R15 R16 1K - to high. It is related to my previous remark - they completely decouple the ADC from the driver
3. Are you planing to use ADC on different board on your final design?
4. ADA8265 can be susbstituted with opa525 opa2625  /if needed/
5. how you gonna achieve thermal coupling with TDP  resistor networks - old school DIP package does not offer thermal connection. No therlaml bridge  e.g.  LT5400
6. Where is the auto calibration circuit? Do you plan to use autocalibration? If yes what type  - gain ,offset, linearity or all of them

Personally I will stick to HPM7177 architecture - differential input AFE
1. Differential inputs easy the PSU requirements.
2. lower Thermal EMF lemo connector - simple physics - lower dT -> lower EMF
3. lower EMC issues due to the twisted pair shielded cable. Applicable in modern world where we are surrounded with noise from 50Hz to 6GHz


 

[Kleinstein]

The RN6 network at the single sided to differential stage sees quite some power and this will cause thermal INL problems. 4 K and up to 12 V would be 3 mA.
To keep the power at a reasonable level one may have to use more like 10 K values and even than it may be a possible source for an INL error (depending on the TC).


For the gain settings the TDP networks should be good enough, at least linearity and noise wise. For the long term stability the data-sheets are often not very specific. Part of the problme is that there is one DS covering a large range of resistance values. Chances are that things are better in a more moderate range (e.g. 10 K ) than for the extremes (100 K or 100 ohm). Long term drift specs are anyway tricky - who knows how a part really reacts to years of aging and real world thermal cycles. Accelerated tests are somewhat limited.

The cascaded OP-amps have multiple purposes, sometimes just one is enough justification:
1) high frequency spikes
2) remove the thermal load from input stage
3) reduce the loading effect on INL (output cross over)
The 2 OP buffer stages may need an extra resistor in the FB to the AZ amplifier. Otherwise the 100 pF are quite some load to the fast OP-amp and may cause instbility.
Anyway - these are the stages that may be skiped anyway.

The U12/U13 part does not need to be low offset / low drift. There drift compares to 10 x the JFET stage drift and is corrected with the AZ cycle anyway.

For a low leakage 4:1 mux, there is the MUX36D4 as a close relative to the 36S08. The 2nd half would than just stay unused. the 4:1 mux chips often come as 2 pole ones.  Analong has the ADG1209 and there are probably more to choose from, many even with the same footprint (if same case).

[Echo88]

@miro123:
1. like Kleinstein said, cascaded OPs which drive the resistor networks are used here to avoid thermal feedback in the AZ-OP due to changing load current, which would decrease their excellent specs
2. correct, directly connected to an ADC this part needs to be changed a bit anyway for CM/DM-filtering depending on ADC-type
3. this frontend is intended to be used later with AD7177-2 and AD4030-24 ADCs, all sitting on the same pcb and thermally stabilized like in the HPM7177
4. yes, in this case the ADA4523 are used due to their excellent CMRR and Avol-specs, to minimize their error-contribution. The OPA2625 can drive the ADC directly, but its not suited for this task without working in a cascaded OP-stage due to its worse specs.
5. TDP1603 are used since:
-DIP-package which reduces mechanical strain from pcb-TC/humidity swelling and therefore changing resistor parameters
-8 available resistors allowing many dividers combinations
-proven in stuff like Wavetek/Fluke 7000 reference, CERN PBC 10V/10mA source (assumed due to paper)
-noise-spec was tested by Nikolai Beev
If further thermal coupling seems necessary that is no problem by usage of thermal jumpers. The TDP1603 dont need to be thermally connected to each other, the design was done so that every divider is consisting of only one TDP each time.
6. The autozero/gain-switching stuff isnt yet included in this design, but will sit in front of the jfet-AFE like in the 3458A. I still need to design it.

The JFET-AFE could also be done as a differential input, but i dont know what parameters will be affected, since im not capable of fully designing a suitable differential cascoded AFE myself. Since the 3458A seems to do well with its AFE, i just copied it hoping for the best.
LEMOs + maybe thermal jumpers for even better thermal coupling are indeed a good choice and ill also go that way.

@ Kleinstein:
Indeed RN6 is probably the most problematic network with its several 10mW dissipation swings. I hope the thermal stabilization (like HPM7177) will help with it, but im unsure if were still talking about TC-effects or already power coefficients, which are of course not as easy to deal with.
Increasing the value as suggested should help, but i have to do calculations again how that influences parameters.
For people that dont use TEC based thermal stabilization of their AFE the trick from CERNs PBC might help: keep the network-temperature constant regardless of dissipation changes with a controlled heater thats thermally connected to it
2x VHD200 might also be an option as a last resort.

Need to read the thread again about the switch-discussions between Julian and you, to produce a nice AZ/Gain-switching in front of the JFET-AFE.

Attached is a prototype-picture of my first Rev. 0 HPM7177-variant. Yet without aluminium blocks and not completely working (hence the logic analyzer...).

http://cds.cern.ch/record/643294/files/cer-002399331.pdf CERN PBC-paper

[Kleinstein]

With RN6 the problem is with the power coefficient, so the input voltage changing the power and this way effecting the resistance ratio. Part of the effect can be local to the resistor and thus a heater and even if using 1 or 2 of the resistors in the network for this would not fully help. This is especially the case with the BMF resistors. With thin film resistors chances are a bit better that the power coefficient is close to temperature change times TC.  The balance with RN6 is between the power coefficient (causing INL) and resistor noise.  I have not tested the TDP resistors, but from my experience the MS ADCs the critical power level is about in the 5 mW range for networks in SO16/SO8.

The auto zero switching before the JFET amplifier can also be used in a kind of differential way. Many meters only do it pseudo differential (one side close to ground), but there is nothing to prevent switching between 2 really different signals. This way I get the 20 V range in my DMM circuit. However it gets a bit tricky with gain.

For the extra driver OP-amps in the 10 to 5 V stage it may be a good idea to use a lower supply voltage there, possibly down to the 0/5 V as for the ADC. The output should not go higher anyway and this would reduce the heating and ease limiting the output voltage. Chances are one would loose a little (like 10%) of the ADC range anyway due to clamping and limited drive.

[julian1]

For the power supplies, I have a salvaged 34401a/34970a transformer, also available for sale as replacement parts.
 
The tranformer's molex connectors/ and pinouts were copied for a test pcb, with some extra jumpers for the screen/guard part.
The 34401a transformer has an isolation screen but the service manual schematic shows it isolating the earth-referenced/ winding which is not useful.
Functionally, it works, but the primary/secondary has measured capacitance of 58pF which is not good for CM noise.

There are quite a few eevblog threads on low-noise dc/dc converters.
Designs include controlled-slew (lt1533), sin/triangle-wave, current-mode or open-loop push-pull.

https://www.eevblog.com/forum/metrology/(3300)-wavetek-7000-the-hidden-gemstone/25/
https://www.eevblog.com/forum/projects/lt1533-lt3045-low-noise-dcdc-pcb-suggestions-needed/
https://eevblog.com/forum/metrology/power-supply-for-voltage-references/
https://www.eevblog.com/forum/metrology/keythley-2612-teardown-and-repair/25/
https://www.eevblog.com/forum/metrology/dmm7510-coax-transformer/ 
https://www.eevblog.com/forum/projects/what-kind-of-transformer-is-this-(eevblog-1119)/
https://www.eevblog.com/forum/projects/low-common-mode-noise-dcdc-converters/


But I am wondering about a self-resonant push-pull approach, as outlined in the Jim Williams AN118, but adapted to low voltage.
Some quick experiments with a high-AL nanocrystalline core, show it's possible to create suitable windings with a measured Cps <= 1pF .

Is there a better approach?

[julian1]

For the amplifer -  the good ideas (non differential) are already given in this thread.
eg. HP/ 3458a for design inspiration, with (optional) Kleinstein modifications for improved linearity, and bandwidth across ranges.
I did some quick tests for linearily, but am not confident about control over confoundinig issues, so it needs to wait  (leakage due to guards at wrong potentials, emi on sig-gen for supply sweep, limit of DMM 100mV range).

Noting that the amplifier is not really in a low-noise configuration due to low cascode base current/ to reduce <strike>Miller</strike> Early effect. and with inductor repalcing low-value source resistors.
lsk389 is less noisy <=1uVpp/ 0.1-10Hz. than jfe2140.
jfe2140 5-6uVpp but seems to settle down 24hours after heat/solderiing to 1-2uV. but quite popcorny, not a guassian distribution.
if3602 is qualitatively different, but has a thermal walk - probably would need a per-cycle AG function/ with a DC source for low reference voltages.

these were quick tests mostly for function - not sure if they are in-line with expectation. It is evident that better shielding/supplies are needed, and I am quite capable of screwing something up.

[Kleinstein]

The main advantage of the resonant converter is that it can work well with loosely coupled transformers and more stray inductance, like with the 2 cores in series. The energy stored in the core is not lost or causing ringing.

For the number of turns one has to choose it according to the voltage / magnetization level, not only the inductance. The dirver circuit than has to work with the inductance one gets from the transformer, not so much the other way around.
It is not only about low capacitance, but also low effective voltage. Here it can help to start from a relatively low voltage, which is easier for a DIY transformer anyway with a relatively low number of turns. It can also help to just have a low voltage (e.g. 5 V) winding on the secondary and generate the higher voltages (like +-20 V) via charge pump / voltage doubling rectifier.

So far I have tried the SN6505  hard switching driver. However it has a weak point in using some spread spectrum mode with some 50 Hz FM modulation that may cause some LF noise. Otherwise it is OK-ish and like other higher frequency converters it needs care with the fitler layout as trace inductance can matter. The relatively high frequency allows for the use of MLCCs in the filter / charge pump which is nice.
A high frequency also meany the transformer can be small and thus naturally low capacitance.  TI calls it low noise, but I consider it low noise in the reasonable easy to meat EMI limits sense, not really low noise for a sensitive instrument. It may still work with an external clock to get rid of the spread spetrum part.
Another option I have tried is µC (output side) controlled old style BJTs to drive a relatively large ring core with high Al and quite some RC snubber to suppress ringing. It works, but is a bit clumbsy and the capacitance is not that small, though likely still OK.



For the JFET noise the relevant frequency depends on the speed of the AZ cycle that is used. With a 1 PLC mode this would be some 25 (30) Hz and with 10 PLC 2.5(3) Hz. So the 0.1 - 10 Hz band may be a bit misleading with too much weight on the very low frequencies.  From my experiance it seems to be normal to have popcorn type noise for the low frequency part of JFETs. The steps just can be quite small with larger JFETs.
From the data-sheet values the JFE2140 should also be relatively low noise (0.12 µV_pp with 2 mA - likely for 1 FET and thus some 1.4 times that in differential mode).  With a low 200 µA the expected noise is about 3 times that, but there can be scattering between parts.

[Echo88]

Question:
Im getting very nice and linear results with my prototype HPM7177-version between about +-7V. More than that (i can measure up to +-11.5V) and its getting very nonlinear, with errors approaching several 10mV.

An applied input voltage of say 10V is measurable after both OPA189 without voltage errors (so the ADGs and OPA189 arent the issue) and the voltage at the ADC input cap is about +5.0018V and +0.6mV to gnd.
The 5Vref in my variant has about 5.357V due to usage of TDP1603 instead of PRND and the resulting slightly different divider factor.
The ADC AVDD is 6V to account for the 5.357Vref, which is within datasheet spec.
Since the common mode voltage for the input difference stage is derived from the internal 2.5V ADC-ref, might this be the cause for my nonlinearity-problem above +-7V?
Since the TDP1603 are 10k in the difference stage i doubt its them misbehaving due to TC/PC.
I could derive Vcm also with a 1:1 divider from the 5.357Vref (->2.6785V), but that would necessitate another OPA189 + divider...or a 1:4 divider directly at the 10Vref.

Edit: Nope, modified the prototype and that wasnt it, as expected. Now what could be the cause...

[Kleinstein]

Finding the cause for relatively small INL effcts is tricky. 10 mV out of 10 V are however no longer a small effect. So I would exclude a thermal effect in the TDP resistors and also the OP-amps, unless there is something really wrong.  I may help to know in which way the nonlinearity happens, so a curve of the INL over voltage.
Another point is having an accurate schematics.

In the plan shown the voltage clamping parts may be an issue - not sure what they are and if installed at all.

[dietert1]

When i look at the AD7177 datasheet there is a maximum voltage rating of 6.5 V but in the text after "GETTING STARTED" they call 5.5 V the maximum supply voltage. Shouldn't be difficult  to reduce the 6V to 5.5 V for a test.

Typical 6.5 grade or better meters i tested all exhibited temperature coefficients between 1 and 0.1 ppm/K. Numerical compensation using a temperature sensor inside the meter works yet is always hampered by the different dynamics of the sensor. The HPM7177 with it's oven is a good example showing what to do: A ppm or sub-ppm meter should run inside an oven or a chamber. The power supply should be outside of the oven. Using a chamber requires a constant (synthetic) mains supply.
I am also trying to work out an accurate meter to run inside an oven. As Kleinstein wrote in his DIY multi-slope ADC thread: Using conventional circuitry at higher voltages one can beat those integrated converters. My own build inherits from the Prema 6048 meter. With about 2 W of heat output it needs a peltier oven (FPGA, 2x LTZ, LTC2386).

Regards, Dieter

[Echo88]

Changed the 6V rail to 5.5V as suggested, changed Vcm to Vref/2 = 2.679V and reduced the internal gain.
After trying to get it to work the whole day with several tests, measurements of the input stage and software modifications i now got it to work within +-10.7Vinmax with <=4ppm INL, without temp control, shielding and long wires between the used F5440B calibrator and the prototype. Good enough for now and +-10.7Vinmax (Limit: 5.358Vref *2 = 10.716V) are not quite 12V, but still enough overrange i think.
When the milled aluminium block arrives i can continue with the TEC control and add shielding to get more stable results. 
Schematic is attached in reply 157.

[dietert1]

Did you remove R18 .. R20 in the frontend? Is THJP some kind of transil?

Regards, Dieter

[Echo88]

Sorry referenced schematic was from my HPM7177 variant in reply 157.
The high impedance frontend idea isnt yet realized. Yeah R18...20 wouldnt be populated in the real implementation. THJP are thermal jumpers, i dont know of any symbol that would fit its function as a thermal bridge.

[Echo88]

I know i already asked the question already once in another thread, but i reworked the schematic suggestion for it:

As im preparing the revision 2 of my ADC-board with less bugs, the Vcm change and general optimizations im still unsure about the correct way to properly average the Gnd-sense of a quad LTZ/ADR1000-array.
Since the original HPM7177 is limited in noise by its single LTZ1000 i included the quad LTZ/ADR to be able to achieve the lowest noise possible as an option.
In my opinion each LTZ is coupled relatively hard to ground via their respective 0,1R resistors, with their respective reference current (about 5mA or so) + shared refdivider-current (5.8mA from 7Vref->5Vref divider + 5.4mA from 5Vref to 10Vref amplifier = 11.2mA max /4 -> 2.8mA per 0.1R resistor added).
Due to this hard ground coupling and the temperature stabilization of the pcb itself the references should be very stable and therefore their currents. This should prevent feedback or instability issues, so i guess the gnd-sense buffer OP can be omitted and all Gnd-sense-pins can be connected together without issue?

At roughly 500€ for a populated quad LTZ/ADR1000-array the circuit necessitates careful thinking. 

I attached the schematic of the proposed quad array, with both gnd-sense variants: averaged and buffered via OP U33 + RN11 or hard connected together.

[Kleinstein]

For the ground side one should be able to directly couple the ground sense and use current compensation for the ground drive side. So the ground drive would not be directly connected to ground be provide about the right current for each reference and than have the GND link with ground sense. So one could skip the extra buffer at the ground side.

One could also use the averaging resistors also to add some filter action - so have space for a film capacitor (e.g. 5-10 µF range) to ground.

The 7 to 5 V divider looks rather low in resistance - this would make the trace resistance rather critical and adds quite some load to U32.

Ideally one would also like to have the option to have access to the individual 7 V references, e.g. so see if one of them is drifting or showing popcorn noise.
I don't see a real need for the 10 V reference level. The 2.5 V Vcm could be obtained directly from the 5 V level or the same divider as the 7 V to 5 V.

For the start I would consider the quad reference overkill. The would be a part to populate only if everything else works. Even than 2 x ref. is likely good enough, especially if the ADR1000 is used. The main point should not be just lower noise, but a way to check for samples with excessive drift.

[dietert1]

In my design i have two LTZ1000 in series to implement a 14 V reference. I hope to avoid Gnd sense and current compensation by having a second ground plane AGnd that only takes the zener current of the lower reference and two constant current loads of the reference. Except some opamp inputs connected to AGnd all other (variable) currents get routed to the supplies, for example the heater currents. Near the LTC2386 ADC where AGnd becomes digital Gnd i have a 10 Ohm resistor. It should measure 50 mV in the end and if necessary it can become a short.
It should be useful to start with 10 Ohm instead 0.1 Ohm resistors and think about what happens. Maybe you want to change the four Gnd connections of the LTZ oven control.

Regards, Dieter

[Echo88]

Completely overlooked the possibility to use the 2.5V tap from the 7->5V divider, good find
Together with increasing RN5 to the 10k variant that decreases the gnd sense current greatly.
Since the whole board is temp stabilized and the references are not varying im unsure wether a gnd current compensation makes sense here, especially now that the gnd sense current is way smaller, thats why its not implemented yet.
Could totally understand it in a frontend with varying input voltage and therefore current into gnd through a range-divider though, like done in the 3458A were it would otherwise shift gnd.
Filter cap and access to each reference was added, thats certainly useful, especially for popcorn noise detection.
I thought the 10Vref was used for gain stability verification/calibration with the switches and therefore makes sense?
The quad refarray is indeed overkill, but since i have enough LTZs for it and wants to see just how low noise i can go with an ADC i want to try it here. I have two ADR1000, but they arent available right now normally and im cautious to trust them.
Drift intercomparison between the references can certainly be done, but only with more switches and im not yet implementing it in this revision, pcb space is already becoming scarce. 

Still need to do a noise simulation to see where that gets me, the shown values on the schematic are just for comparison.
The averaging network RN10 might produce drift issues when not all included resistors drift/age the same, might need a higher quality network than standard 4x1206 SMD-array?

Separate gnds to the respective ref-heaters makes sense, it avoids the substantial ~240mA through the gnd-planes, nearly forgot about that, thanks.
That will also require a supply redesign with beefier LDOs and better coupling to the cooler...always more work to do.

Schematic with changes is again attached.

[Kleinstein]

The resistors for reference averaging are not that critical. They only effect the difference between the reference - so something like 1-2% of the full reference. So standard SMD arrays (e.g. ACAS, MORN) can be good enough for this. No need to go really fancy here. The power loss is also rahter small and not much excess noise with only a small voltage.

The ground current compensation is from a fixed negative voltage to reduce the current flowing towards the central ground point. This also helps if the currents are constant, but with changes in trace restance and maybe connectors in the path if the reference are on there own small PCB.

The ADC (with dividers) gain check would ideally use the 7 V ref signal directly. An amplified 10 V signal would add an extral level of uncertainty with only minimal less noise. A 10 V level may be useful for ACAL with an external high voltage divider though - but no super stable voltage needed here. Another point may be a comparison with an external reference.

The reference schematics look a bit different from the standard circuit - may be the cern version. The use of dual supply OP-amps may be a bit tricky on start up and may need care with the power up sequence. I don't see an advantage compared to the standard circuit using LT1013.

[julian1]

Ignoring CM noise for a minute, I have a question about switcher ripple, because the potential for interaction with op-amp and amplifier PSRR is something I don't understand.

If a 100Hz mains transformer is swapped for a mains transformer + 10kHz low-noise dc-dc switcher, then a typical op-amp (eg. opa140) loses 40dB of its supply rejection function. eg. 100dB to 60dB eg. 100x PSRR.
A 7800 regulator is already fairly good (versus some LDOs) - offering 70dB ripple-rejection out to 10kHz.
Is there a way to think about the combination of op-amps and regulation, to identify the max ripple on the supplies (and therefore required post-regulation) - if the DMM needs >= 140dB for measurement?
Ripple is somewhat sinusoidal/symmetrical for push/pull, but I don't think it makes sense to assume linear/cancelling contribution in the case of supply rejection (consider also AZ frequency and line-synchronization and harmonics).

3458a already has cap-multipliers with 78L/7900 right down at the AC line frequency ( RC=200R/15u=53Hz ) even though it uses a mains-transformer, and there are no dc-dc switchers creating high-frequency ripple.
Although AC measurement ranges would be expected to be more sensitive than DCV, with better AC supply rejection needed.

A resistor is low capacitance, so using RC or a RC based capacitor-multipler is always possible after the dc-dc switcher, and before the linear regulator.

[julian1]

The size of electrolytic caps surrounding the coax transformer of the DMM7510, suggests the operating frequency may even dip down into the auditory range.

Edit,

On another note - just using a mains freq transformer, may yet work, holding the advantage of being a simple and proven design.
The difficulty is coming up with a feasible and practical construction. Here one could use the same trick, placing the primary-secondary windings at opposite ends of a toroid, and using copper tape - as a sleeve and for screen/guard.

I tried with 300 turns on a high-AL NC toroid, trying to roughly match the spec of a similarly sized laminated iron toroid.
With 15H, it's ok at low-voltage, but saturates with 250VAC. So at a minimum it could work as part of a two transformer solution.

[Ole]

Does anyone know the current draw on the 3458s + and - 18V Rails during normal operation?

[Kleinstein]

If the layout is correct and not ground loops / bad ground point the ripple rejection of the regulator and amplifiers just mulitply or add as dB values. However there is a chance to have a not so ideal layout. Another point is that capacitor ESR may contribute to the ripple - so the rejection for the regulators can depend on the details.  With relatively low power one can use relatively large capacitors to start with and also possible added LC filtering for a higher frequency version. Especially push pull stages may not run with a sine, more like a square wave and possibly less ripple.

The simple pre-stabilization (cap mulitplier) can be an option, though it looses some 0.5-1 V.

With a toroidial transformer and windings only on opposing ends this may increase the magnetic stray field of the transformer. It is a balance between capacitive coupling and magnetic coupling.
For low coupling transformers there is also the version with a normal primary all around the core and then the secondary with maximum distance through the center of the core, either one side or as a figure 8.
This way at least the magnetizing current does not produce an extra stray field and the core usually is conductive anyway.

[julian1]

I have a board which fixes some issues that interfered with testing.
Since the opportunity was there, the input section has also been updated/improved based on comments and suggestions.

Perhaps more important, there is now support to run automated self-diagnostic/unit tests, which are nice and quick to iterate through, and that don't require ad-hoc code deployment or instrument setup.

Being able to route precision voltages around the board using the board calibrator/ dcv-source, works really well.
And getting the test setup vector/ as well as expected-behavior managed programmatically, and locked down in code, is progress of a kind.

It is an interesting property that the input conditioning may be able to measure it's own leakage, and switching charge contribution,
And with different input dc biases.

With the tests in place, the analog switches can be progressively added, and change observed.

test method,
test05  charge cap to +10V. hold 10sec for cap DA to settle, then turn off/float primary himux switch inputs, and observe voltage. measurement is taken from boot buffer/opa140 output.
test06  same except use -10V dc-bias.
test07  same except 0V dc-bias .
test08  charge cap to 0V/agnd, let cap DA settle. Put a +10V test on primary himux input (pin 5), while it is turned off.
test09  same except use -10V on pin5.


- with two hi muxes (U413, U402) fitted.
test05    -0.5mV/10s. = -0.5pA.
test06    leave 5mins for DA to settle.  +1.7pA. 10mins. the same.
test07    5 mins for DA.   250uV/10s. +0.25pA.
test08    300uV/ 10s = +0.3pA.
test09    300uV/ 10s = +0.3pA.

conclusion - with just the adg1208 muxes, leakage is very controlled.


- add TI sn74lv4053 (U412) precharge switch, muxing boot.  AZ switch (U414) is *not* fitted.
test05    +22pA.  +21pA,  20pA.
test06    +23pA.  +25pA.  25oA,
test07    +17pA.  +20pA.

conclusion, a bit higher than might be hoped for,


- same test, as previous test except 4053 muxing signal.
test05    +20pA.
test06    +25pA.
test07    +22pA.

conclusion - 4053 switch position doesn't matter.


the 47p caps (C421, C428) are mlcc, and therefore a bit suspicious, but the voltage difference across them is very low.
board are well cleaned.
the copper guarding looks good to me.
the sn74lv4053 is salvaged from other boards, but that's because it had been demonstrated to work well.

I will try to add the previously shown AZ test modulation into the test suite- but am not sure charge-injection at ordinary AZ freq, will be evident above the leakage. I should probably re-review the previous 4053 tests, already posted to this thread. 

[Kleinstein]

The leakage currents without the 4053 fitted look really good. So the ADG1208 really seem to be good.  Even 20 pA with the LV4053 are not that bad, though we had hoped for less.

I don't understand the purpose of C430:  normally the signal to control the 4053 type switch should be a clean logic signal and not slowed down. One could even consider having an extra schmidt trigger like HC1G14 in front of the 4053 switch.  Depending on the control signal, the signal to the 4053 may also be a bit negative so that chip interal diodes start conducting despite of D409. This may lead to extra leakage. The input leakage my also be different with different inputs used.

[iMo]

I would pass all logic signals into the analog chips via 50-100ohm resistors..

[julian1]

C430 is my misunderstanding of an earlier comment, that this signal should be slowed.
I think I experimented in the past with a schottky at D409, to reduce possible negative voltages on the 4053 input protection diodes.
It is probably worth checking again.

For source-termination resistors, they may be an idea.
There is a little ringing on digital signals and 10-90% rise time is fast - 2ns measured with passive probes .
But the presence of quite a few control signals make it look more complicated than it is. 
And there is actually very little going on (by design) during normal DC sampling.


Does anyone know the input bias current of the 3458a (or other modern HP/Keithly) meters, on 10V/high-z range, with AZ turned off?

[iMo]

I would pass all logic signals into the analog chips via 50-100ohm resistors..

The logic signals are noisy even when stable at log0/1. And when chasing nVolts slowing the fast edges is good thing as well (the resistor's RLC and parasitic capacities create a low-pass).

[Alex Nikitin]

Does anyone know the input bias current of the 3458a (or other modern HP/Keithly) meters, on 10V/high-z range, with AZ turned off?

Here is what I have measured in the past for HP3458A and HP3456A (horizontal axis in Volts, vertical in pA), using  Keithley 617:

Cheers

Alex

[julian1]

I was trying to work out why leakage somehow got overlooked from the previous 4053 tests.
Those circuits had the possibility to trim the bootstrap/-ve rail offset relative to the input signal.
This was done with the intention to trim pmos/nmos charge-injection balance, but showed that switch leakage could be trimmed as well.

Looking at the data for lv4053, using ~= +-25mV offset, is enough to bring leakage into line.
So it is possible an offset had been inadvertently / accidently added when the measurements were done  ( data shows <1pA ).
Or maybe part variation, although that seems unlikely.

So it's possible to revert back to that circuit.
Or select another manufacturer's '4053, with lower leakage specs, but higher charge injection.
Although, after soldering, I notice there may be some some temperature dependency for 4053 leakage also.

Alternatively, Kleinstein's original proposal using discrete jfet/fet, and complementary driven capacitively-coupled charge-balance, with a low pF. trimmer cap, was nearly working in tests.
It appeared there was just a pcb layout issue, so that the control signal appeared to also be getting coupled to the signal. The advantage of the trimmer cap is that it can trim additional parasitic capacitance.
And it's probably a simpler circuit.

[julian1]

To summarize, I doubt I mis-measured the boot offset in previous tests - since it was some effort to generate - requiring a dedicated extra op-amp.
But it's hard to overlook that +-25mV offset could trim 20pA of the sn74lv4053 leakage, which is in the region of what the new tests show.
So perhaps there is something going on there.

Another possibility, might be to use both positive and negative bootstrap rails.
Then any 4053 leakage could be trimmed out with a resistor to the rail.
At least for the non-temperature dependent component.
But that seems a bit ugly.

The nice thing about jfets is that low-leakage (j201, 4117) comes out of the box as a datasheet value.
Then the charge-injection just needs to be balanced, with an inverted signal.
It just needs a good layout, whereby the very small trimmer cap is working in the range where it is effective.

Anyway doesn't matter for the moment, it's probably good to get the az modulation fixed up again.

[Kleinstein]

The leakage current from diodes and other semiconductors is quite temperature dependent. So the compensation is more from a diode than via a resistor. With JFETs it is common to have a dioded connected JFET towards the positive side as a compensation for a JFET switch turned off (it is actually 2 switched, as leakage it to both sides).

The -25 mV supply can be about enough to get the leakage of the neg. side diodes to about there saturation value. The effect can be quite nonlinear.

At least for an initial test the 20 pA leakage is not that bad. AFAIR the high end meters like 3458 and Fluke 8588 call for < 20 pA and other meter often only specify < 50 pA for the inputs.

[David Hess]

There are some rare JFET input integrated operational amplifiers which used input bias current cancellation, but they could rely on the matching of integrated JFETs.

It might be worth looking up the old ways of doing external input bias current cancellation.  Tektronix also did input leakage cancellation of JFET input stages in a few of their vertical amplifiers.

[Ole]

I do have a few ideas on cancelling out the Gate Leakage current on JFETs,
the easiest one, in my opinion, would be similar to the bias cancellation circuit in the Datron 1281.
Though that design has the problem of, if I am reading that correctly, the tempco of the leakage.

I have added a concept for cancelling the Gate Leakage current, though this would work best with close thermal coupling between the primary JFET and the Compensator JFET. Though this too would need to be carefully measured and adjusted to work ideally.

On another topic:
Concerning the AZ-Cycling I had the idea to utilise a 8:2 MUX (MAX329 or MUX36D04) with four phases, two of which being Zero Phases. Though this would be aimed at a differential front end.
The MUX36 could be problematic concerning guarding as its a TSSOP Part.

[Kleinstein]

Normally the gate current of the JFETs is not a big problem, it is low, at least at room temperature. Like with normal diodes the leakage current is not very dependent on the voltage (except for very low and very high voltages). So the obvious way to compensate if the leakage of another gate to the other side. As this is leakage to source and drain it would compensate for 2 JFETs switched off.
A nice point is that the temperature dependence is expected to be similar.

With just a single JFET one may not have to compensate and it depends on other bias paths if and how many diode connected JFETs make sense for compensation.

[David Hess]

Take a look at how external input bias current cancellation works using a second operational amplifier in the same package.  This comes up in single supply parts because single supply input stages cannot include input bias current cancellation, but it can be added externally with a second operational amplifier in the same package.

Since the input bias currents match for parts in the same package, the second amplifier is configured as a follower with a high feedback resistance which creates an offset proportional to the input bias current, and then the same resistance between its output and the input to be corrected adds the needed current for correction.  For scaling the feedback resistance could be made variable.

Tektronix implemented input bias current cancellation on their 7A22 differential amplifier using a pair of thermisters with one controlling offset and one controlling gain, so I guess there were two effects going on, or maybe that was for linearization.

[julian1]

Still exploring cmos switches for a bit,

Briefly for sn74lv4053a one difference with the previous tests - is the zener used to set the boot supply rail.
but tests show that a bootstrap supply rail between 4V to 5.5V doesn't matter much for leakage or charge injection.
Also tried another sn74lv4053a, purchased a few years apart from the one used for initial tests, but with the same result.
So i am not sure how to explain the discrepancy with previous test results.

Running az modulation. all muxes fitted.
DC accumulation on 10nF/ over 10s.

test14.
sn74lv4053a
+10V dc bais
1000nplc/off   20mV. 18mV.
100nplc/2s     17mV. 17mV.
10nplc/200ms   21mV. 22mV.
1nplc/20ms     35mV. 73mV.  70mV.   large measured difference. odd. but was definltey there.


But max4053 looks a lot better,
I almost wasn't going to bother re-testing it, based on past resulsts.
Identical setup as above - accumulation on 10nF/ 10s.

max4053
+10V dc bias.
1000nplc/off   0.3mV. 0.5mV
100nplc        0.8mV.
10nplc         3.8mV.   3.6mV.
1nplc          30mV.   28mV.

max4053
-10V dc bias.
leave five minutes for +4.5mV/10s. cap DA to settle.
1000nplc/off   2.5mV  2.8mV   - oct 8  2.3mV.
100nplc        3.0mV. 3.3mV   - oct 8.  2.3mV
10nplc         5.6mV.  5.7mV  - oct 8. 5.2mV.
1nplc          30mV   30mV.   - oct 8  29mV.

max4053
0V dc bias.
1000nplc/off   0.8mV.
100nplc        1.0mV.  1mV.
10nplc         3.8mV.  3.6mV.
1nplc          28mV.

leakage is more controlled -  <1pA for +10V and 0V, and <3pA for -10V dc-bias.

for charge injection
ie. 1nplc == 20ms.  10s/0.02s == 500 cycles.
this is 30mV / 500 == 0.06pC .
if I have the units correct, through full-cycle switch.

The above tests were done with the azmux held off, with only the pre-charge switch switching.
this would eliminate/isolate any leakage through the amplifer input jfets (if fitted) .


test15.
When the azmux also changed to for normal sampling between PC-OUT (S1) and LO (S6), the result is similar.

max4053
+10V dc bias
1000nplc/off   1.0mV  0.2mV.
100nplc        0.2mV  0.2mV
10nplc         1.0mV  1.2mV
1nplc          20.5mV.  20.5mV

max4053
-10V dc bias
wait for DA.
1000nplc/off   3.8mV. 3.2mV    maybe a little DA still from +10V test.
100nplc        2.5mV
10nplc         10mV. 10mV.
1nplc          56mV.  55mV.  56mV

max4053
0V dc bias.
1000nplc/off   1.3mV 1.2mV.
100nplc        1.8mV
10nplc         4.8mV
1nplc          38mV. 37mV.

Edit. add more data

[Kleinstein]

The data with the max4053 look good.
At least for 10 PLC mode and likely still with some 5 PLC the charge injection is good. For 1 PLC it may be an issue in a few cases, but would be OK too most of the time.
I am a little surprized that the charge injection / charge pumping depends so much on the bias voltage. The idea with the bootstrapped supply to the switches was to make the charge injection part at least independent of the external voltage. There may be an effect of the waiting time for the charge injection due to some DA or similar settling effect at the MUX / amplifier.

[julian1]

The charge-injection is is reasonably independent of dc input voltage, with just the PC-switch.
eg. at 1nplc.  between  28mV - 30mV from -10 to +10 V.
This indicates the bootstrap switching part is working,

But otherwise, I agree there appears to be a sensitivity to dc-bias when both switches are used together,

at 1nplc,   56mV (-10V) / 20.5mV (+10V)  =  a 2.7x difference
 

There may be an effect of the waiting time for the charge injection due to some DA or similar settling effect .

The previous tests used a 500us precharge phase.
When the precharge phase is increased from 500us to 5ms.  sensitivity to dc-bias is reduced.

  -10V bias.  1nplc.   38mV. 38mV.
  0V   bias   1nplc    30mV. 30mV.
  +10V bias   1nplc    25mV. 25mV.

  spread = 38/25mV = 1.5x difference.

So your insight/intuition looks right.

I think the magnitude of the charge-injection may yet be improved by following the original input discrete jfet scheme.
With a complementary signal, and small coupling cap/trimmer.

This could use a (maybe inverted) pc-switch signal, or az-mux or - perhaps a third control signal for more control.
but I would need to try think about what it would look like.

Edit. might be worth trying to bodge a 3pF trimmer from the pc-switch ctrl to the input node, just to see what happens.

[Kleinstein]

Adding some small capacitance to compensate some of the chanrge injection also with the CMOS switch may be an option (if the polarity of the control signal is right). Instead of a trimmer one may also use just a piece of wire getting close. This would more like a 0 - 1 pF adjustable cap.

A 500 µs precharge time is already not that short, but may be still OK. From another thread (3456 repair) I just saw that the HP3456 seems to use some 200 µs for the precharge phase.
For the difference in the input bias it is not some much the ratio, but the difference. With the short precharge time there are some 36 mV, corresponding to 36 pA average input current comparable to some 550 Gohm (looks negative ?) at the input. So it is not great, but also not bad. Still there would be the option to use a slower cycel when needed.

p.s.:
 I just got an idea for what could cause the extra current with a short pre-charge phase:  open, unused input at the MUX would be weakly coupled charge reservors that can act like DA ar a RC elelemt on the order of 3-5 pF and a few Tohms. So unused channels may want a defined (e.g. GND potential).

[julian1]

Some more experiments,

test15.
revert to baseline. 500us precharge.
max4053, 1nplc,
+10V   21mV,  21mV
0V     37mV.   37mV.
-10V.  55mV.   58mV.

I felt for-sure that tie-ing bootin guard (currently floating) to gnd would do something, by changing the capacitive loading on azmux out.
There is quite a bit of copper surface area and proximity. (this guard needs to wait for the amp to be populated to drive properly).
BOOTIN tied to gnd. also pin7 azmux instead of being left floating.
But, the result is the same.
+10V.   20mV
0V      39mV.  39mV.
-10V.   55mV   56mV.

remove cap C430. slowing pre-charge switching. - the same.
+10V    20.5mV.
0V.     37mV.  39mV.
-10V.   56mV.

tie-off unused azmux inputs (dci-lo, 4w-lo) to gnd. All azmux inputs are now defined.
no difference
+10V  20mV.
0V.   39mV.
-10V  57mV.

it is impressively stubborn, even to try and shift in a bad way/direction.

                       
Perhaps it's worth describing the algorithm. The guiding motivation is that whenever the azmux switches, the pc-switch should mux BOOT to protect the input signal. This gives the following sequence,

1. init/reset - pc switch to boot (to protect signal)
2. az mux switch lo -> hi (precharge phase, 500us)
3. pc switch - to signal. take HI measure.
4. pc switch to boot (to re-protect signal).
5. az mux switch hi -> lo.  take LO measure.
   goto 2.


I still think maybe it is not that bad -  if the magnitude of the charge-injection is reduced, it will also trim the difference.
But perhaps max4053 by itself, is still not the quite the right part.
         

[julian1]

max4053 seems more sensitive to the supply rail. Increasing the supply from 4V to 4.7V  increases charge-injection over baseline. 

test15. 1nplc. 
+10    31mV.  31mV.
 0       51mV.  51mV.
-10V  71mV.  74mV

The datasheet is characterized down to 3V single-supply. and suggests it can operate as low as 2.7V.
If I can find some lower voltage zeners, I'll try reducing the supply rail voltage.

[Kleinstein]

A reduced supply is indeed an option. In many cases the charge injection goes down with lower supply, For a more normal DMM the higher R_on not yet a problem.
Instead of a low voltage zener, one may also use a white / blue LED. The low voltage Zener diodes are often not that good (high TC and differential resistance) anyway.

It is interresting that a higher supply especially increases the charge injection when the input voltage in negative.

A parameter that one could try changing is also the small capacitors at the switch. Charge injection also slightly depends on that capacitance.

[julian1]

With max4053 supply at 2.70V.

1nplc.
+10V.      -12mV.  -12mV.            note negative .
0V        7.5mV.  7mV.
-10V.      26mV   27mV.

leakage is still controlled.

+10V   1000nplc/off -0.4mV
-10V  1000nplc / off 3.8mV.

But it is still a 26 - -12 = 39mV. difference. So the charge is the same, just the offset changes.

[Kleinstein]

The difference between the +10 V and -10 V case may not depend that much on the switch for the precharge switching. The max4053 does not see much of the change in the voltage, only maybe a different size current peak from charging the amplifier / ADG1208. The current peak may be effecting the supply voltage for the may4053.  Getting to some 7 pA input bias at 0 V is good.
Getting a more positive drift at a negative voltage means a positive input resistance (going back the zero), in this case on the order of 500 Gohm. This is OK, but not really great and odd that it depends on the time spend in the precharge phase.

The change of the input bias with input voltage may well be more a thing of the ADG1208 or the amplifier. These parts see the difference in the voltage. A small part (independent of the PC time) may be just leakage without the bootstrapped guards. Another part could be lossy capacitance and thus delayed charging of that capacitance. At least a part of this could improve when the bootin part is working.

[Kleinstein]

There is about an 18 pA change in the average input current from 0 V to 10 V. With some 40 ms for an AZ cycle this is some 0.72 pC per cycle.
One mechanism is lossy capacitance at the mux and amplifier input. FR4 material has a loss factor of some 2% so it would need about 40 pC or 4 pF at this loss level to get the 0.72 pC of charge flowing at the wrong time (e.g. with some delay). 4 pF of parasitic capacitance on the PCB and MUX chip package sounds plausible, depending on the layout. Ideally the driven guard traces at the mux and amplifier could at least reduce the effective capacitance.
Besides loss in the dielectric material itself there is also a chance to have partially isolated somewhat conductive islands (e.g. dirt spots on the surface) that can cause some "dielectric" absorption.

The current state with an effective input resistance of some 500 GOhm ( 10 V / 20 pA) is not that bad for a DMM. With a slower AZ cycle (e.g. 10 PLC) the change in the input bias goes down (nearly 10 x) and thus even higher input resistance. The inverse (= conductance) may be the better parameter to specify as conductance of parallel paths (e.g. leakage at the terminals, leakage at the input mux, charge pumping) adds up.

Not sure how other DMMs react with the 1 PLC mode - the 3458 prefers 10 PLC for highest accuracy and the specs are only for > 10 GOhm (not sure which mode) and thus not very sharp. I would not be surprised to also see considerably lower input resistance with 1 PLC than with 10 PLC.

[julian1]

The distance from azmux output trace to input amplifier jfets is short - only a couple of centimeters.
It is a six layer board, with two cores, and the trace is sandwiched on a dedicated copper layer between the two core (not prepreg) layers.

However the trace does cross a bunch of star grounds and some digital signals on other layers.
It is a weak point, but I considered it acceptable since there are no dynamic/changing voltages during sampling operation.
(the remedy if necessary - is to move the amplifier jfet placement).

But these gnd traces would definitely add to capacitive gnd.
Still it was surprising that manipulating the BOOTIN guard potential which has very close copper features, did not change behavior at all (good or bad).


At least it should be easy to test the loading - it is just a matter of lifting the azmux output-pin.

Edit. english
Edit 2. core not prepreg.

[Kleinstein]

Already as is the input resistance is not bad and with 3 PLC one would likely be already > 1 TOhm.
Chances are the curves shown earlier by  Alex Nikitin for the 3456 and 3458 are for 10 PLC as the default setting. I would not be surprized if at 1 PLC they would also show comparable or even more input current than the current PCB discussed here.

With a multilayer one can get shielding, but of cause the capacity also may get relatively large with only the thin layers.
A big difference may come up when bootin is actually driven as a copy of the input signal. Any other fixed level will not make much of a difference, though a floating copper part could be bad.
Driving bootin may be one of the next steps to try.

A relatively short distance from the mux to the amplifier is good - for some reason the old 3458 has quite some distance there.

A reduced supply voltage may also be an option for the LV4053 - though I would not unsolder the max4053 for this.

[julian1]

Ok, this looks more promising,

test15
baseline max4053, 2.7V supply. 500us precharge. 1nplc
+10V        -12mV
0V          7.0mV.
-10V        26mV.

identical - except with the azmux out pin lifted (U414,p8).
1nplc
+10V   2.6mV. 2.6mV
0V.    5.0mV. 5.0mV.
-10V.  8.5mV. 8.4mV.

No components are populated at the end of the short azmux-out trace.
So this suggests pretty strongly a layout/pcb effect - coupling, board DA, or guard or similar.
there's a lot that can improved here, but the bootin/guard is the easiest and probably should be addressed first.


Leakage may also be slightly better - suggesting pcb leakage > adg mux leakage.
perhaps still some DA mixed up in the result too, with a 5min settle-time.

leakage 1000nplc/off
+10V.  -0.2mV.
0V.     1.7mV. 1.0mV. 0.1mV.  ??
-10V    2.2mV. 2.1mV.

[julian1]

Reviewing the pcb again, and there is single control-trace for the azmux (that is used), routed about 1.27mm over the mux-output.
it is separated by fr4 core, but still a good candidate for the issue.
using a wire bodge from mux-out instead of the pc btrace should be a workaround.
Edit. now i am not sure. there is also a middle layer copper fill that should mostly shield digital signals running on the bottom layers.

[Kleinstein]

If one has reasonable guard traces from bootin, chances are this can suppress much of the capacitance and losses in the PCB. So chances this would be than good - as is it is already good enough for most uses, especially as the current gets smaller with 10 PLC.  The case with AZmux out lifted has some 6 pA of difference from -10 to +10 V and thus some 3 GTohm of input resistance. The very few cases that need a near electrometer perfomance could use the OPA140 input buffer in non AZ mode and thus some 1-2 pA of bias and 10 Tohm range input resistance.

[julian1]

Driving bootin may be one of the next steps to try.

Agreed. Also, it brings the discrete jfets of the amplifier into play. 
 
I've populated the amplifier in a simple configuration - jfe2140.  5V6 zener.  tle2071 op.

An air-wire connects mux-out to the amplifier input.
The board is *not* well cleaned due to a few bodge wires that limit access.
But this also provides a good test of guard effectiveness.

- with bootin tied to gnd.

leakage 1000nplc/off
  +10V    -0.7mV. -0.8mV -0.8mV. 
  0V      +1.1mV +1.1mV
  -10V     +5.4mV +5.3mV

charge 1nplc
  +10V    -7.6mV. -9.2mV -9.3mV.  -8.9mV
  0V     +6.9mV +7.2V
  -10V    +22mV +23mV.


- identical except bootin driver op added.
(this copies the voltage on the copper fill under the lifted mux-out pin, and surrounding the amp input air-wire connection, as well as other sensitive amplifier pins)

leakage. 1000nplc/off
+10V    +0.7mV. +0.7mV.
0V      2.2mV.  2.1mV
-10V    5.2mV.  5.3mV

charge 1nplc.
+10V    -0.9mV  -1.0mV.
0V      4.9mV  4.8mV. 4.8mV.
-10V    +11.2mV  11.3mV

So it looks like bootin is quite effective at reducing the charge difference at different dc inputs..

[julian1]

I added the dcv ranging (100mV,1V,10V,100V,1000V) components (hv divider etc) and functions.
It work wells with the amplifier in a simplified non-compound configuration.

Also, look to have discovered the issue with the 4053 precharge-switch behavior compared with prior standalone tests.

The current-source (1mA) for the bootstrap zener terminates at the 10R (R405) included as an option to unload the capacitance of the guard fill.
But given this is after the op feedback node, a 10mV offset is created across the resistor.

So the precharge-switch was switching between input and boot but with a small 10mV offset.
This was not clear in simple tests, but easy to see on a scope at the amplifier output with gain=100x (why the hell is there a 1V offset during the pc phase?!!).

Changing R405 from 10R to 0R makes boot=signal.
But after fixing this, the previous good trim for the max4053 is upset (too negative even at low 2.7V supply).

However, charge contribution is more consistent with previous test data.
And the bad leakage from lv4053 has disappeared.

With a 0V/BOOT input offset relative to the -ve supply rail,
- max4053 adds negative charge.
- lv4053  adds positive charge.

The trick of trimming charge by adjusting the supply voltage works for both max4053 or lv4053.
But there is not quite enough adjustment headroom/range, to null the charge offset for a 0V input relative to the negative supply rail.
eg. max4053 is still too negative at 2.7V supply.  and lv4053  is too positive at 5.5V supply.


But it is possible to compensate with a small cap from the precharge signal to the output of the pc switch.
And signal polarity, and switch phase, can be made to cancel the positive charge offset of the lv4053.

anyway, I didn't want to put extra time into this, but it is more clear now what is going on, and perhaps interesting enough to share.

- With sn74lv4053.   at 2.7V.   10p. compensation cap.
- use lower supply voltage for lv4053 to minimize leakage, and rely on cap to trim charge offset.
     
leakage  1000nplc / off
+10V    -0.9mV.  -1.5mV
0V.     -0.5mV   -2.2mV
-10V    0.9mV    1.9mV.

charge 1nplc
+10V    -6.1mV  -5.8mV.
0V.     -2.6mV -2.4mV
-10V    +5.8mV  6.2mV

[Kleinstein]

Getting good leakage with even the cheap SN74LV4053 is nice.  A lower supply is usually no problem, unless one wants super low noise for a more nV meter like version. This would anyway need a few more changes to keep the resistance and thus noise in the path low.

For the charge trim there would be not only the overall supply voltage, but also a possible split in a positive and negative supply relative to the input / guard.
10 pF of capacitance for the compensation of the charge injection looks large, but if it works why not. Much smaller capacitors are a bit tricky anyway.

The leakage current is really low (1 mV drop over 10s with a 10 nF capacitor means 1 pA).  So the 1 PLC case would between +6 and - 6 pA.  That level of leakage is likely a mix from the input MUX, the pre-charge circuit, the 2nd MUX, the amplifier and possible PCB leakage. With the switches this is well below the typical specs and things can vary with units.

A point that may be interesting is how much switching spike is visible at the input  - not so sure how to measure, maybe just the scope input directly ?
The older DMMs (e.g. 3458, 3456, K19x) seem to use relatively slow switching and this one can expect relatively broad pulses. Here the switching is fast and the current pulse starts out short and is than somewhat broadend by the RC filtering.

[julian1]

Added some more functions,  aper, nplc, fixedz, azero off mode, and a non-az. 'electrometer' mode using the boot op.

For observing switching from the input side, I hooked up the input to a 10x probe - so a 10Meg input-impedance.
the mains 50Hz mains is ever-present on my probes.
But what is worse is that the 10p comp-cap (switch-node to output-node) really pushes/smacks around the signal.

It is possible to change to the original scheme with a compensation-cap from switch-node to input-node.
And using lv4053 (unlike max4053) this also works.
Experimentation shows an air-capacitor formed by two wires crossing - shifts the charge-offset about 1mV.
And a 3.5pF trimmer, set to 2.5pF according to an lcr meter shifts about 5mV.
With lv4053 at 2.7V it there is still about 7mV more trim needed to null the offset.
So this could be reasonably achieved via a combination of fixed-cap and/or trimmer.

But with this circuit arrangement too, the cap really pushes the signal around a lot.

Perhaps the most interesting case - is when no cap is fitted.
Here, the switching effects are negligible and very hard to observe.
There is some pertubation that can be seen at the amp output with G=100x.
And this also matches what I see with 34401a input, with the same test setup - it's very hard to see switching artifacts - maybe just a bit of non-linearity impressed onto the mains hum.

What is puzzling, is that I kind of expected to see the 4053 cmos switch also push the signal around through a half-phase transition (the comp-cap is only meant to offset this).
So maybe the cmos charge-injection is just really low, and the below observable limit.

And perhaps the accumulation offset on the 10nF, is some factor other than switching charge-injection.
Perhaps it is due to Vos of the boot op, or asymmetric leakage with voltage spiking.
If this other factor is removed then perhaps no cap is needed.

[julian1]

Huh, it looks like the forum image upload really does reverse the intended image order. 

The other thing I was thinking about, would be a kind of phased coupling approach.
So an independent ctrl node could deliver a transition in one polarity into the output when the precharge-switch is muxing the signal-node.
And then dump the opposite polarity when the precharge-switch is muxinig low-impedance boot.

On another point, perhaps the complexity of introducing a dac in the 3458a is for ratio-metric switching - where hi-side jfets need to be switched as well, and charge-injection compensated.

[Kleinstein]

The spike with the 10 pF cap in place looks quite strong, while the case with no extra cap looks really good - essentially only the 50 Hz hum. To get a better signal one could maybe use direct coax connection to the scope - so no probe and largely shielded.

Are the tests for the input spike done with the 10 nF capacitor connected ? I guess not as this capacitor should stretch the spike much more.

The 10 pF capacitor was shifting the average input bias, which can have many other reasons than charge injection. So I think the logical point is to skip the capacitor. The case with 1 PLC had a drift rate of some 5 mV/10s and thus some 5 pA of input bias, which is totally acceptable. Some 2 pA are also there without switching (e.g. the input mux and OPA140 buffer input). If reelly needed one could consider compensating the input bias in a different way, e.g. offest to the precharge signal (like in the 34401, 3457,...).

The complexity in the charge compensation of the 3458 is because the switching is with JFETs. The CMOS switch chips have quite good chearge compensation build in from using the N and P channel. I don't know if the 3458 uses the DACs with fixed settings (determined during a factory cal run) or if they are adjusted depending on the voltage or maybe signal source (e.g. different for the HV divider or shunts). The 2 DACs could just be a fancy substitute for 2 pots in the 3456.  For the ratiometric measurement I see not charge compensation in the 3458 - this would get the full spikes from the input JFETs. This would also apply to the new front end with the MUX before the precharge part.  To avoid this one would need a precharge circuit for every critical input (e.g. 2 voltage inputs and the HV divider) and could drop the MUX before the precharge part. This is how I have it planed and with the LV4053 this also looks sensible. 

[dietert1]

The image with the amplifier output is nice. I think one can see the two precharge phases. Though it's somewhat surprising that both of the precharge phases show the input signal on the amplifier output.
Then there are two spikes of opposite sign when leaving the autozero phase, the first one very short, the second one more like the input side spikes of the compensation cap tests. As far as i understand charge injection depends on those asymmetries
- Autozero phase on and off
- Precharge phase on and off during autozero phase off.
One would need a little more effort the generate a "perfect" compensation signal.

Regards, Dieter

[Kleinstein]

The 2nd "pre-charge" phase for the step from the input signal to the zero reading is not really a precharge of the amplifier, but more an isolation of the MUX switching. The ground path does not really need a pre-charge. Naturally the off switching of the MUX is much less intrusive than the on step. So this part is naturally less intrusive. There still seems to be a little offset / shift.

There us a chance the at tiny bit of wire capacitance (e.g. 0.1 pF range) may be about right to compensate the small visible spike when switching from the precharge to the actual input signal.
This spike would be the part to compensate with a capacitance, not the net contribution to the bias.

For the charge injection we have to distinguish between the net charge effect for a switching cycle, like here with the DMM input and the charge injection in the switch specs - that is usually only the switch off part, like relevant for the S&H stage. Besides capacitance to the control signal also the capacitance to ground (or the switch supply) can effect this charge injection.
The net contribution to the bias depends on the symmetry between the peaks for switching on and off.
The charge injection on switching a CMOS switch off depends on the symmetry in the impedances.

[julian1]

The waveform pics are all use the ordinary dcv ranges. 
The accumulation cap (C410) reserved for timed tests is not engaged.
At 2.7V, the measured in-circuit rds-on is still really low - 25R for lv4053. and 170R. for max4053.

i agree the size of the cap needed to compensate the '4053, based on waveform pics, makes it mostly infeasible.
charge-injection is already well compensated due to nmos/pmos design, and by the bootstrap that keeps input constant wrt the supply rails.

But there is still an apparent leakage/bias that shifts the offset seen in the 10nF accumulation cap tests.
And this has some dependency with switch frequency.
So it is not possible to compensate with say a fixed 100G resistor to the bootstrap rail.

The other way to manipulate this is by changing the boot v input offset slightly.
So similar, to the original mechanism, to trim nmos/cmos contribution using the dedicated extra op-amp.

But there may be a simpler way - by intentionally creating an offset on R405.
ie. to trim in the range of the Vos of the opa140, R405 could be a 0805 0.1R current-sense resistor.
So with 1mA source, V=IR, -> 100uV.

And the opposite polarity (if needed) could be done with a negative current-source terminating at the boot node.
For a negative current-source,  adjustment could be made -0.1 to -2mA, via the negative-source emitter leg resistor (even a trimpot), to allow trim on R405 ~=  +-1mA.

We just need to make sure other parameters are not disturbed - particularly constant leakage, which seems to be an issue for lv4053.


I also need to check that the FP5V supply is not dropping when the 4053 is switching fast, since we know the charge-offset has a dependency to the supply rail.
The buffer npn Q411 was removed, in order to get the 2.7V with the zeners I had on hand.

[Kleinstein]

The input current is already pretty low (e.g. 5-10 pA range) even with 1 PLC AZ cycle. If really needed one could use a little longer integration at a piece. I see no real need to compensate for it. This is within the specs for the high end meters (e.g. HP3458, DA1281, Fluke8858).  The input current with 1 PLC is pretty much on par with the curve for the 3458 in this post:
https://www.eevblog.com/forum/metrology/analog-frontends-for-dmms-approaching-8-5-digits-discussions/msg5087488/#msg5087488
Chances are the data were for 10 PLC as the default speed.

If one really wants to compensate such a tiny current, one could consider a little light to a low leakage diode and there are a few glass case types. It does not take much for a few pA.
Light can also effect the bias on some chips in a plastic case, especially the thinner ones.

To generate an offset for the pre-charge voltage one could use less current a a bit larger resistor. It is gneral a good idea to keep the power low to reduce thermal effects. Thermal fluctuations in combination with thermal EMF or similar can be limiting the LF noise.

[julian1]

To show the data for lv4053 again, with compensation caps removed.
I agree, the 10nplc case is good. 2.7mV to 6.7mV.   So. 2.7pA to 6.7pA input bias current, across the +-10V input range.
Ideally, the offset of 13mV for 1nplc at 0V dc-bias could also be nulled.
But not if it adds a lot of complexity.


input dc-bias
10V
  1000nplc/off    1.8mV. 0.6mV.   0.1mV.  1.4mV.   varation recorded depends on switch phase.
  10nplc          2.7mV. 2.7mV    2.7mV.
  1nplc           10mV   10.2mV.
  0.5nplc         18mV   18.9mV.

0V.
  1000nplc/off    0.7mV. 0.7mV,   1.9mV
  10nplc          2.7mV  2.6mV
  1nplc           12.6mV 13.8mV.
  0.5nplc         24mV   24mV

-10V.
  1000nplc/off    2.0mV  2.8mV 2.0mV
  10nplc          6.7mV  6.7mV
  1nplc           20mV   20mV. 20.5mV
  0.5nplc         32mV   34.2mV


Edit. A small resistor at R405 looks like it should work and can create a constant offset shift at all input biases. But a negative source is needed for lv4053 (existing positive source is ok max4053).  But I probably won't tinker more just at the moment.

[David Hess]

If one really wants to compensate such a tiny current, one could consider a little light to a low leakage diode and there are a few glass case types. It does not take much for a few pA.
Light can also effect the bias on some chips in a plastic case, especially the thinner ones.

Before I knew enough, I designed one circuit which had to use hermetic packages and found that the glass diodes were most sensitive to near infrared causing excessive leakage.  For some reason instead of black paint, we dissolved black mastic in thinner and used that as paint.

If I did that design now, I would use transistors as low leakage diodes and bootstrap them to easily achieve less than a picoamp.

[schmitt trigger]

Subscribing to thread

[Alex Nikitin]

If I did that design now, I would use transistors as low leakage diodes and bootstrap them to easily achieve less than a picoamp.

No, BAV199 diodes from Infineon or NXP would be much better (and not light sensitive). Here some leakage data on several BAV199 makes at 26C, both for reverse (0-100V) and forward (50mV-500mV) bias, vertical scale in Amps, horizontal in Volts. Measured with Keithley 617.

Cheers

Alex

P.S. - added a comparision between some of the worst of BAV199 (from Diodes and Multicom, IIRC) and 1N4148, just to put this matter into perspective

[DeltaSigmaD]

@ Alex: Thanks for these measurements. One point must be considered with the BAV199: this diode has a long reverse recovery time, too slow for some applications. I assume that the BA199 has a wide depletion zone without deep traps dedicated to work as fast recombination centers, as the case with the 1N4148. Therefore, the leakage current and the capacitance are very low, but minority carriers have a long life time.

[Alex Nikitin]

@ Alex: Thanks for these measurements. One point must be considered with the BAV199: this diode has a long reverse recovery time, too slow for some applications.

Nothing is perfect  . It is worth remembering however that at the current levels discussed (picoamps and below), a microsecond is not much, as 1pA is about 6 electrons per microsecond.

Cheers

Alex

[David Hess]

If I did that design now, I would use transistors as low leakage diodes and bootstrap them to easily achieve less than a picoamp.

No, BAV199 diodes from Infineon or NXP would be much better (and not light sensitive). Here some leakage data on several BAV199 makes at 26C, both for reverse (0-100V) and forward (50mV-500mV) bias, vertical scale in Amps, horizontal in Volts. Measured with Keithley 617.

The BAV199 is only *tested* to 5 nanoamps, which is not practically any better than a small signal bipolar transistor, so either must be graded or selected anyway.

The BAV199 has a huge advantage in reverse breakdown voltage, comparable to a base-collector junction if you what to go that route instead (1), but if bootstrapping is used, then the base-emitter breakdown voltage is sufficient, and the base-emitter junction is lower capacitance and orders of magnitude faster (2) than a BAV199.  The 60 millivolt conductance that you measured is identical to a 2N3904 base-emitter junction, so that is a pretty good diode, but no better than a transistor.

5 to 15 volt low leakage fast diodes used to be available, but even in the past, they were expensive simply because there was so little demand for them.

(1) A base-collector junction has higher capacitance and is slow, but the BAV199 only bests it with better conductance.

(2) I measured 600 picoseconds on typical 2N3904s, which is consistent with fast low voltage low leakage diodes of the past, but I would like to repeat this measurement with better equipment.

[Alex Nikitin]

I am not in a business of selling diodes, I only share my data. There are diodes with better leakage specs, for example FJH1100 with the max leakage current of 3pA at 5V and 10pA at 15V, with the price over $10 each, much lower max voltage and comparable capacitance and current ratings. I did include this diode in the graphs by the way - have a look *. And obviously, I've measured many diodes from each of different makes and batches, the performance curves as on the graphs are pretty typical and I haven't seen any real outliers. For the price difference you might just as well measure each and every diode before using it  .

Cheers

Alex

* - P.S. and the FJH1100 is light sensitive even if the black coating is not damaged

[Kleinstein]

Diode leakage is not really an issue in the front end so far. The clamping diodes can be bootstrapped and thus only see a low voltage in the 1-5 mV range. One version has a AC optocoupler input (IR diode) to do the clamping. These have a relatively high forward voltage and thus likely also low leakage.

For the lowest leakage one may have to gamble on using the typical specs. The limiting specs are often just limitations on the test setup and actually performance is often way better and most of the parts are likely close to (or even better than) typical.  The question is if it is worth testing the parts upfront, or just use in the circuit and than check the complete or maybe partial populated PCB. Even if parts test good before, soldering may change things.

The critical leakage is more from CMOS switches or alternatively JFETs used for switching.  Modern CMOS switches like the ADG1208 seem to be pretty good - as measured here even better than typical specs.
The CMOS switches are much easier to use than JFETs. Still JFETs are nice in that they are essentially no power and essentially no leakage when on.  Ideally not that many swiches are really critical with leakage.

A point I see is that it helps to design for low power. Some heating (5 to 10 K) above ambient has a positive effect on humidity and thus surface leakage, but more is bad with thermal fluctuations and semiconductor leakage.

[David Hess]

Diode leakage is not really an issue in the front end so far. The clamping diodes can be bootstrapped and thus only see a low voltage in the 1-5 mV range. One version has a AC optocoupler input (IR diode) to do the clamping. These have a relatively high forward voltage and thus likely also low leakage.

The wrong diodes will still leak at millivolt levels, so there is still cause to use low leakage diodes.

Using an optocoupler input diode is clever.  LEDs when painted also make useful low leakage diodes and also achieve low leakage at low forward voltages.

[julian1]

For the adc, the design is similar to the one in the diy-voltmeter thread.
A difference is the integrator reset which is managed with another spdt 4053 mux, instead of being muxed through the main buffer/amplifier.

configuration -
ref lt1021/7V.
amplifier lsk389. will revert to jfe2140 as baseline, when get some more.
bench supply.
a biscuit tin lid covering the pcb helps to reduce noise.

The main column of interest is the last one,
10nplc noise is around 0.33uV RMS.  1nplc noise around 1.4uV RMS. I believe this is mostly from the adc input resistors.
reference noise in the adc, should most cancel, for a lo measurement/sample.

- sample ref-lo with no amplifier gain,

az 10nplc
> reset; azero on; nplc 10; himux ref-lo ; azmux ref-lo ; gain 1; buffer 30;  trig
counts  10002 2022507 1977610    891 4000001 (lo)  (hi -0.000,003,7V) (lo 0.000,003,8V, 0.000,003,7V) az meas -0.000,007,5V   mean(30) -0.0000077V, stddev(30) 0.31uV,
counts  10002 2022490 1977610    232 4000001 (hi)  (hi -0.000,004,6V) (lo 0.000,003,8V, 0.000,003,7V) az meas -0.000,008,3V   mean(30) -0.0000077V, stddev(30) 0.32uV,
counts  10002 2022507 1977610    891 4000001 (lo)  (hi -0.000,004,6V) (lo 0.000,003,8V, 0.000,003,8V) az meas -0.000,008,4V   mean(30) -0.0000078V, stddev(30) 0.33uV,
counts  10002 2022490 1977610    229 4000001 (hi)  (hi -0.000,004,3V) (lo 0.000,003,8V, 0.000,003,8V) az meas -0.000,008,1V   mean(30) -0.0000078V, stddev(30) 0.33uV,
counts  10002 2022507 1977610    889 4000001 (lo)  (hi -0.000,004,3V) (lo 0.000,004,0V, 0.000,003,8V) az meas -0.000,008,2V   mean(30) -0.0000078V, stddev(30) 0.33uV,

az 1nplc.
>  reset; azero on; nplc 1; himux ref-lo ; azmux ref-lo ; gain 1; buffer 30;  trig
counts  10002 202317 197812    726 400001 (hi)  (hi -0.000,009,9V) (lo -0.000,001,1V, 0.000,001,8V) az meas -0.000,010,2V   mean(30) -0.0000071V, stddev(30) 1.28uV,
counts  10002 202317 197812    713 400001 (lo)  (hi -0.000,009,9V) (lo 0.000,002,7V, -0.000,001,1V) az meas -0.000,010,7V   mean(30) -0.0000072V, stddev(30) 1.41uV,
counts  10002 202317 197812    723 400001 (hi)  (hi -0.000,007,0V) (lo 0.000,002,7V, -0.000,001,1V) az meas -0.000,007,8V   mean(30) -0.0000072V, stddev(30) 1.39uV,
counts  10002 202317 197812    716 400001 (lo)  (hi -0.000,007,0V) (lo -0.000,000,2V, 0.000,002,7V) az meas -0.000,008,3V   mean(30) -0.0000071V, stddev(30) 1.37uV,
counts  10002 202317 197812    721 400001 (hi)  (hi -0.000,005,0V) (lo -0.000,000,2V, 0.000,002,7V) az meas -0.000,006,3V   mean(30) -0.0000071V, stddev(30) 1.38uV,


There is a -8uV difference when ref-lo is sampled from the himux versus the azmux - in az mode, regardless of nplc.
The ref-lo trace is kelvin sensed at the gnd pin of the lt1021.
The only adc count that changes (for 1nplc example) is the rundown count, so it is not a calculation artifact.

The difference is a bit large to be a thermocouple effect on ic pins/ or copper trace.
So I don't like this.
maybe switch charge-injection when the az mux switches between the lo/boot from the pc-switch to the ref-lo.
and/or distribution for different impedances of the mux paths?
But I still wouldn't expect this given that ref-lo is a low impedance input.
EDIT. Also if it was a charge effect on would expect to see the effect change at different nplc/apertures.

The other LO that is common to himux/himux2 and azmux is the star-lo.
So I should check to see if that shows the same issue.
Also there is the resistor R417 that can match/compensate the rds-on of the hi muxes.


for 10nplc no-az input noise is about the same as the az case.

> reset; azero off; nplc 10; himux ref-lo; azmux pcout ; pc signal ;  gain 1;  buffer 30; trig
counts  10002 2022490 1977610    228 4000001 no-az meas -0.000,004,2V   mean(30) -0.0000038V, stddev(30) 0.34uV,
counts  10002 2022490 1977610    225 4000001 no-az meas -0.000,003,9V   mean(30) -0.0000038V, stddev(30) 0.33uV,
counts  10002 2022490 1977610    232 4000001 no-az meas -0.000,004,6V   mean(30) -0.0000038V, stddev(30) 0.35uV,
counts  10002 2022490 1977610    230 4000001 no-az meas -0.000,004,4V   mean(30) -0.0000038V, stddev(30) 0.37uV,

There is a 3.8uV difference in non-az mode.
But this expected thermal variation (ref, op-amp Vos,resistors) from the calibration baseline point taken about 10-15mins earlier.

[julian1]

For the amplifier, the ref-lo can be sampled with gain,

az, 1nplc, gain = 100.
>  reset; azero on; nplc 1; himux ref-lo ; azmux ref-lo ; gain 100; buffer 30;  trig
counts  10002 204765 195449    840 400001 (lo)  (hi 0.207,785,5V) (lo 0.207,950,7V, 0.207,939,0V) az meas -0.000,159,4V   mean(30) -0.0001477V, stddev(30) 7.82uV,
counts  10002 204748 195449    246 400001 (hi)  (hi 0.207,803,0V) (lo 0.207,950,7V, 0.207,939,0V) az meas -0.000,141,8V   mean(30) -0.0001472V, stddev(30) 7.71uV,
counts  10002 204765 195449    830 400001 (lo)  (hi 0.207,803,0V) (lo 0.207,960,5V, 0.207,950,7V) az meas -0.000,152,6V   mean(30) -0.0001470V, stddev(30) 7.51uV,
counts  10002 204748 195449    258 400001 (hi)  (hi 0.207,791,3V) (lo 0.207,960,5V, 0.207,950,7V) az meas -0.000,164,3V   mean(30) -0.0001478V, stddev(30) 8.06uV,
counts  10002 204765 195449    839 400001 (lo)  (hi 0.207,791,3V) (lo 0.207,951,7V, 0.207,960,5V) az meas -0.000,164,8V   mean(30) -0.0001484V, stddev(30) 8.62uV,

note. amplifier Vos around 2mV.

no-az,  at 1nplc  gain = 100.
> reset; azero off; nplc 1; himux ref-lo; azmux pcout ; pc signal ;  gain 100;   trig
counts  10002 204748 195449    210 400001 no-az meas 0.207,838,1V   mean(30) 0.2078348V, stddev(30) 6.20uV,
counts  10002 204748 195449    211 400001 no-az meas 0.207,837,2V   mean(30) 0.2078352V, stddev(30) 6.00uV,
counts  10002 204748 195449    223 400001 no-az meas 0.207,825,5V   mean(30) 0.2078349V, stddev(30) 6.26uV,
counts  10002 204748 195449    216 400001 no-az meas 0.207,832,3V   mean(30) 0.2078343V, stddev(30) 5.66uV,
counts  10002 204765 195449    946 400001 no-az meas 0.207,847,3V   mean(30) 0.2078348V, stddev(30) 6.12uV,


For the 1nplc, gain=100x case, the az and no-az look similar for noise.
I am not sure how to interpret that.
Is the noise from the amplifier or 99k/1k feedback resistors, or the (amplified) white-noise of the resistance of the muxes/passives before the amplifier?
I kind of expected the az subtraction to cut-out flicker noise in a more observable way.
Or maybe it is evident, given that AZ mode only uses half the HI samples, but achieves similar variation.

[Kleinstein]

The AZ mode reduces the effect of flicker noise by limiting the lower frequency end. If there is not much flicker (the LSK389 are pretty low noise) this effect may not be that large and 30 samples are not that long (less than 1 second in 1 PLC non AZ mode). The non AZ mode noise is not much lower, despite of having effectively half the BW. So there is some low frequency noise, but not very much.

The noise with gain is still not that low as one may hope for.
The 1 PLC AZ mode has a noise BW of 2x25 Hz
The 8 µV are already well more than the ADC noise alone, so most of the noise is from the amplifier, not much from the ADC.
some 8 µV at the output or 80 nV corresponds to some 11.5 nV/Sqrt(Hz) for the input noise.  This is not really good, but also not super bad.

The 11.5 nV/SQRT(Hz) correspond to the noise of about a 8 K resistor. So the 1 K in the feedback can not be the main source. There are likely a few more resistors in the input path for filtering or protection that could add up and the ground sense path may also have resistance, if only for compensation / symmetry.
Another part of the noise may still be from thermal fluctuations. 80 nV are not much and in my circuit I had some 30 nV_RMS from thermal fluctuations.
It may help to look at the frequency spectrum or allan deviation of the noise - to record some 10000 points and plot it. Thermal noise is more flicker / random walk like. Resistor noise is usually white noise and interference / beat frequency to mains may have a distict frequency.
If there is significant popcorn noise (well possible for a JFET amplifier), one can often see this in the time domain, preferrably in the non AZ mode.

The ADC noise shows more noise than expected from the input resistors. With 50 K this would be more like 290 nV RMS noise for the 1 PLC AZ case. The noise is OK at least for the start (maybe close to the KS34465), but still not great.  The ratio of noise in the 1 PLC and 10 PLC mode is around 4.2. This is more than square root of 10 as expected for simply the lower bandwidth. This points to some noise from the run-down part / comparator or possibly quantization still relevant in the 1 PLC case.  I don't have the details to have a good guess on the noise sources, but it is likely more than just the input resistors.

Even with 0 input voltage there can also be reference noise (from higher frequencies around the modulation frequency in the ADC) to contribute to the ADC noise. The +- ref modulation acts like a mixer and bring that higher frequency down to the near DC range.
It is often overlooked, but is relatively easy to fitler out, somtimes even as a side effect of a slow amplifer. Worst case (no filtering effect) it could make up some 1.1 µV for the 1 PLC case.   

8 µV of difference for different ground sensing paths is a bit high for just thermal EMF, but not impossible. Some ICs and also resistors can have relatively high thermal EMF. I have measured some 4 µV as the difference between 2 units of the protection part. Thermal EMF would also be sensitive to warm up and air flow.

[julian1]

To follow up on the 8uV observed difference for ref-lo depending on sense point (at himux or azmux point).
It looks like there really is a small voltage difference there.
The way to confirm this, and rule out AZ/switching issues, is to use non-az mode and collect samples for both cases.
Perhaps the separate/ copper islands used for guards create more localized thermal isolation/differences across the pcb.
Something for the future might be to test dg508 as well.

For noise investigations, a good first-step is probably to swap the lt1021/7V to rule out issues.
For ltz1000, the pcb has a 'normal' pin-out soic-8 dual op-amp.
I have bjt single-supply mc33172 (lacks some LF characterization), and opa2145 (jfet). BB opa2234 look good but are obsolete.

Maybe mc33172 could be used, and then some in-circuit checks done?

If ref-hi was fed to a 10-30uF PP film capacitor (same as a lna), the output could be amplified 100x and then digitized/sampled,
The 10Meg divider/ fixedz, could also set the input source impedance.
I think this should permit measuring ref-noise, independent of its contribution to the adc,
(the assumption is that ref-noise is higher than amplifier noise, which seems reasonable).

[julian1]

op-amp choice for reference.

lt1006 / lt1013. (can't use because of pinout)
  input noise voltage,   0.55uV. 0.1-10Hz.
  input noise voltage   22nV / rtHz. f=1kHz.  23nV/rtHz at 100Hz.
  input bias current    10nA. typ.
  input noise current,  0.08pA/√Hz   f=10Hz


MC33172
  input noise voltage,  Vpp 0.1-10Hz. not given.
  input noise voltage 32 nV/ √ Hz    f=1kHz.
  input bias current 20nA. typ.
  input noise current. 0.2−pA/ √ Hz    f=1kHz.
 
    V=IR,  with 50k input impedance. assuming 'In' has any meaning at 0.1Hz.
    = 0.2e-12 * (1 / Math.sqrt( 0.1)) * 50e3
    = 3.16e-8
    = 31nV.    at 0.1Hz. ?
 

opa2145.
   input noise voltage,   0.32uV. 0.1-10Hz.
   input voltage noise .  7nV / rtHz. at 1kHz.  7.1nV at 100Hz.

[Kleinstein]

Not sure if it is already time to use an LTZ1000 reference. At near zero input the reference noise to possibly worry about is the higher frequency (e.g. 10 kHz to some 100 kHz) and this is relatively easy to filter out with a relatively simple RC (e.g. 1 K and 1 µF).

Even if using the LTZ reference it would be good to also have some filtering there.

The reference noise is also only one possibly source of extra noise.
I would exclude extra 1/f noise, like excess noise of resistors as the 10 PLC case is even lower noise density.
Looking at the noise data as a plot could help - maybe something really low frequency (e.g. supply drift, a beat frequency with mains, thermal). Also a schematics of the ADC part would help and make it less guess work.


AFAIR the transistor part at the LTZ1000 has a gain of some 200 and this should be enough to attenuate the OP-amp noise and drift by about that factor.
In theory the MC33172 should be just OK, though a slightly odd choice. The current noise and maybe drift of the input bias could be an issue.
The OPA2145 should be OK too - much better specs in most aspects, just a bit unclear about long term offset drift. I would consider it more like overkill.
The higher BW may want some care.

The OPA2234 is kind of a predecessor to the OPA1642 and a bit on the fast side and high in power consumption.

[julian1]

Is there a go-to octave/matlab script for spectral decomposition/ allan variation for a larger sample set?,
I've done fft on time-series data a long time ago.

To potentially rule out some basic issues - I swapped the ref over, changed the rundown bias resistor (R902) from inexpensive thin-film to zfoil to exclude thermal effects.
Also added gain to the slope amplifier,  from opa140, 10k/10k to opa140 2.15k/21.5k (2k loading on integrator output is probably too high).
In the past I tried perturbing the slope-amp with bjt op-amps - ne5534, op27, op37, lt1358. but without seeing much affect.
the reset resistor (R903) is 3.74k. not 20k. as indicated on the schematic (also a load on the integrator op).
only the lt5400 resistors are populated. the discrete resistors are to experiment.

The biggest difference is seen by adding tin lid for shielding. 0.6uV -> 0.4uV.  10nplc. az off.

Two things in my mind are  - to populate the RC (C916,R909) between the adc current and integrator input.
I remember probing it, and it is certainly spikey. but I never got around to adding RC here.
I should also try sampling boot on input, to by pass the 2k+2k+mux rds(on). input source resistance (R425, R431).

But maybe potentially distinguishing white-noise/ flicker noise, would be easier with a frequency/noise plot.

[iMo]

I've been just using the TimeLab for ADEV/MADEV while looking at an ADuC ADC here..
It makes the analysis "online" as the data stream off my ADC (via bluetooth into Teraterm, TT logs into a file and TimeLab reads the data off the file in the real time, setting Aquire->Aquire from the live ASCII file). Example below..

[Kleinstein]

The reset resistor does not matter directly for the noise, a larger resistor only makes the reset slower and thus more time needed for the reset. 4 K and 2 nF are 8 µs time constant and thus likely some 20-40 µs as a suitable time. The 3.74 K sound about reasonable as they also load the integrator.

The RC element C916 and R909 is defintely a good idea. Even if not fine tuned it generally helps with the settling of the integrator. That is less ringing visible at the output of U906. That output is anyway a good testpoint to check the integrator settling and how long one should wait between switching events. The values for R910 and R911 also effect the settling. They are not an alternative to adjusting the integration capacitor, more a thing to trim the speed of U906, e.g. to allow different speed combinations.

The slope amplifier has also the task of limiting the bandwidth for the signal to the comparator. More BW here also means more noise. Less BW (e.g. more gain at the slope amplifier) gives a slower reaction and more overshoot and thus a slightly slower rundown for the slow slope part. A rather high BW with a relatively large integration capacitor could be an issue and add residual charge noise, so noise that gets higher for short integration. Part of the noise seen is of this type (about 4 :1 ratio instead of square root 10).

Another possible issue would be that there is only partial filtering at the references. When I removed the filter capacitor in my ADC with a LM399 reference, the noise for 1 PLC went up from some 550 nV to some 1.3 µV.
A more minor issue is that the resistors at the reference amplifer are relatively high. It looks like 8 x 10 K in series for the whole amplifier and thus 40K+40K seen by the inverter part. This effectively adds the noise of a 20 K resistor. Still this is only a more minor noise source. So skipping RN902 and double R902 may be a thing for later.

In the plan the flipflops to syncronise the control signals are 74HC175. These have quite some jitter and the LV or AC series would be better. Depending on the clock signal also ACT or similar to work with a smaller input signal.

For the integrator input it looks like the plan is for 40 K at the reference and 50 K for the input - just like the HP3458. This would give an about 14 V FS range, but may result in more gain drift from the switch resistance. I would expect an extra   -1 ppm/K from this. So not very much, but avoidable. It also increases the resistor noise a little over the case with 3 x 50 K or 3 x 40 K. Using a +-14 V ref instead of +-12 V as in the 3458 is the better alternative to the lower resistors for the references.

[julian1]

Thanks Imo! I tried a batch file import around 11k obs/ 4 minutes, copying your config - with decimal frequency for data field, and 0.02 sample rate.
The axis don't pick up labels or units. Perhaps they need to be set up by hand?, or it's a wine issue?

[julian1]

Allan plot using NXP octave code from, https://www.nxp.com/docs/en/application-note/AN5087.pdf

1nplc, no az.

Edit. fix freq.

[Kleinstein]

The Allan deviation showns the normal square root slope below some 1 s as expected for mainly white noise. This points to a relatively low level of 1/f noise - so not much excess noise from resistors.  The bump at some 10-20 s is a bit strange. It could be some typical frequency of popcorn type noise in the OPA140 or front end amplifier. Another thing could be a thermal effect. I have seem a comparable frequency as thermal oscillation and in non AZ mode there can be some sensitive parts at the integrator.

The raw data look like there is some rounding / quantization noise included. Overall it is pretty low drift for a non AZ mode of operation.

[iMo]

@julian1 - your data in my TimeLab (win10)..

PS: added the same with the latest TimeLab 1.71a beta

[julian1]

I've made some changes to improve adc noise a bit.

changes creating obvious improvement -
  - swap lt5400 to morn resistors that I had at hand. these look superior from Castorp's published research, reduced 1.3uV  to 1uV RMS 1nplc.

  - nov 18. lowering freq. 330p/84kHz to 1.5n/ 19Khz. reduced 1uV to about 0.7uV RMS 1nplc.
    This improvement is less than the expected ( Math.sqrt( 84kHz ) / Math.sqrt( 19kHz) = 2.1x ), if integrator op-amp noise was dominant.


other changes, with less noticeable influence

  - swap synchronizer 74hc175 to lv175, not sure how I overlooked this.
  - swap comparator from lt1016 to tl3016, mostly to reduce current and heat. lt1016, is horrible and the to-92 L7805/7905 regulators are hot and can barely be touched.
  - shallower rundown, less quantitization, although past tests suggest this may affect INL a little due to DA.

  - also increased slope-amp gain (to reduce slope-amp BW - and gave more hysteresis for the comparator, to ensure no output glitching/meta-stablility issues.
      (control over the comparator latch to prevent glitching, is not effective if the control cannot first sample a clean value on the clock edge).
      this seems to be more an issue for tl3016 v lt1016.
      although none of these changes appeared to influence measurement noise.

  - I couldn't see any difference, from adding LP filtering of the ref for HF noise with LC 1k/1u PP or x7r,
      Perhaps a series RC bypass to ground would be better - similar to the 1u/5R of the adr1399 reference circuit?
      - the ref sits right next to the adc current source ladder which is good.
      but the ref-lo and ref-hi traces cross the adc circuitry to reach the input muxes, so this could be an issue.
      It's not possible to LC filter the references here, so this has to be addressed with an improved layout.

  - using 34401a transformer to power the board, instead of a bench supply.

- I believe it's possible to see the adc noise on a scope.
    Hooking up scope/digital probes does ground reference the circuit, and introduces additional EMI, which increases measurement stddev 2x to 3x.
    But it is still possible to visually correlate the waveform variance and magnitude, which is mostly associated with runup (horizontal displacements of the waveform at the end of runup),
    rather than anything around rundown/comparator sampling.

- it should be possible to do a kind of rundown re-sample/multi-sample. So after final rundown, the output could be steered to perform a second rundown cycle
    And ths would improve rundown sampling noise.
    But given what can be seen on the scope, I doubt that it will help.
    Also switching to an ADC to multi-sample the rundown output would be more effective and simpler.

[Kleinstein]

There are quite a lot of possible relevant noise sources for the ADC.  And some of the details of the ADC decide which a really relevant and which are hardly noticable. The more important ones are:
1) The resistors at the integrator :  with equal resistors this behaves like 2 of the resistors in series to the input.
2)  low frequency noise of the integrator. This is usually 1 OP-amp with a noise gain of about 2 (with equal resistors at the integrator) or a bit higher with smaller resistors for the references.
     With a BJT also the current noise can matter, it is effective with the input resistor to the integrator and some DS are a bit optimistic.
3) Jitter from the clock, flip-flops and switches. This is more inportant with faster modulation and slower chips.
4) Capacitance of the ref. switch input side leading the "reset noise": may be an issue with fast modulation and relatively large capacitance. Should be OK with the LV4053 switches.
   Fluctuations in the charge injection acts similar.
5) low frequency noise of the reference amplification (usually 1 OP and the resistors at the inverter)  - should be a more smaller part
6) higher frequency reference noise, that is modulated by the runup patters and gets mixed down. Often one has some fitlering for this, by caps to stabilize the reference amplifiers.
    This may be an issue in some of the Keithley meters as they tend to use fast amplfiers in the ref amplification.
7) higher frequency noise of the integrator and slope amplifier leading to noise at the comparator. This noise is usually effective with the BW of the slope amplifier. The size of the integration cap also enters here. This noise is part of the residual charge noise and this more relevant for short integration.
Quatization noise, usually for the residual charge and thus more a thing with short integration. This part can usually be calculated quite well.
9) switching between different run-up patterns that should ideally give the same result, but with a relatively high DNL error would also give noise. This is more an issue with an auxiliry ADC for the residual charge, less with a reset.

The LT5400 resistors should be OK and low noise it may be the resistor value that can make a difference.  Noisy ones are more like AORN and NOMCA and some separate thin film resistors (e.g. ptf56 series).


Changing the modulation frequency from 84 to 19 kHz and the corrosponding change in the capacitor is expeced to reduce the effect of jitter, but get the resitual charge part more important.

P.s. getting to 0.7 µV RMS for 1 PLC is already quite good.  Expect a mix of noise sources if one is that good.

[julian1]

It is probably good to test other circuts for basic function, to be in a position to make revisions.
This is an attempt at an ohms current-source - very classical, with one resistor per range.

overview,
- tested. appears to work, can iterate fixed current-ranges (1uA-10mA), without oscillation, although I havent tried with the protection.
- kept simple, in the sense that different switch paths are all identifiable and separate. although it's open to the criticism too many switches and resistors are used, creating a poor BOM.
- agn200 relays are nice and compact. about the same footprint as an soic part.
- TC stability should mostly be determined by resistor choice - a custom footprint allows 0805 to 2010 parts.

design,
- there are two independent output sections - a high-current (dmos pfet), and low-leakage output (pjfet, depletion mode fet). relay K601 selects the output stage choice.
    this requires an extra switch, but is more open/flexible than than trying to combine a low-leakage and high-current output in the same circuit (34401a,3458a).

- for the 10mA range, relay K602B is used instead of a U605 mux channel, to avoid excessive voltage-drop through the mux.
  The original schematic has an option for a low resistance mux u608 (eg. adg1408 rds-on=4.7R) for the 10mA and 100mA ranges, but I decided against the 100mA, and it has been removed. 

- K602A (with K602B) was added to support a relay state combination for galvanic off isolation.
    but may also help protect the low-current output-section from accidental engagement of high-current (10mA) drive.
    not sure if useful, and it is currently shorted with a jumper.

- Q615 is used to (digitally) sense negative over-voltage conditions, and is taken straight from Kleinstein's design.


what i don't like,
- I feel relay k603 that selects the bottom divider resistor should be able to replaced with a mux.
    But I cannot see how, without adding the TC sensitive mux-resistance to the divider, or else by duplicating other circuit elements.

- the zener (replacing d601,d603) setting up the working headroom, could be made user-switchable for a lower output compliance voltage.
    But would require another mux...

[Kleinstein]

The leakage of the P-FET in the current regulator should not matter. If at all it is about the gate leakage and even the larger P fet should be good enough here. The actual leakage is usually vial the protection and performance can vary. So I don't think the switching of the p-fets for high / low current is really needed.

The part that may want switching would be the OP-amp to do the regulation, as this is a compromise between bias dirft and noise / voltage drift. The higher currents would be happy with something like an OPA387 for the regulating OP-amp for low voltage drift. The lowerst currents (e.g. 1 µA and less) would prefer the OPA140/OPA145, as here the bias current and current noise is more relevant. For the bias it is actually only the current drift that really matters. The normal bias is just a part of the test current. Only the current ratio between the 3 V and 0.3 V ref voltage would differ a bit.
So if one wants to switch between high and low current parts it would make sense to switch more, e.g. the complete current source up to the protection.
Using a dual OP-amp for U603A/B is not such a good idea as the needs are a bit different, with the smaller currents. U603A wants low drift, but the bias is not that critical as long as it's less than the test current.

Another point for the higher current ranges is that the power loss on the current setting resistors gets quite large. So 10 mA test current would be more set with 1 V and 100 Ohm and not 3 V and 300 Ohm. Even a 2010 foot-print may be a bit on the small side for the 10 mA test current - I have 3 pieces of 0805 in parallel and thermal effects are still quite large.

With a 10 mA test current one may want to have a way to turn of the current in case there is a significant foreign negative voltage. The SOA if the small SOT23 transistor is usually not that good. One may get away with a software solution, though not ideal.

The diodes in series with the MUX chip mainly make sense when there is an additional resistor to an auxiliary voltage level to catch MUX leakage. This way the drive side MUX gets non critical (e.g. could use something like TMUX4051 or HC4051 with level shifters). This way the leakage is from the diodes instead of the MUX chip. With the rather good ADG1208 one may get away with just the MUX, and skip the diodes.

For the K603 part the simple way would be to work with a fixed current source from the low side and switch the resistor tap at what is now R608.
Not sure if one really needs a buffer for ref. low, of simple GND may be good enough. A buffer would anyway need a negative supply, as it would need to drive current at essentially GND level.
Switching to a lower output compliance voltage could be rather crude with transistor switching - this is not about precision, but only order of magnitude. There is anyway some drop at the protection.

For stability with an inductive DUT one may want a resistor (e.g Kohm range, but depends on rest of circuit) in parallel to L601.

[julian1]

The actual leakage is usually vial the protection and performance can vary. So I don't think the switching of the p-fets for high / low current is really needed.

For the split output section, I probably need to actually measure/test the gate leakage of pmos / bss84, and decide on parts to determine if it is justified.
The adg1208 mux and jfet input of U603A have leakage in low pA.
So anything in that range would be fine for low-current ranges.
3458a uses bjt op07 as driver with much higher input bias, but perhaps better drift.
I agree there is a high chance the bav199 diodes following the mux may not improve leakage below the mux leakage.
Also there is a chance dg508 is better than adg1208.
I just never tested it beyond some quick tests, to confirm that both were pretty good.
 

With a 10 mA test current one may want to have a way to turn of the current in case there is a significant foreign negative voltage. The SOA if the small SOT23 transistor is usually not that good. One may get away with a software solution, though not ideal.

The software solution for negative OVP, using the signal from Q615 isn't great.
perhaps the collector could just be used to pull the output p-fet gate up, to turn off?
eg. after the gate-resistor R606, maybe using a current-mirror to the +18V rail.

A buffer would anyway need a negative supply, as it would need to drive current at essentially GND level.

Thanks, that is a critical mistake. I was thinking about the op inputs at gnd, but forgot about the op being able to pull output to ground, without a dual-supply.

Switching to a lower output compliance voltage could be rather crude with transistor switching - this is not about precision, but only order of magnitude. There is anyway some drop at the protection.

Yes, just a crude ability to switch between say 2V and 10V would be enough.
I am trying to imagine would it might look like.
A zener or vbe multiplier/rubber diode to reduce compliance voltage would work well.
And better than messing with the static reference voltages at the lhs.
But I cannot see how to short-it/turn it off with a fet - without introducing leakage, maybe an optocoupler?.   
and if it is ground referenced, then it may screw up protection for over-voltages.

[Kleinstein]

The input bias of U603A is not critical at all. The current is provided by the drive side and not flowing through the range setting resistor. So it is only about drift and noise there. Somthing like an OP07 or more modern OPA207 is OK there.

The diodes in series with the MUX would only help for one direction of the leakage current, but not the other. The idea with the diodes in the 3458 and Keithley2002 is to use diodes to set the leakage instead of the MUX. One can than use a rather plain simple mux with higher leakage (e.g. DG408 or new TMUX4051) and also higher current capability. The 3458 even usus BJT switching incombination with the diodes. In my version I also use diodes for the middle ranges and a transistor instead of the diode for the highest current. So far I have not seen a leakage problem with the transistor and this way the 10 mA don't have to go through the mux.  Chances are the ADG1208 is good enough and can get away without the diodes. The fixed part of the leakage is not even critical. It is only the variable part of the leakage the would matter. This mainly the temperature effect as the voltages are fixed.

The somewhat critical parts for leakage are U603B, U604, U605 and D606.  If the series diodes with resistors to a auxiliary level are used U605 would be replaced by the diode leakage.
In addition there may be a buffer for the guard potential around the output / protection level.
Another point can also be relays. Especially the cheaper reed relays seem to be somewhat leaky.
Overall the leakage it not that super critical. There is no need to be much better than the normal voltage input.

The software solution for negative OVP, using the signal from Q615 isn't great.
perhaps the collector could just be used to pull the output p-fet gate up, to turn off?
eg. after the gate-resistor R606, maybe using a current-mirror to the +18V rail.

Such a system work, I have it in my circuit, with on the single PNP transistor. A current mirror would be even more controlled. I can use the auxiliary buffer that is there for the diode switching anyway, using the +18 V would likely be OK too.

For limiting the compliance voltage, one could also use the optional guard buffer and regulate / limit the there. This could be even relative accurate, though possibly a bit slow and tricky to get stable under all conditions. So there could still be transients with higher voltage.

[julian1]

I did some basic tests on current measurement functions.

Some thoughts on the design -

- high current relay K703 offloads the 1A and 10A ranges to shunt R702 (Vishay VCS301 0.1R 4W resistor) as soon as possible, so subsequent relays and copper traces can be smaller/thinner.
- the shunt/TIA select relay K709  unloads the capacitance of the shunt chain/switches from the TIA input, when the TIA is active.
- the high-current relays K702,K703 are latching RT424 and were tested for leakage, at least to 1pA level.
- BOOT2 used to bootstrap the protection is switchable depending on whether shunts or TIA are active.

The shunts drop 100mV.
So amplifier gain = 100x, except for 10A where gain =10x.
Excessive self-heating on the R702 for 10A may be an issue.
So 3A or even 1A (P=100mW) could be a practical limit, if the VCS301 doesn't have a heatsink.

The current shunts get switched using relays, while the sense taps are switched using analog-switch U703.
The spare relay pole could also be used to switch the sense tap.
But the analog-switch has an advantage as a precaution against extra Seebeck/thermocouple effects due to relay construction.
The 100x gain, means thermocouple offsets get amplified along with the small burden voltages.
On this point, relay K709 (shunt/TIA select) is shown placed in the shunt chain, after R702 where DCI-HI is sensed.
I think it should move before R702, to eliminate relay thermocouple effects, even if that would require changing to a high-current relay.


The TIA 10uA,1uA, 100n  ranges are stable with feedback caps of 22p.
Output range is +-10V.
A TIA has a large inherent dynamic-range. but range-switching is added using several feedback resistors.
This should reduce the Vos drift present in the measurement signal, compared with a fixed value TIA and switchable gain amplifier.
I am not sure if a chopper-stabilized op would work for ACI ranges (possible feature development), due to intermodulation distortion.
I have a preference to avoid zero-drift amps due to inexperience and high apparent complexity (high Ios/input offset currents, switch noise, emi source, one-time complexity).

Perhaps the TIA should be a compound amplifier, to help equalize BW across ranges, similar to the main amplifier.
But I am not sure if this applies to a TIA where current-gain is the important point, at least on the op-amp input side.
Also, bandwidth for different ranges, can be somewhat controlled for - with the value of C in the Rinput/Cf ( 10k/22p=723kHz ).


The input protection has not been tested.  A single bridge-rectifier repackage (gbj1508) would be simpler than discrete dpak bjts and smb diodes.
It would probably be better to demonstrate that the more complicated circuit with BC tied bjts is needed before using it.

I am not sure if some inductance should defined on the input near the input fuse.
Or whether the inductance shown in some schematics is added as a workaround for small dimensioned fuses blowing on transient currents.

[Kleinstein]

K709 should indeed be moved to before the whole shunt chain starting with R702. It is not so much because of thermal EMF in the relay but because of contract resistance that would be included too.

The 0.1 ohm shunt is OK for 1 A, maybe 2 A with a few thermal effects. I would not expect much more than that. It is more that one uses even less than 100 mV burden for higher currents to keep the heat low.

Nomally the main amplifier as used for voltage could also be used for the shunts, especially for the higher currents. With the still relative low resistance there would be no issue to use an exra AZ amplifier (e.g. OPA189 oir OPA388), but as the JFET stage for the voltage mode is really low noise, there is not real need for this.
For the low currents it is natural that they get slower. A compound version (a little similar to the 2 OP-amp integrator) may be an option if one wants to use an AZ amplifier at the TIA too. This would allow to use a slow AZ OP with 5 V supply combined with a faster FET type to still get a full +-10 V output. This would mainly be a thing if the TIA is also used for slightly larger currents.

[julian1]

Edit. sorry deleted and reposted.  I may have misunderstood Kleinstein's comment. Using larger current resistors, with +-14V may be preferrable.

For the integrator input it looks like the plan is for 40 K at the reference and 50 K for the input - just like the HP3458. This would give an about 14 V FS range, but may result in more gain drift from the switch resistance. I would expect an extra   -1 ppm/K from this. So not very much, but avoidable. It also increases the resistor noise a little over the case with 3 x 50 K or 3 x 40 K. Using a +-14 V ref instead of +-12 V as in the 3458 is the better alternative to the lower resistors for the references.

I already noticed differential heating effects from switch resistance with +-14V and 3x40k in the past.
So it is marginal.
Some ways to address this are - to parallel the '4053 switch which would double charge injection, or drop the ladder voltages - eg. to +-12V or lower.
There are a couple of ways to do the divider ladder.
A 3 resistor divider is simple but doesn't map well into combinations of fixed value arrays (4x10k, 4x50k etc).
A 4 value resistor divider needs gnd current compensation, or else another op to buffer the gnd.

I am tempted to try discrete smd z-foil instead of thin-film arrays, because TC tracking is probably good enough.
They are not generic, however the flexibility to change values and experiment as needed would be really nice. Also inexpensive non-prec resistors can be used for some tests.
Cost is not too different.
Is there a better approach?

Has anyone tried vertical in-line stacking of smd resistors to minimize temp gradients, to see if it improves TC tracking?
z-foil datasheets show a typical TC parabola (Fig 3. vmsp datasheet), but it is not clear in what direction it might shift for individual resistor samples.

[Kleinstein]

Getting a +-12 V reference to get essentially the same configuration as the 3458 is not that attractive. I consider this more like an oversight and strange choice already for the 3458.
It would be better to change to 3 equal resistors (e.g. 3 x 50 K or 3 x 60 K) for the integrator. The resistance of the switches has a high TC (some +6000 ppm/K). Even combined with some 2000x higher series resistors this still contributes some 3 ppm/K. To get good matching for the overall resistance it helps to have the the same resistance. A 20 % difference is not dramatic, but still adds some error to the matching.
The other point is that there is additional noise gain, when the resistors for the references are smaller. So 3 x 50 K is not only easier but also lower noise. With equal resistors at the integrator the reference amplification is easy and can use 4 equal resistors for a +-14 V range reference and some +-13 V range.

For the ref. amplifier the choice of 3 resistors as a single chain or separate gain and inverter is a balance. The version with a single chain adds noise from the 2nd OP also effective to the reference voltage. On the upside it needs less current or could use smaller resistors with the same power consumption. I don't consider it a big difference and either way can work.
The resistors as shown with some 2x10 K at the inverter make about sense. These resistors also add to the noise and OP-amps like the OP27 really like a low source impedance. So I would more prefer somethink like old style OP07, OPA207 or cheap OPA202.

The resistor value at the integrator is a compromise: lower resistors give less noise, but more INL.  I have 50 K as this is available as array. A bit more would not be that bad. The extra noise is like having 2 x the resistance in series to the input signal. The 50/40 K combination of the 3458 has about as much noise as having 3 x 56 K for the resistors and a little more noise from a few other sources. So 60 K or 70 K should still be OK.

The INL effect is 2 fold:
1) self heating of the resistor : here having 40 K as 4x10 K in series helps to spread the power and with good matching this should not be an issue.
2) nonlinear R_on with the MOSFET switches: this is not a thermal effect, but more adding half the voltage drop across the channel to the effective gate voltage. Here the quality of the resistors does not matter. 40 K may still be OK, at least for the start.
If really needed one may mix 10 K and 20 K resisor arrays. The MORN type should fit on a LT5400 footprint, just without the thermal pad.

With 3 seprate resistors the INL part is not about TC matching but about the TC of the resistor for the input. Tracking only applies with rather tight thermal coupling. For the ref. amplification TC matching would still apply. If really needed there are even 5 K BMF arrays in a SO8 case, though I would consider them overkill.

So far the TC matching in the resistor array I have tested (NOMCA and ORN) seems to be quite good. From the gain vs temperature I got better than 1 ppm/K so far for temperature close to roomtemperature. The TC specs are for the whole range including the tricky low value resistors. Chances are the ORN arrays  have a worse TC matching specs than the similar MORN type mainly because the ORN series also includes lower values. The 5 K / 50 K resistors used in the ADC are the easier and thus usually better ones.

[julian1]

Thanks Kleinstein,

I may have got stuck in my thinking, because past tests showed integrator noise correlated very closely to resistor value choices.
Changing from ref=2x40k,sig=80k to ref=2x40k,sig=40k halved the measured integrator RMS noise.
Then changing to ref=2x40k,sig=50k to try to reduce heating, and fix INL, increased noise proportionately.
So the schematic values of 40k and 50k shown were a compromise to juggle noise and inl/heating based on past experimentation, rather than match HP design choices.

But, maybe these results were entirely down to the choice of lt5400.
Switching from lt5400 to morn without other change, significantly improved noise - perhaps so that other factors now dominate.
And this is consistent with your experience.

So it would be good to evaluate higher values - 3x50k or 3x60k .
And using +-14V for references, makes using resistor arrays easy as you note.

[Kleinstein]

Normally the LT5400 should be low noise. A point where the LT5400 is not that good is the extra capacitance to the thermal pad and between the resistors. When fast switching is used this capacitance can add noise. Unless super fast modulation is used this should still not be very much.

With 3 equal switching the natural choice really is to also use equal resistors and than a +-14 V ref makes sense.
The main question remaining is what resistors to use. 50 K works well for me and is available as arrays, which makes it the logical choice for a simple version.
With 3 x 100 K the noise would be relevant and hardly a chance to reach the noise level of the 3458 anymore.
The noise from the 50 K resistors corresponds to some 290 nV for the 1 PLC AZ mode. A significant noise source, but still a bit away from the 500-600 nV noise level of the 3458.
There is a little noise from the switch capacitance that also scales with the resistance, but this should not be very large with the low capacitance LV4053 switches unless swithching is really fast (e.g. >300 kHz). The 50 K / 40 K resistor combination in the 3458 already contributes some 306 nV - so less attractive.

Slightly larger resistance like 60 K (e.g. 3 x 20K) should be noise wise still OK (e.g. some 320 nV of noise contribution).  Already combining a few resistors smears out the heat and each array sees less heating and chances are that matching can be better from statistical averaging. It is not so much the slightly larger resistance, but also less thermal resistance that helps. With the LT5400 40 K = 4x10 K should be OK too due to the low thermal resistance and good matching. The question there is more the U² part from the nonlinear switch resistance - unless the front end compensates for this by using positive and negative readings.

[julian1]

I added a second channel mux/pre-charge switch.
The idea here is to apply the same input switching strategy to alternative HI inputs, to improve 4-phase sample cycles.
This should work for ratio-metric mode (alternate dcv-hi, 4w-hi).
As well as for AG mode (alternate dcv-hi,dcv-source ) and should support an amplifier configuration option using jfets with high thermal effects/walk (if3602 ).
Another possibility would be alternate sampling of voltage and current inputs, although it's not clear how useful this is.

After adding the extra channel, it is interesting to see the extra symmetry created in the input section.
There is the possibility to use the second channel to also mux isolated LO inputs (eg. DCV-LO, 4W-LO) - even just for test purposes.

A further possibility would be to make the gnd-referenced node selectable.
A divider can create a CM node between the buffered boot hi/lo inputs.
And if this CM node is gnd-referenced via a selection relay, a differential voltage-range is avaliable with twice the input range.

If I understand correctly, Kleinstein has discussed this approach, and does something similar,

  https://www.eevblog.com/forum/metrology/diy-high-resolution-multi-slope-converter/msg3827432/#msg3827432

I think LF noise from the channel buffers, will be added when sampling in this differential mode.
But this noise ought to be mostly cancelled by the AZ zero subtraction.
In addition, the mode would only be used/useful when amplifier gain=1.

Does this approach makes sense?

The additional complexity once the second-channel precharge switching/ mux for RM, AG modes has been added, seems low.
It looks like it just needs an extra relay and divider.
And maybe some changes to the input protection.

The question there is more the U² part from the nonlinear switch resistance - unless the front end compensates for this by using positive and negative readings.

A single DPDT relay/or mux could invert the inputs, to support taking measurements in both polarities.
This would ease turn-over tests from external (isolated) input dc sources, and might be justified on the basis that it is a good check for measurement confidence.
But the switching action couldn't be performed per-cycle, without disturbing the inputs, unless they were tapped after the precharge switches.
And then it gets complicated with the gnd-reference.

[Kleinstein]

A second input can make some sense. However for the 2nd input I see relatively little need for the extra MUX in front of the pre-charge circuit. There should already be plenty if input paths available.

I see a limited use for the divider between the 2 guard (buffer of the inputs) signals. The relay to link the the circuit star ground makes no sense as the amplifiers are from the same supply anyway and one would only load the amplifiers differently.

Doubling the range in a differential mode is not linked to having a 2nd input. The idea for doubling the range is driving the low side terminal, so that the ADC can read +U/2 from the input and -U/2 from the low side. So the AZ cycle is not switching between signal and zero,  but a positive / negative type chopping.
The circuit is by using an inverter (with low pass function for stability) from one guard signal and use this to drive the low side terminal.  To have the doubled range also for the other signal one would need to switch which guard signal to invert or have a 2nd inverter and switch after that.  One would still have the doubeld input range only available for 1 input at a time and the other input has to use the protection part (FETs with PV OK for control) to isolate the unused input, as otherwise clamping (and thus more input loading) can happen early. The low side signal would go to the main mux, but no need for a precharge part for the inverter output.

To still have the normal mode available and especially for the amps part it would make sense to have a relay at the low / COM terminal to switch between the circuit ground (as the classical connection) and the driven low side from the inverter.  If there is no extra protection at the inverter output one would also need isolate the current input, which would be a 2nd low impedance path. So the relay should switch both COM and the current input.
The idea for protection is to have only 1 unprotected path - classically ground, but it can be another low impedance signal as well.


In the current amplifier configuration (amplification relative to ground) the differential mode with the driven low side is mainly useful for a ~20 V range. Already with an amplifier gain of 10 and thus a 1 resp. 2 V range the inverter to double the range is a 2 sided thing: it still doubles the range and can help with INL, but the noise of the inverter is relevant. So the 2 V range would be possible, but more noisy than the 1 V range.  The noise of the inverter enters with the same frequency band as the main amplifier (e.g. around 25 Hz for 1 PLC operation). It is not so hard to make the inverter lower noise than the ADC and accuracy of the inverter is not critical. Still the main amplifier is usually lower noise than the inverter (from the resistors alone).
My current configuration (in the link to the other thread) is a bit different and needed the AZ type main amplifier.

With the extra inverter to double the range the ADC alternates between U/2 and  -U/2. This helps with even oder INL contributions, but is still not a turn over test, as it depends on the quality of the inverter and the ADC offset. The inverter is still not that critical as even a case with +0.6 U and -0.4 U would still suppress the even order errors quite well and not reduce the range very much.
One gets a limited INL test by comparing the result in the classical 10 V mode and differential mode. E.g. with 10 V at the input one has 10 V and 0 V compared to some 5 V and -5 V.

To support a turn over test and also the more general sum of 2 voltages type one could add switching for a choice of 2 low side terminals and than also use the 2nd input path. For the turn over test one has then U1+low2 and U2+low1 externally connected in parallel.

[Echo88]

Can you show us some photos of your prototype julian1?

[julian1]

Can you show us some photos of your prototype julian1?

Here is a pic of the current old board, which should give a sense of the layout/design.
The decoupling and digital control are mostly on the backside (not shown).

The license is open source gpl 3 or cc by-sa 4.
For any future revision I will add better creative attribution, and properly reference this eevblog thread as the source of community design ideas and discussion.

A note about the layout -
I couldn't decide what configuration I liked - a traditional-style DMM or datalogger, so it is kept open for extension.

The lhs ER digital/mcu section is enough to do stand-alone datalogging with usb-cdc for comms, SMA for ext-rigger/meas-complete, flash storage, and rtc for data time-stamping.
But this is optional, and the headers at the isolators, would support a UI control-panel board and features - buttons, lcd/vfd, buzzer etc.
A mcu/rasperry pi/beaglebone - anything with spi would also work if the code was ported.

[julian1]

A second input can make some sense. However for the 2nd input I see relatively little need for the extra MUX in front of the pre-charge circuit. There should already be plenty if input paths available.

Thanks, your comment prompted the realization that dcv-hi is common to all dcv/ohms AZ readings, as well as readings with a second hi (dcv-source, 4w-hi), so it makes sense to give it a dedicated pre-charge switch, and without the extra mux in front of it. the mux in front of the other pre-charge switch can handle other inputs.

In addition, removing this mux eliminates it as potential source of leakage, especially on the most critical input paths.
So it is a very good simplification.

I see a limited use for the divider between the 2 guard (buffer of the inputs) signals. The relay to link the the circuit star ground makes no sense as the amplifiers are from the same supply anyway and one would only load the amplifiers differently.

I need to go through the details, to properly understand how differential mode works.
It suspect there are enough moving parts already to test.

[Kleinstein]

The 2nd input allows to use some kind of differential mode, be measuring the difference between the 2 inputs. However under most conditions this does not come with an extended range. It depends on where the test circuit and meter circuit are connected with a more low impedance link.

To extend the input range one needs to shift the connection to have one signal positive and the other signal negative. The easiest way for this is to get back to the more normal case with only 2 links from the DUT to the meter and the low side shifted to the negative of the input instead of the classical fixed meter ground. Reading the low side does not need extra protection or precharge, as it is a low impedance signal driven from the meter side.

I see still 2 options for the driven low side.
1) Use the same COM terminal and switch between the driven low side (and the current input isolated) and classic COM=ground.
2) have the driven low side in addition to the COM and current terminals and than have additional protection (current limit to some 1 mA). This would allow to use the terminal also as a voltage output, e.g. for a reference voltage or high ohms test.

[julian1]

With less resources at hand for doing calibration like checks, there is justification to have an expanded set of self-tests to validate behavior.

For turnover tests - I expected to use a separate pcb board, having a true isolated voltage source, and relays to invert the voltage source to be applied to the dmm inputs.
But perhaps a simple on-board cap, switched by a DPDT relay could achieve the same thing.   
So the cap would first be connected to the gnd-referenced on-board dcv-source by the relay to get the reference voltage.
And then disconnected, and reconnected at the input - in both polarities for the readings.
My initial thought, is that a relay would be better than a mux/ltc1043, to completely avoid charge-injection offsets, during the connect/disconnect cycle, and because there is no demand for fast switching.
But depending on the cap size perhaps a mux would also work.


Similarly for quasi-INL adc tests - performed by sweeping the charge-voltage on a PP cap over the input range, while perturbing the adc runup parameters.
This was previously done with a separate pcb board - with relays and to mount the physically large (20uF) PP cap.
But perhaps the sweep could be managed with muxing on the 10nF accumulation cap (C410).
The previous leakage tests show that drift is probably low enough.
It just needs to be stable enough to take two consequitive adc measurements at each voltage point.

[julian1]

Scratch the idea using the 10nF accumulation cap as switched capacitor. I had units, uV and mV for leakage drift confused. But perhaps a board level 1uF PP cap might be physically manageable and could be added to the board.

Edit. actually 6.8uF PP is manageable.
for the turnover test, and to transfer the charge from dcv-source to the input, it might be necessary, to switch a few-times, to overcome the capacitance (protection, muxes) of the input section.

[Kleinstein]

For the INL test an external relay could be an option, but it could also help to have control over it, either directly or just a sync signal.

Instead of the simple turn over test, one could consider the more general sum of 2 voltages version. This needs 2 separate DT switches. 2 inputs could substitute 1 switch and 2 low side paths also the 2nd switch. Here especially the case with 1/2 the voltage is interesting as it is a bit easier too look at the result. As an additional advantage over the simple turn over test one also includes a check and compensation for the meters / switch offsets. The 2 extra readings allow a more accurate turn over test for the ADC than just a single relay for a polarity reversal.

The external part would need a low noise short time voltage reference for 2 connected voltages, ideally with several values to choose.
 A simple version could be a chain of batteries (e.g. 8 x 1.5 V) and connectors/switches to choose different points to connect. The external ref. part needs to be isolated and separately powered. So it could well be an external unit. To make the test work well it may need quite a few repeats (at least if the references are noisy) and automation can help with this and avoid thermal EMF from handling the cables.  A fixed speed also allows to compensate for drift better. With a low noise reference manual switching may still be an option for a first test. I don't see a need for very many test voltages and the choice of which voltage to use could still be manual.

Using a capacitor for the turn over test could be tricky and at least require a large capacitor, as parasitic capacitance can pump out some charge and effect the test. One may have to do the test with different capacitor sizes, e.g. 2 capacitors in parallel and options to disconnect on both ends (e.g. with jumpers). It may need quite some care and still the capacitance or manybe thermal EMF at the switches as a possible source of error.

For the slow drifting test voltage the 10 nF may be a bit on the small side. With 10 pA if leakage this would still be 1 mV per second or 3.6 V per hour.  For may tests I liked it usually a bit slower, more like 1 V per hour. Ideally one wants to look at the critical regions with even mode details / lower speed.  It may need a bit extra averaging and not just a single 1 PLC conversion to the the short range INL errors tested with this method. One is hoping for errors < 0.5 µV and this is about the RMS noise for a single 1 PLC conversion. So one should have more like 20-100 averages per point.

Another test that comes naturally is using the ACAL procedure with additional test voltages, like +1 V and -1 V for the 1 V range gain. Ideally the gain for the x10 gain step should be the same from both tests. The difference gives a hint on the liniearity of the ADC and gain stage combined. The extra test voltages make a relatively fast self test and via averaging also alow to average out some of the INL error to get a more accurate ACAL result for the gain steps.

[julian1]

A quick update,

One goal for a new board, is to change the copper features to improve the input switching parasitics, based on the previous experiments.
The design now features traditional ring guards wherever leakage needs to be controlled.
As well as a copper fill at BOOTIN potential, underneath the AZ mux, and surrounding the azmux node and amplifer jfets, to reduce capacitive loading.


Leakage
Input leakage can be tested by first charging 10n cap for 10sec, then turn off azmux and observe leakage by sampling boot.
leakage looks very controlled.

    > reset ; dcv-source 10; test05
        0.57mV 0.54mV

    > reset ; dcv-source 0; test05
        0.7mV 0.8mV

    > reset ; dcv-source -10; test05
        1.2mV 1.1mV.


Precharge switching,
Change injection is constant at different input bias voltages - as expected due to the switch bootstapping.
This can be improved/trimmed, by lowering the supply voltage on 4053, and trimming VEE relative to BOOT, with a bipolar current source.
But I haven't bothered for the moment.
Accumulated charge injection, nplc 1, on 10nF for 10s, using lv4053,

    > reset ; dcv-source 10; nplc 1; test14
      6mV. 6.4mV

    > reset ; dcv-source 0; nplc 1; test14
      7.2mV  7.2mV

    > reset ; dcv-source -10; nplc 1; test14
      7.8mV 7.6mV


Normal Az switching,
The copper fill at BOOTIN (copying the AZ input voltage), under the azmux works to suppress the capacitive loading of the switch-node output.

    > reset ; dcv-source 10; nplc 1; test15
      5.0mV 4.95mV

    > reset ; dcv-source 0; nplc 1; test15
      7.5mV 8.2mV

    > reset ; dcv-source -10; nplc 1; test15
      8.15mV.
 

Board has two distinct input channels, with separate pre-charge switches.
So four-cycle RM and AG (to compensate thermal walk of a high-gain amplifier) functions are possible,

ratio of ref-hi, 10nplc, sampled on two separate channels,
ratio, 3 of 4 meas 0.999,999,9 mean(10) 0.9999999V, stddev(10) 0.06uV,
ratio, 0 of 4 meas 0.999,999,9 mean(10) 0.9999999V, stddev(10) 0.06uV,
ratio, 1 of 4 meas 0.999,999,9 mean(10) 0.9999999V, stddev(10) 0.06uV,
ratio, 2 of 4 meas 1.000,000,1 mean(10) 0.9999999V, stddev(10) 0.07uV,
ratio, 3 of 4 meas 1.000,000,0 mean(10) 0.9999999V, stddev(10) 0.07uV,
ratio, 0 of 4 meas 1.000,000,0 mean(10) 0.9999999V, stddev(10) 0.07uV,

[julian1]

For sum-tests,
I spent quite some time trying to get an arrangement with two series 10u film caps to work.
This included a bunch of over-engineered muxing - for cap selection, and polarity, and to be able to charge to different spot voltages.
But I couldn't avoid a constant leakage of -2uV/s likely to the negative rail (probably due to 0.65" ssop dpdt mux package).
In the past I used relays, but that would be too cumbersome with multiple relays needed

To try the battery approach,
8x 1.2V enneloup batteries in a battery-holder with taps, switched manually
Method - is sample AB for 10 readings, 10nplc, then BC (bottom half) , then AC (series ), take the means, and calculate the diff/delta.
repeat 5 times.
eg. diff = 4.8V + 4.8V - 9.6V


After reducing resolution, change series rundown bias-resistor from 220R to 1k. and new cal.

> data cal show
Matrix: 3 by 1
row 0:     17.4986934
row 1:    -17.9358312
row 2:   -0.458200302
model_id    0
model_cols  3
stderr(V)   0.86uV  (nplc10)
res         0.115uV  digits      7.94 (nplc 10)

4.8
diff -3.50uV
diff -5.12uV
diff -4.66uV
diff -4.04uV
diff -1.76uV

2.4
diff -5.39uV
diff -4.11uV
diff -3.88uV
diff -0.94uV
diff -3.44uV

7.2
diff -5.95uV
diff -2.77uV
diff -3.09uV
diff -4.99uV
diff -2.00uV

3.6
diff -4.51uV
diff -6.62uV
diff -5.07uV
diff -4.34uV
diff -1.98uV


6.0
diff -8.43uV
diff -7.10uV
diff -3.93uV
diff -7.28uV
diff -2.49uV

6.0 repeat.
diff -8.09uV
diff -4.13uV
diff -3.95uV
diff -3.43uV
diff -4.59uV


1.2
diff -1.94uV
diff -2.22uV
diff 0.08uV
diff -2.07uV
diff -4.10uV

8.4
diff -3.94uV
diff -1.96uV
diff -2.35uV
diff -2.66uV
diff -2.43uV

I've only just got this working, and am not quite sure how to interpret the offset.
Probably it would be good to try the negative polarity, and I would like to experiment more with a two-variable weighting model for the adc reference currents.

The board includes footprints for 8, and 10pin mdacs, for creating +- spot voltage and these are working,
The idea here was to test inl in a sum-type ratio mode, through a polarity flip.
But I forgot to add a resistor divider, which would need to be bodged.
And I don't like the idea of lower-impedance source, as one cannot buffer the divider since the buffer Vos will not invert through the polarity mdac reference voltage flip.
The mdacs look to be reasonably low noise as far as I can tell - cannot see much above the reference noise.
So the mdacs may be better for drift like INL spot tests, where the adc runup parameters are perturbed.

[Kleinstein]

The input leakage and average current from charge injection looks really good. Also the input inpedance / conductance looks really good: some 2-3 pA of change in the input current when going from -10 V to 10 V would be an input resistance in the 10 Tohm range and this is even with 1 PLC mode. It is cool to have some kind of self test for the input leakage.


For the sum test it would also be good  to include a 4 th measurement (BB) for the offsets. The BB rading would be subtraced from the result.  This way one has the low side at A and B twice each and the high side at B and C twice each and int the resut each point once positive and once negative. This should give a quite good compensation of offsets (e.g. from the protection part).

For the sum of 2 voltages one needs the test voltages to be floating to have the ability to connect the center point to the low side (GND) for 2 of the readings. This makes is tricky to use the same reference nad DAC. One would need some charge pump floating capacitor system (like the 10 µF film caps) or similar system with current source and series of resistors. One than still has the problem that the error can be from the ADC or the charge-pump (or current source output resistance). With the capacitor the issues are leakage, switch charge injection and also parasitic capacitance that can pump out some charge.

The result from the sum test still show quite some scattering. Part of this may be from drift in the battery voltages. At least I see this as a weak point with batteries. The dift can give a systematic error and just simple averaging is not enough. One can compensate at least for the linear drift part, by interpolation to the same time from more readings in a row.
 
Depending of the voltage reference used (especially a LM399) there can also be an error from popcorn type jumps in the reference voltage. Here just averaging over enough reading could help.

With the scattering and possible error from drift of the battery voltages it is hard to say what the results mean.

[julian1]

Here's a sum-test plot in both polarities as baseline.
The measurement readings are interleaved somewhat to reduce the scattering.
BB is plotted as a control, but is not subtracted from the diff because the magnitude is too small to be consequential.
I thought I would try to deal with the simple case first - and the input test voltages are from a dedicated pin header into a mux, that bypasses protection.

There is a fairly distinctive shape, dependent on input voltage.
I still need to tidy/fix a few things - LC after the switch and before the integrator etc.
Ref currents are signal=50k, ref=40k,40k, so there's some opportunity for differential TC effects on the ref-current switch.
So probably a good test is to try and equalize to 50k,50k,50k or similar using jumpers.
I have a small test-pcb, with a floating/isolated mdac/divider, but it had a few issues, so the present focus is with batteries.

[Kleinstein]

The residual offset for the BB readings is small and as usual also relative constant. It may get larger and more temperature dependent if more protection is included and than the BB reading could correct most of the added error from the protection and switches.
The difference looks OK. The worst case is at some 3 µV or 0.3 ppm of the 10 V range.
For a smooth INL curve the difference is somewhat larger than the INL error, suggesting and INL error in the 0.2 ppm range.

From my last tests the differential TC part does not seem to be that bad, at least not with ORN resistors. At least it is a rather slow effect. So one can tell it apart from the slow response.
Changing to all 50 K would likely not help much with the INL, but it could help with the gain TC. From a crude estimate I would expect a slightly ( ~ 0.5 ppm/K) more positive gain TC when using all 50 K resistors. So the change is in the scattering range due to the resistor TC.

[julian1]

I was watching Fesz' youtube channel recently, where he demonstrates some interesting experiments looking at shielding techniques to suppress electrical and magnentic emi.
For electrical (versus magnetic) emi, the shield needs to be grounded to avoid coupling which can make the situation worse.



Furthermore, the experiments show a difference between a shielding plate that terminates to a single-point ground connection (7.54min), versus one that terminates along the full width of the edge (10.06min).
EMI suppression improves considerably for the "full ground connection all around" low-impedance gnd (at RF frequencies), versus the single point-connection.

The implication for pcb shielding cans, is that they should make an electrical connection along their edges to a pcb ground fill.
Or as a practical manufacturing compromise - make staggered connections along their edges.
One sees this kind of arrangement in sensitive RF designs.

Perhaps an interesting option here might be Harkin style clips, these are SMD components that can be soldered to the board.
They then grab and make electrical connection to the can.
The advantage, is that it is possible to quickly fit/remove the can, and without requiring a permanent soldered joint.

https://www.mouser.com/ProductDetail/Harwin/S1711-46R?qs=93uzuGORGqc8FyLhIh5ctw%3D%3D

Both 3458a, and k2002 have outside chassis enclosures, as well as a second inner shielding enclosure. For both top and bottom.
The 3458a has an additional (3rd plate) over the top of the adc.
It is hard to tell, but from watching teardown videos, it almost appears the k2002 black inner sheet-metal shield, may be floating/and not connected to chassis gnd.
So perhaps the shielding demands are not as high as supposed.

In terms of layout - it is possible to think of several options - one could have a shielding-can for the adc/refs, and another for the zero switch/muxing/amplifier.
Since the adc has some switching frequencies, a dedicated can/enclosure may make sense for emi egress.

Alternatively a single inner cover (like k2002) for all the analog parts of the pcb could be done, (eg. excluding digital/ hot regulators, and accessibility for fuses, input connections etc.) .

[Kleinstein]

Ideally one would have 3 layers of shielding, just like with the 3458.  The inner most is at the circuit-ground (ADC and amplifier). The next is connected to an external guard input or (via a switch) to the low side input. The outer shield is the case, e.g. connected to PE.  The guard part is normally considered mainly for the low frequency part (e.g. mains) - so here a single connection and not perfectly closed shield is OK. The switch between internal and external guard is already a single connecting point anyway.
Chances are the balck shild in the K2002 is more like the guard. It should be connected to something and not float. Otherwise it would only be for thermals. A shield will definitely also effect the thermal environment. The block color could be to get more radiative coupling.

Ideally at least one of the 3 layers would reject RF frequencies too. This would be difficult with the case. For the shield to be effective against RF all the wires / lines going in would need RF filtering. This is easy for mains / power and the data connection, but tricky with the measurement inputs. An inductor is easy, but one would not want capacitance to the case (e.g. PE) for the signal inputs.
A similar problem is with the guard, though a little capacitance could be OK. The guard part may not need to go to the PCB at all.
So the logical way would be to have the inner shield(s) RF tight.  Here I would ideally have it separate for the amplifier, ADC , the FPGA/µC and DCDC part. The linear voltage regulators may not need a shield. The inner shield should present only DC voltage towards the guard part. Otherwise AC voltage, e.g. from the DCDC converter part could couple to the guard. So there should be some inner shielding also at the DCDC converter part.

[julian1]

Thanks Kleinstein, that is extremely helpful.
The emi environment is much worse today, with all the switching supplies, than when the 3458a, k2002 were designed - so it makes sense to take care where feasible.

The guard part is normally considered mainly for the low frequency part (e.g. mains) - so here a single connection and not perfectly closed shield is OK. The switch between internal and external guard is already a single connecting point anyway.

To focus on just the Guard shield for a moment,

There is currently a provision for an external user-guard connection at the front/rear terminal gang-switch.
It is routed (with protection to PE) to the input power connector, for connection to the inner-shield of the power transformer (if available).
There is also the option to connect straight to internal star-ground.
The choice is currently static - and made with jumpers.

This guard net should be used for a guard potential shielding assembly over the pcb.

But I think a relay is needed to cover the cases to avoid leaving it floating -  Eg. a relay to switch between internal (eg. star-ground) or external user connection.
(I think I had a relay in a past schematic revision, mostly because I couldn't envision the measurement or validation scenarios where it might be useful).

[julian1]

Ideally at least one of the 3 layers would reject RF frequencies too. This would be difficult with the case. For the shield to be effective against RF all the wires / lines going in would need RF filtering. This is easy for mains / power and the data connection, but tricky with the measurement inputs. An inductor is easy, but one would not want capacitance to the case (e.g. PE) for the signal inputs.

Using an outer enclosure shield for RF appears to be the strategy of the 3458a. Eg. the signal input DCV gets filtering of 2x RC 5k/82p

Some things that might help reduce the parasitic capacitance to the outer enclosure could be -
- plastic housing for the input jacks/connectors. (issue of RF ingress, but maybe there is a compromise point)
- beads on input wiring.
- a shield sleeve around the inputs wires.

If pcb board cans were attempted for RF, then there is still the pcb gap between top and bottom can.  (although PTH copper slugs could help fill),
And there would appear to be many more inputs and outputs, depending on which circuits are chosen to be inside/outside the demarcation.

As a practical concern I suspect the ease/difficulty of sheet-steel manufacturability for custom cans versus full-enclosure is about the same.

[julian1]

Considering the approach of using sealed-cans at circuit ground potential for RF, I noticed that two-piece "frame and lid" style cans are available.

The advantage with the frame is that it can be soldered around the perimeter, but since the lid is detachable, one does not lose access to the board/components.
They would make a much better seal versus using retention clips.

The top and layer/bottom pcb layers could be flood filled, for the attachment pads.
And for soldering, perhaps mild-steel sheet can be pre-tinned with a hot iron.

What doesn't work though is the layout, since the TH filters for 4W, are some distance from the input muxing/amplifier.
Likewise the inductance/ optional capacitance for DCV input is placed with other TH protection parts / and HV pcb cutouts.
So these would be outside the cans.

But perhaps they would still be worthwhile as an additional measure.

[Kleinstein]

A few THT parts would not be that bad. The capacitor to ground would be grounded anyway. A few small solder joints on the outside are also not that effective an antenna to pic up much RF.
The bigger issue may be the clearance for high voltage at the very input. The protection part wants clearance and ideally also a thermal shield, which is a bit tricky combination.

The input protection may be OK outside. The MOSFETs, when turned on or off all the way should not be that susceptible to RF interference. The clamping part and fast turn off opto-coupler are howerver a bit tricky. This would add a few more lines going in /out of the cans.

[julian1]

I don't see a way to use RF cans around the HV section given clearance needs, or else forcing very large layout changes.
But maybe that is just the trade-off if a full Farraday like enclosure is not used.
Preserving the functional standalone module nature of the design, independent of enclosure choice would be nice.

I purchased some inexpensive electric and magnetic near-field probes and wide-band amp, for the scope in fft mode.
Not sure if they will help to draw conclusions about shielding strategies.
But it could be interesting to experiment, particularly for internal switching voltage and current sources - isolators, cmos xtal oscillator, adc, transformer.

[Kleinstein]

It is probably OK to have the protection part outside the cans. For the amplifier and ADC part a can could be nice. Here amplifiers may react to RF signals, though already the ground plane (even of at the back) can to quite a bit for shielding.  For me shielding is still a bit of RF magic, open to surprizes with things that may look good and still fail.

[dietert1]

Some days ago i had a look at the TI ADS125 delta-sigma ADC datasheet. In the recommended application schematic fig. 98 they already show four 47 Ohm damping resistors for the SPI lines. Nowadays that many MCUs chips produce sub-nanosecond risetime signals this may be a good thing to do in mixed signal designs. Also depends on the trace lengths.
Imagine EMI suppression as an attenuator made of a low impedance close to the receiver and a high impedance close to the emitter.

Regards, Dieter

[julian1]

I should add resistors for the the output of the isolators (it's a tradeoff with routing space). I think Imo made the same point.
They are modern low-voltage parts designed to switch as fast as possibe, since bandwidth is the usual criteria being looked for.

The nice points, are that one can choose either capacitve or magnetic parts.
And because they are fast, the adc counts are transferred quickly during pre-charge phase, or during a reset, when there is no measurement sampling.

I scanned the datasheets, but I am not sure if the internal data-encoding scheme means they are still switching/sending data continuosly across magnetic/isolation barrrier,
even if there are no changes to user-facing input/output state.

So I am a bit curious to find out if they are emi emitters.

[CurtisSeizert]

I apologize ahead of time for the long post. I am still getting caught up on this thread, but I have some observations on EMI mitigation strategies from my nanovoltmeter project that may be helpful. Because the power source is a battery, it was necessary to generate the primary rails fed to LDOs with two buck converters and a Cuk. These went in on a daughter board with an Orbel Lazerlok shield over most of the PCB.  The bottom of the daughter board sits about 8 mm above the plane of the top of the main board. The shields on the main board are Laird BMI-S-210 (for the input stage) and BMI-S-230 (for the ADC and associated signal conditioning block). Both of these shields have non-perforated covers, and that was important in this application to be able to use them to mitigate air movement around sensitive nodes. I have also used shields with perforated covers when the sizes don't work out otherwise and put tape over the holes, but that looks a little how ya doin' (as Dave would say). Both of the shields on the mainboards have identical shields on the bottom side because both sides of the main board are populated. Only one side of the SMPS board has components on it (except for the TH connector). The shields on the main board have vias on each land to ensure a low inductance connection to the ground net.

Regarding the shields themselves, the Orbel shields are definitely much higher quality and are cut from thicker sheet. With the Lazerlok shields, there could be issues because they make contact all the way around. You could in theory change the footprint to be able to route signals on the layer with the shield, but that is putting some trust in the solder mask integrity as an insulator. They also cost a lot more than the Laird shields - about 5x as much with both the frame and cover costing $10-15. The covers are also stiffer and take some work to pry off without flexing the board. Between the two Laird shields, the BMI-S-230 is nicer, and the lid is pretty easy to snap off, which is a helpful feature on prototypes.

The performance of the shields on the boards is quite good. I have used a sniffer probe made with five turns of magnet wire amplified 25x with two ADA4896 stages (about 30 MHz bandwidth) to get a qualititative feel for EMI around the board. I could not detect any peaks due to the SMPS in the spectra I took with the cover on the ADC portion (which required some bending to get the probe in). I determined which peaks were due to the SMPS by comparing spectra with the board powered with the SMPS with spectra where the board was powered by a bench supply. The probe was located above U34 in the middle of that shield. There is quite a bit of noise directly under the SMPS board (probe was close to C20 at the upper right corner of the ADC shield). I think this is due to pulsating ground current from the switching of the Buck converters, and some of this current was likely flowing on the bottom layer.

Mains hum is not completely suppressed in measurements, with the size of the peak being dependent on the measurement conditions. With an internal short (from one of the relays in the top left), the peak is about 20 nV/rtHz. For the front panel connector, I switched from Pomona low thermal EMF lugs to LEMO 0S circular connectors with a shielded twisted pair cable, and that helped both for reducing mains hum and low frequency noise, the latter likely from transient thermal EMFs. I had some issues with intermodulation products between the mains hum and the chopper switching frequency aliasing down to low frequency with a simple block averaging filter, but I haven't implemented the feature to synchronize with powerline cycles. I was able to fix this without synchronization by changing to a cascaded integrator comb filter, which only required another six lines of code and a few 64-bit accumulators.

I placed the op amp and current sink for the input differential pair composite amplifier outside the shield because they are the biggest power dissipators, and this doesn't seem to be too problematic. The inputs of the op amp are are fairly high impedance nodes (about 70k each), so they are susceptible to electrical field coupling, but the discrete stage of the composite amp operates at very high gain in this design and the impedance of the inputs is balanced, so it is not too big a deal. I do see some switching residue in the analog outputs of the input stage, mostly from the ~10kHz burst mode operation of one of the LT8608S switchers.

There is some EMI from the MCU, but those peaks are not visible under the shields. All the fast switching lines like the SPI busses and UART have 33R resistors and 50 ohm traces (based on guesses about the output impedance of the driver circuitry). The digital section is all 1V8 to reduce power consumption, reduce EMI, and avoid level shifters with the ADC IO. With the STM32U575 drivers, the edge rates are not particularly fast at this voltage even with the HSLV bit enabled. There is a clear difference in rise time between the AD4030/AUC glue logic outputs and the MCU outputs on a 100 MHz scope, with the former being faster. There a number of signals to mod/demod switches that operate regularly during conversion with 100R resistors and thinner (but not 100 Ohm) traces. I don't see these as big EMI risks because they all switch during dead times in the conversion, which is presumably the case for all the designs in this thread with similar switches for autozeroing.

For the stackup, I used a 6-layer 1.2 mm board with the JLC2116 stackup. This was a compromise between keeping layers close together for low susceptibility to EMI and keeping them far enough apart to minimize parasitic capacitance on some feedback traces. Top and bottom were signal with some ground pours for thermal reasons, and layer 3 (In2) was power. All the others were ground. The 1.2 mm stackup keeps layers 3 and 4 relatively close (about 0.22 mm). I used 1 oz copper on all the inner layers to reduce the impact of any uncompensated ground currents.

Overall, this works pretty well. I do see some issues that seem to be from thermal gradients across the relays, but these are single digit nV effects at their worst and subnanovolt effects when conditions are well controlled. I would probably use a similar strategy for EMI mitigation if I were pursuing an 8.5 digit design with the inclusion of a guard shield between the case and the board (as Kleinstein suggested). I did not have room to include that and still fit everything (including 4x21700 batteries) in a Hammond 100x160 mm extruded Al case for my design, but I have considered the idea of changing cases if I were going to make a revision. I would also be using a lot of antialiasing filtering, something like a six or eight order Bessel filter with fc of about 0.1x the Nyquist limit with an AD4030. I think that a strategy like this (or using an integrating ADC of some description) would help with EMI-related woes because the cross-section of the circuit where it could prove problematic is much smaller. Oh, and one weird effect I noticed was despite powering the circuit with batteries, I needed a CM choke on the input to avoid odd behavior when connected to various sources, including a change in the offset voltage when the inputs are shorted internally. The case for my design is tied to PE through the USB shield during normal operation, so it is possible that an inner guard shield would mitigate such an effect.

I have a couple other general comments about things I saw elsewhere in this discussion. I agree with Kleinstein on the point of multiple parallel or series buried Zener references at this stage in the design cycle. It seems wasteful. For expensive components, I would prioritize good gain setting resistors because those will be crucial for achieving good linearity unless one is implementing some sort of continuous gain calibration faster than the thermal TC of the gain setting resistors or another way of dealing with power coefficient nonlinearity effects. I saw a reference earlier earlier to a substantial noise voltage using the JFE2140 JFET pair at the input. I have used a lot of these, and from what I can tell they have (probably) the lowest 1/f noise corner of any discrete JFET. I have attached a spectrum I took and a schematic showing the measurement conditions. The -3dB bandwidth was 13 mHz to 10 Hz. RMS noise for the DUT (uncorrected) from 0.1-10 Hz was 7.62 nVRMS with a capture of 4M samples at 200 SPS. The noise for each individual FET would be a factor of sqrt(2) less. I have a spectrum somewhere with the -3dB down to 10 mHz, and I think the NSD was about 25 nV/rtHz at the low end there. I spent some time investigating this, and the datasheet measurement setup for capturing noise spectra is pretty bad for low frequencies as the current noise of the OPA210 makes the 1/f corner appear higher than it should. I believe the gain also rolls off before 100 mHz in the datasheet setup. I have taken long captures of three parts for the JFE2140 like this, and there was almost no detectable scatter between parts. The LNA used to take this measurement actually uses 16 of them in parallel and gives a consistent SNR down to below 100 mHz, where input AC coupling filter noise noise (and some other sources) start to come into play. The SNR is near the theoretical 12 dB, so the parts I measured don't appear to be standouts. Another nice thing about this part is the gate leakage current is quite low. I use a Vds of 1.4V for my LNA with 400 uA drain current per FET and get a total of 2.7 pA, so <200 fA per FET.

I realize a lot of this information is anecdotal and qualitative, but I hope it can be helpful nonetheless.

[julian1]

Hi Curtis, thank you very much for your detailed comments.

I wanted to ask, if you use COTS or custom RF cans and how you route the land vias, in the nanovolt thread, but didn't want to pollute the discussion with mundane detail.

In your research - did you find any makers of (fence and lid style) RF shields who can manage custom dimensions, in prototype quantities?
I should search on the manufacturers you list - Orbel, Lazerlok, Laird  to see if they offer custom services.

To improvise - I did a Freecad step/dxf model for 0.8mm mild-steel sheet, and had it fabricated to try to prove the concept.
This approach should be OK for the larger LF magnetic (and thermal) guard cover, but is the wrong thickness for a rf-can.
I found a source of pre-tinned (for solderability) mild-steel in 0.2mm and 0.3mm thickness, but need to find a (local) service who can cut and fold the thinner metal.
Being able to pop the lid for access is probably needed as you note.
At this point, there's a trade-off between money spent on custom fabrication, versus extra time routing the pcb to accomodate fixed dimensioned parts.
The simultaneous aspect of mechanical design is a challenge.

The performance of the shields on the boards is quite good. I have used a sniffer probe made with five turns of magnet wire amplified 25x with two ADA4896 stages (about 30 MHz bandwidth) to get a qualititative feel for EMI around the board.

Using EMI sniffer probes and then doing experiments, switching between a bench supply and DC/DC converter is a really good idea.
Perhaps small electric and/or magnetic probes could be made a permanent (pcb) feature, that remain under the RF cans?
So the probes would route and present to a DUT connection header outside of the shield can.
I purchased a set of near field probes to try to get a bit familiar with doing EMI tests, but there's no way to use them with the cans fitted.

For the stackup, I used a 6-layer 1.2 mm board with the JLC2116 stackup.

Are there advantages in using JLC2116 versus other stackups, or even a basic manufacturing stack-up?
It seems like a good thing, if everything is well defined from a manufacturing pov.
Perhaps routing the fast digital signals (spi, adc control) with controlled impedance might reduce radiated emi, even if there are no timing/reflection needs.
For the dmm board, there are inner and outer layer grounds to shield (capacitive, magnetic) mostly orthogonal traces.

For the amplifier there are soic-8 footprints for jfe2140, and lsk389.
There is also a footprint for if3602.
I noted your comments about the thermal wander of the if3602 from the DIY cascode jfet lna thread,
So there is a 4-cycle sample acquisition sequence, that can measure and compensate the amp gain, against a small reference-voltage.
But use of if3602 is more in view as an alternative configuration like HP 34420a, rather than a general DMM and is not a priority.
Following Kleinstein's suggestion, I did some Allan variance noise tests with the jfe2140, posted in this thread, but still need to do it for the other parts.

I don't remember the numbers, but in a separate LNA project that I modeled a lot after your initial discrete jfet LNA design, I found lsk389 to be lower noise than jfe2140, but higher leakage (to be expected).
But shielding really needs to be improved first to gain confidence.


For supplies - at least for a first pass - I want to see if the design can be managed without dc/dc converters - and AZ ops for that matter.

I believe Shahriar Shahramian uncovered issues with the DMM7510 - even with the super low-coupling transformer used in that design.
I suspect fast voltage transitions on the rectifiers are a problem.
Adding LC filtering after rectification re-introduces coupling capacitance on the inductors.
So power supply issues are pushed-out as separate scope.
As fallback, I have a simple open-loop fixed-freq. push-pull, and resonant llc with zcs to test on a board, but they are a bit basic.

So for a power supply at the moment - the board can run with a scavenged 34401a mains-transformer (power input headers are designed to match).
Although this transformer is inadequate - with higher than expected coupling-capacitance and lack of a proper screen guard.
I did an experiment stuffing a small sheet of copper, between the two bobbins of Bel signal transformer, as a makeshift guard.
And this already works to reduces coupling (3x reduction from memory) better than the 34401a transformer, so it may something to explore.

If EMI can be measured qualitatively following your approach - with some sniffer probes. then trying out different supplies should be more of an option.

[Kleinstein]

For a normal DMM the noise of the JFE2140 should be well good enough.  There is often more noise from the protection part and other resistance. Another noise source are the gain setting resistors.
It is only for a nV meter with ranges below 20 mV that the JFET noise is really an issue.

Using a 3 or 4 conversion AZ cycle to also measure the amplifier / ADC gain for each cycle is possible and it is done with some meters (e.g. Keithly 19x). However the time lost for the extra steps adds to the noise / reduces the reading rate.  Good resistors for amplifier gain would make things easier. The resistance is a compromise between thermal effects and noise from the resistors.

For custom size shielding cans there is also the option to start with a standard size and cut and bend by hand to get a smaller size.

For the DMM the main point for EMI is a signal from the outside effecting the DMM circuit. Emissions may be an issue with the common mode part though. Here the old style 50/60 Hz transformer may not be that bad. With a low power design battery operation is an option too, even if this likely need some SMPS to get the different voltages.

[CurtisSeizert]

Julian - it is my pleasure. This is a very interesting project that all of you are putting a lot of effort into and doing a great job of documenting.

On routing the vias, I just put them in the pad itself and connect to the ground planes. With 6 layer, as you probably know, JLC fills the vias for free, which opens up via in pad as an option, which is nice. All the shields I used were stock at Digikey. I fully acknowledge that finding a stock part with the right dimensions to fit everything you want is a PITA. Also, I would say pollute away with seemingly mundane details because sometimes mundane just means consequential but easily overlooked.

I did not look into getting custom cut and bent sheet metal for RF shields. I could be wrong, but I would think that the cost of that would be unappealing for small order quantities. How much did your custom part cost? Another manufacturer to check out would be fotofab. I think they custom cut and dimple sheet metal, but their stock shields are already quite expensive (around $70 from Digikey, I believe). If I need a custom shield my plan would generally be to secure it with SMD shield clips (Harwin, I think). I would 3-D print a form with two locating holes for dowel pins, drill corresponding holes in the sheet, cut it as needed, and bend it around the form. By the way, if you do find yourself needing to drill sheet metal, try using brad-point (woodworking) bits. The drill doesn't wander, the point doesn't deform the sheet, and the hole comes out very clean. You might not be able to pull this off with 0.8 mm sheet, however. I was considering it for 0.25 mm stock.

The inclusion of probe features on the pcb itself is an interesting idea. I usually don't have much free room under shielding cans where that would be the most useful, but another way of learning what you need to know would simply to make a test board with the relevant features and sniffer footprints.

The reason I used the JLC2116 1.2 mm stackup was that it offered a good compromise between reasonably low width for 50 ohm controlled impedance traces and low(ish) capacitance to ground for places where that would be bad. One thing to be cognizant of in 6 layer designs is that signals on the top layer and the second inner layer may share a return on the ground plane on the first inner layer because the distance between the middle two layers can be comparatively rather large. I think it is a good idea to try to route fast digital signals as controlled impedance in a noise-sensitive design. I have heard Eric Bogatin say you are likely to get EMI problems long before you get signal integrity problems, by which I assume he means digital signal integrity. I take this to mean you are going to get issues with low level analog signals before you start seeing bit errors. I kept my SPI bus lines quite short, with the MCU pretty close to the ADC, so the time delay may not have been sufficient to justify. Sometimes, however, I think it is prudent when design resources are limited to overdesign by default rather than get away with as much as possible for everything because it takes time to figure out how much "as much as possible" is.

I tend to agree that it is easier to try to avoid DC-DC converters, and I didn't mean to imply that they were the right choice for your design. It was necessary to include them within the specific parameters of my NVM because of the whole battery power thing and the importance of keeping power dissipation nearly constant through a discharge cycle to avoid drift in the magnitude of parasitic thermocouples. The results from EMI probes are nice at the level I use them, but the ultimate question is whether a change impacts the quality and repeatability of measurements. When I was probing around, I was trying to understand whether the higher-than-expected noise density with shorted inputs to the ADC driver was caused by EMI, so I made what changes I could to assign the peaks in noise spectrum under normal operating conditions. The challenges, at least with my equipment and setup, were limited dynamic range and the potential for obscuring peaks in the background noise. Also, any experiments are, to some degree, non-representative of actual operating conditions, because the board cannot be in an enclosure. I was able to rule out the SMPS as a root cause for the specific issue I was investigating, but I did not ever get to a complete understanding of the problem. Actually, one of the most valuable debugging features I put on the NVM board was the analog out SMB jack after the input stage.

I should buy a few LSK389s and see how they come out for noise using the same setup I used for the JFE2140. I was aware they were lower noise, but I am interested to see where the 1/f corner is. I haven't used them before because they are more expensive than the JFE2140 and the matching specs are not as good. I would generally be inclined to parallel JFET pairs before using an IF3602 because the matching, capacitance, and leakage are so bad for the latter. The reason I added those details about the JFE2140 was because of some noise measurements you had posted maybe six months ago. It is sometimes difficult as a casual observer to know which issues have been solved.

By the way, have you posted a full schematic of the board? I don't believe I have seen one, but this thread is 11 pages long, so I might have missed it.