Analog frontends for DMMs approaching 8.5 digits - Discussions

[Echo88]

This thread continues the analog front end discussions from the HPM7177-Thread, so it wont get even more offtopic.
Basically this thread should focus on equipping very good ADCs like Kleinsteins Multislope-ADCs, the AD7177 or AD4030-24/4630-24 with suitable analog front ends (high impedance, protected...) that dont degrade the performance that can be achieved with said ADCs.
So far we discussed my approach to build a +-10V high impedance AFE for the AD7177.

To learn how to do it correctly im now studying the 3458A schematics and copied the DCV-path (simplified/omitted control ICs) up to the ADC in Kicad, to make it easier to understand/follow. Maybe its also of interest to other users.
Im thinking wether i should also include the current source/ohms measurement (ACV is another can of worms...) or if that´ll make it too crowded...

Do you think we should first go through the 3458A-DC to then derive a suitable schematic for the AD7177 or maybe also for your Multislope-ADC Kleinstein? I know that youre interested in applying ACAL with your ADC.
Im still having a lot of questions regarding the 3458A-schematic, maybe the more experienced 3458A-scholars know the answers?

Questions:

Is the 1V Signal at Q21 used to do the 1V-range ACAL?
Is the 1:100 HV divider RP7 used for the 0.1V-range ACAL?
Why are the switchable signals at the JFETs divided by Q12 into two signal-"trees":
-maybe one for positive "hot" signals and the other for "gnd"-like signals?
+CurrentShuntOut on one tree, -CurrentShuntOut on the other?
What do Q23/24 measure exactly with their resistors to gnd1?
How exactly are the jumpers JM201-207 on the bottom right page of the "Sentry Current Shunts" page compensating the
TC of the shunts (so ive heard)?
   
Regarding the HPM7177-frontend we discusses beforehand Kleinstein: Does a completely symmetrical AFE (till the ADC level-shifter/driver) like attempted for the HPM7177 have any advantages compared to the approach to just set one voltage input to ground directly?

Schematics for the HPM7177-approach and said 3458A-DCV-schematic are attached.

https://xdevs.com/doc/HP_Agilent_Keysight/3458A/doc/3458A%20CLIP.pdf

[dietert1]

For analog font ends (with their ADS125 24-bit ADC) TI recommend a different kind of multiplexer, with higher channel resistance and much less leakage than the ADG1408. Their recommended MUX36D08 is better than the MAX328 that i used to replace the JFET input MUX of the R6581T. Both of them are specified with leakage around 1 pA at 25 °C, except the TI part has 20x less channel resistance.

Regards, Dieter

[Kleinstein]

The R6581 input is not a good example: it lacks some kind of precharge phase and thus has quite some charge pulses from the auto zero cycle.  The way the JFET gate drive signals are generated is also not ideal.

It makes some sense to inlcude the additional input path(s) for the amps range in the concept. The other point with the current ranges is that they are also linked to the low side / COM terminal and they may effect the protection, if there is more than low side instead of 1 universal COM.

The AD7177 and other ADC chips are usually differential. This can make different front ends more practical. Instead of switching between the input an zero one can do the AZ cycle of a differential ADC by swapping the inputs. Another point can be 4 wire ohms, that could use a real differential input.

The 3458 like many old DMM use JFET switches. In many aspects the modern CMOS switches can make the life a lot easier, especially when it comes to multiplexers with many inputs and if there is no good guard signal from the input to drive the JFET gates.

A big decision to make is whether one wants to use zero drift amplifiers (often as OP-amps) or wants the auto zero switching directly at the input. Both ways are possible an have there pros and cons. The auto zero switching does produce switching spikes even with precharge. These are less frequent than with an AZ OP-amp, but with the variable voltage the spikes tend to be larger and more tricky to suppress.

[David Hess]

What do Q23/24 measure exactly with their resistors to gnd1?

My guess is that they are for measuring leakage current.

[Kleinstein]

Questions:
...
Is the 1:100 HV divider RP7 used for the 0.1V-range ACAL?

Why are the switchable signals at the JFETs divided by Q12 into two signal-"trees":
-maybe one for positive "hot" signals and the other for "gnd"-like signals?
+CurrentShuntOut on one tree, -CurrentShuntOut on the other?

The HV divider gives a 0.1 V signal that can be used for the 0.1 V ACAL step, though with a little extra noise and high impedance that would need some extra waiting time.
An alternative 0.1 V signal could be obtained from the current shunts, but this has also additional noise. The HV divider is likely the better signal.
Ideally one would have an extra 0.1 V signal from a lower impedance divider. For an improved accuracy and as an extra self test it even makes sense to have both positive and negative signals for ACAL.

Yes the separtion in 2 parts is for the Az cycle switching: one for the signal side and one for the more GND like.
The compensation for the switching spike is quite some effort (the extra DAC and OP-amps around this and in parts also the gurad amplifier for the boot signal). With the extra switch Q12 this is only needed once and not for multiple inputs separate.

[tszaboo]

The R6581 input is not a good example: it lacks some kind of precharge phase and thus has quite some charge pulses from the auto zero cycle.  The way the JFET gate drive signals are generated is also not ideal.

While I understand the purist point of view: In my experience the 34410A or the 34401A has quite a bit of charge injection to the measured circuit. You can easily measure it if you connect the DMM into a high impedance node, and measure the same node with an oscilloscope at the same time. I don't remember doing the same when I had access to a 3458A, so I cannot comment on that. My point is, it might be "good enough" because other maters are doing it as well (though they are 6.5 digit).

[Kleinstein]

Switching between inputs causes some charge spikes. It depends on the meters how much effort is used to reduce these:
The R6581T uses no precharge phase and in addition a not so good JFET switch gate drive from the output side, that can add to the charge pulse from the switching.
The 34401 uses a precharge phase, but not extra fine adjustment there. So expect the charge spike to be quite a bit better, though no individual trim.
The HP3456 uses precharge and an adjustement of a capacitive coupled part that is adjusted with a trimmer.
The HP3457 uses precharge and some offset adjustement for the precharge phase with a DAC, likely as a way to trim the charge spike.
The 3458 has precharge and additional capacitive coupled compensation that is adjusted via 2 DACs to reduce the charge peak.  So quite some extra effort to reduce the switching spikes.

The precharge part is relatively straight forward and in many cases one wants a buffer for a guard signal or bootstrapping some clamps anyway. The main part in mind here is the capacitance to ground at the amplifier and switched. Switching some 10 pF at some 25 Hz already is a noticable load (e.g. 10 Gohms range).

The question is a little if one needs an extra reduction of the current spikes beyond the pre-charge part, to compensate some of the charge injection (gate charge) of the switches itself. One tricky point here is that the charge injection usually depends on the voltage. The charge injection parameter found in the datasheets of CMOS switches is usually defined as the extra charge on switching off. With the AZ mode one has both the turn on and turn off phase.
The solution in the 3456 with a trimmer and capacitive coupled part is still relatively simple. These old circuits use JFET switches, things can be a little different with CMOS switches.

[MasterT]

I noticed, that some confusion comes from mixing up two different concept.
1. Old fashion dual/ multi slope, where processing mostly analog in nature, so problems with absorbtion & charge injection  was dificult to resolve.
2. Modern SD ADC, ad7177 etc (I'm experimenting with max11270 & mcp3562) - here we shoudn't care about injection & switching whatsever noise since it's much easier to throw  a sample taken rigth after switching and take another one after long enough settling period, 1 millisec or so. Counting to get 1 kHz sampling rate high just above most OPA +Voltage references   1 / f corners. So requirements to switching IC is close to non - any cd4043 is good.
 

[Kleinstein]

If one has control over the MS-ADC, there is also no problem adding waiting time. The problem is that external capacitance at the DUT can extend the time. So just a little waiting after AZ switching is not an universam solution. It can work for a more internal signal that can tolerate a current spike much better.  Much of the function switching is usually less critcal: one can usually accept additional waiting after a change of function or range.

The SD ADC chips usually already have very low drift to start with and may not need frequent switching. This makes it attractive to use also zero drift amplifiers in the front end, so that there is no or little need for an auto zero mode with switching at the input. Possible extra zero measurements may than be more rare cases and not alternating with the actual input.
The simple Auto zero cycle of alternating between the signal comes with a disadvantge: only half the time is spend on the input and this essentially doubles the noise bandwith.

The CD405x are limited to relatively low voltages (e.g. +-5 V). That may be good enough for the SD ADC diretly, but not really for directly the input with a +-10 or +-12 V range.
Also leakage can be an issue directly at the input. There can be parts that can use the cheap parts, but not all.

[MasterT]

If one has control over the MS-ADC, there is also no problem adding waiting time.

Control over, you mean another switch ?

Lets me put a few words on the primary topic, before my consiousness stretched over billions small details.

 HP was able to developed unprecendented precision level of theirs ADC in the 80's/90's due to the fact, that HP bought on black market  very sofisticated background re-calibration algoritm. Analog Front End in general play big role, but it's limited to 6 digit, microvolts scale level. It was not possible to get 8.5 digit at that time, intill they made a deal with KGB. Not even now.
 Disscussion may continue for another 100-pages, fruitlessly, wiki-pedia style - many words w/o any sense, like Kleinsteine talks (with all due respect).
 
  But precision at nanoVolts level MUST include continuosly running re-calibrarion,  more complex than AZ. It requires wide view on the design, including hardware and software.
PS: Calibration  Logic based on very old mathematics puzzle.

[iMo]

..HP was able to developed unprecendented precision level of theirs ADC in the 80's/90's due to the fact, that HP bought on black market  very sofisticated background re-calibration algoritm. Analog Front End in general play big role, but it's limited to 6 digit, microvolts scale level. It was not possible to get 8.5 digit at that time, intill they made a deal with KGB. Not even now.,

Could you elaborate on that a little bit? HP making deals with KGB on 8.5digits resolution algorithms sounds like a plot from a James Bond movie (I am a big fan of JB movies)..

[Kleinstein]

For the DMM there are 2 steps of "calibration" or automatic corrections that may or may not run in the background.
The more common part the auto zero function to correct for an offset error.
The 2nd point that was usually found in the older meters (e.g. HP3455 and Keithley 19x, Keithley 2001 ) is a correction for drift in the ADC gain and possibly amplifier gain. These meters from time to time or in every conversoin cycle also measure a stable reference voltage (e.g. the 7 V or a rather stable 2 V (e.g. 7 V/4 from PWM or charge pump).
Some of the newer meters like the HP3456, 3458 do no use the perodic check of the ADC gain. The 3458 only does this in the ACAL procedure that is called seprately.
The main point to get away with the extra regular gain calibration is from having very stable resistors, so that the gain does not drift that much.
It still makes sense to include the option to do an internal ADC gain calibration.

For the Multi-slope ADCs there is usually no secret extra linearity correction that is run in between or background. There may be some factory calibrations and maybe special tests to correct for some of the more prominent INL errors. This could be somerthing like seprate gain for the positive and negative side or maybe a small square term. The HP3458 ADC has a somewhat odd looking correction hardware for the zero - not sure how and if it is used at all, as it can be turned off too. My suspicion is that it would do more harm than good.

At least for my MS-ADC I don't need any extra numerical correction to get good INL. The only point is measuring the slow slope to fast slope ratio and auxiliary ADC scale in an extra mode. This does not have to repeated very often (more like 1 time or yearly) and it does not need extra hardware.

If one has control over the MS-ADC, there is also no problem adding waiting time.

Control over, you mean another switch ?

The MS-ADC does not need an extra switch to add a pause. By design there is a switch as part of the ADC to seprate the input from the integrator. If needed one can extend the rundown phase and add some waiting in the µs to ms range.

There is no real magic in the 3458 or other high performance multi-slope ADCs.  Much is a careful design to avoid mistakes that lead to avoidable noise and INL. There are several designs that got to the 8 digit level:  HP3458, Solartron 7081 (though a bit slow), R6581 (with some numerical corrections), Keithley 2002 (though barely 8 digit), Datron 1281 and follow up Fluke meters.
The DC front end of the 3458 is not that much different from the 3456,  mainly better parts and a more sophisticated reduction of the switching spikes.

There are mainly 2 types of front end options:  AZ switching all the way at the input (3458, R6581) with a 1 stage amplifier  or some kind of chopper stabilized amplifier at the front and switching auto zero only after that (K2002, Datron1281) with 2 amplifier/buffer stages. The difficulty with the HP like 1 stage design is keeping the switching spike small. So the charge injection is more than a small detail.
The difficulty with the chopper stabilized way is keeping the bias current and current noise low. The lowest noise AZ OP-amps have a rather high bias. Switching of the chopper amplifier part is more frequent, but with the advantage that it is between 2 voltages that are very close together.

[MasterT]

..HP was able to developed unprecendented precision level of theirs ADC in the 80's/90's due to the fact, that HP bought on black market  very sofisticated background re-calibration algoritm. Analog Front End in general play big role, but it's limited to 6 digit, microvolts scale level. It was not possible to get 8.5 digit at that time, intill they made a deal with KGB. Not even now.,

Could you elaborate on that a little bit? HP making deals with KGB on 8.5digits resolution algorithms sounds like a plot from a James Bond movie (I am a big fan of JB movies)..

I already say too much.
Truth is that ADC, DAC strictly patented and guard by Big corporation located in the West. Royalty is payed out of each single IC produced.
 But enormous number of patents based on stolen or bought dirty cheap inventions come from the East. List is long, I know for sure only about AZ aplifiers, Composite amp, PCM179X DAC's, S/H circuits.
Is recent cheap shortage crissis related to patent war? Who knows.

 Turning back to the topic, disput about AFE w/o knowing Logic reminds me
https://en.wikipedia.org/wiki/Blind_men_and_an_elephant
 
 Just ask yourself, how  comes that backgroung recalibration never published, more over never mentioned.
 
 Schematics are useless w/o knowing what compromises were made at each elements level. Those decisions, vary with  progress in analog /OPA technology, because a lot of stuff that was necessary to implement in the past already integrated inside modern OPA. What is not touched by time is a Logic. Hidden in the dark. Guarded as a rocket science.
 

[julian1]

The question is a little if one needs an extra reduction of the current spikes beyond the pre-charge part, to compensate some of the charge injection (gate charge) of the switches itself. One tricky point here is that the charge injection usually depends on the voltage.

The potential charge injection/current spike at the AZ switch depends on parameters such as - gate voltage, gate/rails headroom, signal input voltage, and is maybe constant for aperture.

Rather than a capacitively coupled dac offset - why couldn't a simple post-facto software correction be used instead? For instance, a 20 point INL like correction delta (dependent on input voltage) for use in AZ mode. And with values determined at the factory with reference to a non AZ calibration.

[David Hess]

Rather than a capacitively coupled dac offset - why couldn't a simple post-facto software correction be used instead? For instance, a 20 point INL like correction delta (dependent on input voltage) for use in AZ mode. And with values determined at the factory with reference to a non AZ calibration.

Software correction does not know how the source impedance responds to the charge pumping.

[julian1]

Hare-brain scheme;

For the AZ switching, alternate between using one channel of a mux, and two channels of a mux.

That yields raw measurements with 1x and 2x switch charge injection riding on top of the input node voltage (The voltage magnitude difference depends on input impedance). Then do software correction/two-point interpolation - to estimate voltage for no charge.

The disadvantage is the extra data being thrown away. Alternatively the data could help derive the offset needed to use for a dac + capacitor compensatory approach.

[Kleinstein]

One can reasonably well compensate for the charge spike from the gate charge, at least for a constant voltage. Essentially all CMOS swtich chips already have some compensation from using N and P channel in parallel and some additional compensation.  It is however not always clear if the chips are more optimized for low charge spike,  low change in on_resistance or maybe a compromise.

One could get around the variable voltage problem by having 2 switching stages in series and have the supply for the first (towards the input) switch bootstrapped to the input voltage. So the first switch gets a supply following the input and is switching between the direct input and a buffered input signal (precharge / gurad signal). The first switch would thus see an essentially constant voltage (relative to its supply) on both sides (except for maybe mV level offset). The switching between the signal and zero and other signals would than follow in a 2nd MUX.
It is some extra effort for the extra bootstrapped supply and level shifting the switch signal - still not that bad compared to the DACs in the HP3458. Other signals may need separate amplifiers for guard signals.  As the extra switch at the input only sees low voltage a moderate supply (e.g. +-2 V) is needed - the exact voltage could be choosen to get minimal charge injection. Chances are a CMOS chip would be easier than 2 JFETs with drivers.

The residual current spike at the input should contain mainly high frequencies, e.g. from residual delays between the switches and compensation (if needed). One should be able to filter out the higher frequency part with acceptable small capacitors / resistors / inductors that may be wanted for EMI reasons anyway.

[David Hess]

The LTC1043 datasheet and application notes discuss the limitations of charge pump compensation and how it is affected by input voltage.  As Kleinstein suggests, a discrete design should be able to provide compensation over a wide input voltage range.

Most circuits do not care about it, but it does come up when the source has its own charge pumping going on and the frequencies are close.  The result can be a  slowly varying offset voltage.  Most often I see it when trying to measure the input resistance of one multimeter with another multimeter, in which case I may break out one of my old multimeters which use a linear input stage with no charge pumping to make the measurement.

This is the same problem that early and some modern chopper stabilized amplifiers have when dealing with AC signals close to their chopping frequency.

[julian1]

Bootstrapping the switch(s), to manage charge-injection over variation of signal input looks clever and elegant. 

A useful first step would probably be to characterize switch charge injection, for modern jfet versus cmos mux, and maybe even discrete n+p fet switch options.

Parts like adum/isolators that might ease doing controllable gate drive wrt the floating signal input.

[Kleinstein]

Discrete MOSFETs tend to be rather low resitance and relatively high gate capacitance. There are hardly any tiny discrete MOSFETs available - excepts maybe RF types, which are usually dual gate ones.
For the JFET way a relatively small (more RF type like mmbfj211) would be a sensible choice, as low capacitance is wanted. For the initial test the large types like J113 / 2N4393 may be easier to measure and the principle should not change much.
For CMOS chips the choice of the chip would be relevant, as much of the gate charge compensation is inside the chip. The trim for minimal current pulse would likely be from the supply (or common mode voltage). A difficulty is that the leakage specs are usually quite loose and not tested. The lower voltage chips tend to be mostly relatively low resistance and not low leakage. For a test I may consider the 74LV4053 with a 3-5 V supply.

The RF or magnetic based isolators tend to need quite some current also on the receive side. The control signal does not have to be very fast of accurate timed. So one can use rather conventional optocouplers or just a current signal via a current mirror. 1 signal to control a SPDT switch would be sufficient.

[David Hess]

Discrete MOSFETs tend to be rather low resitance and relatively high gate capacitance. There are hardly any tiny discrete MOSFETs available - excepts maybe RF types, which are usually dual gate ones.

In theory Calogic and Linear Integrated Systems have 4 lead small signal MOSFETs available which are ideal for this.

http://calogic.net/products/mosfets/
https://www.linearsystems.com/product.html?category=dmoshss
https://www.linearsystems.com/product.html?category=mosfets

Signetics used to sell 4 lead small signal MOSFETs which were just the transistors off of their integrated MOS IC process.  Their performance was amazing and became the SD series.

[opa627bm]

Hi All,
Anyone here can help explain How Q001 Q002 Q003 and Q004 works?
why Source and drain are shorted and not connected to anything ?
Regards,
Li

[MegaVolt]

Hi All,
Anyone here can help explain How Q001 Q002 Q003 and Q004 works?
why Source and drain are shorted and not connected to anything ?
Regards,
Li

With this connection, the transistor operates as a diode with very low leakage in the reverse connection. These diodes are for protection.

[David Hess]

Anyone here can help explain How Q001 Q002 Q003 and Q004 works?
why Source and drain are shorted and not connected to anything ?

With this connection, the transistor operates as a diode with very low leakage in the reverse connection. These diodes are for protection.

To expand on that, low leakage diodes *are* available, however they come with a high price premium because of the required extra testing.  JFETs are routinely tested for gate leakage, so they are usually or always less expensive than a tested low leakage diode.  The 2N4117A/2N4118A/2N4119A low leakage JFET is typically used for this with a tested maximum gate leakage of 1 picoamp at 25C and 20 volts.  The non-A versions have a tested maximum gate leakage of 10 picoamps.

[Kleinstein]

Here is a possible way for the input switching an protection. The 2 parts are in principle independent though they share the OP-amp (U3) for bootstrapping and guarding.
The ESD protection is not yet 100%, so this is more like for careful use in a lab and for low noise, not so much a rugged design. The idea of the protection with MOSFETs and photovoltaic gate driver is borrowed from the Keithley meters like K2000 or K2001.

The switching is relatively fast, so that the current spikes are rather short, though higher peak current. The idea is to get more effective filtering and this way less external charge pulse.
In comparison the HP3458 uses rather slow switching (a slew rate of some 5 V/µs and thus some 1-4 µs for the transients), likely because of the limited speed of the DACs used to trim the charge compensation. Not sure if they use a fixed setting or make it voltage dependent to compensate for the nonlinear gate capacitance.

The fast switching makes digital trim hard and thus the old style variable cap.
The adjustment of the gate charge compensation via C5  could be a bit tricky for 2 reasons:
1) it may not be easy to measure the small transients - ideally not much reaches the input.
2) the capacitance for C5 is quite small and parasitic capacitance adds to it. There are not many trimmers in this range.
In the simulation C5 wants a value of around 0.55 pf for J201 FETs.
The adjustment, the delay from C7 and filtering (values of C4 and C6) effect the transient charge pulses and also the input current pumping. So if way off it can contribute to the input bias current.
Chances are some resistors / capacitors would have to be adjusted on real world hardware, because of parasitice capacitance and similar effects.

The filter capacitors C4 and C6 are towards the guard / bootstrapped signal, because the charge pulse from the gate drive also comes from there. So the OP-amp does not have to drive the fast spikes.
Because of these capacitors noise from U3 could contribute a little to the current noise, though mainly the higher higher frequency part.  So it may be worth using a low noise amplifier for U3.

The CMOS mux at the end is just an example type.  If really needed a 2nd channel (e.g. high side ohms sense) could use a similar precharge scheme.
For a high voltage divider I would consider an extra AZ op-amp as a buffer. This way one avoids the auto zero switching spikes and the switches are less critical.