DIY high resolution multi-slope converter

[MiDi]

Detailed curves around -300mV for run-up Q & V are added to the corresponding former posts, R & P follow.

Sir, may I ask you compared with off shell commercial adc, why would us diy adc like hp do in 3458a? And have a conclusion of your project, compared with adc in 3458a, how this diy adc perform? I want to diy and share an open source dmm, and if I implement your adc design, how far it will go, 6.5 digit? Thank you very much sir.

3458A ADC has INL <0.1ppm (HP Journal p. 14), TC ~0.4ppm/K (HP Journal p. 13), noise input short ? (~0.1µV AC RMS @100PLC incl. frontend), long term drift ? (Keysight allows up to 0.43ppm/day according to SN18A)
DIY MS ADC has INL ~0.1ppm (excl. around -300mV), TC tbd, noise input short ~0.06µV AC RMS @100PLC (w/o frontend - 3 reads ru W), long term drift tbd

Performance of a DMM with this ADC will be limited mainly by references and frontend.
E.g. LM399 is good up to 6.5 digits, selected up to 7.5 digits.

[Kleinstein]

Some modern ready made ADC chips ( AD7177,  AD4630, LTC2500-32) got impressive performance, both from the noise and also the INL. These chips are still expensive and need special drivers and a 2.5-5 V reference (the usualy high end references are 6.6-7 V). So even a ready made ADC chip would need some critical circuit around it (ref. divider and buffer, maybe input divider, input driver).
The more common SD ADCs are cheap and relatively easy to use, but they are also more noisy and higher INL (e.g. 1-5 ppm range).
The SD chips are low power and small - so at the lower end range with 5.5 and 6.5 digits they are a very viable way.
SD ADC usually also offer different choices of frequency response / digital filtering (e.g. sinc³ filter). This can help, but also make a comparison difficult.

A seprate build MS-ADC has the advantage of getting a native range of some +-10 or similar, so that one can directly measure a 10 V or 7 refrence. They can use a 7 V reference (LM399, LTZ1000,...) without an extra divider. The INL is often better than most (if not all) of the SD chips.

The DIY ADC so far is noise wise at the level of the 8.5 digit DMMs, that is comparable to the 3458 or Fluke8858 or the AD7177 ADC chip.
Speed wise the software is mainly made for the 1 PLC case, slower is included but of limited interest. Faster is possibly but not tested very much. I had initiall tests working with 100 µs integration time as well - here the data transfer is the more limiting factor. As the rundown takes some 100-150 µs the current version is never as fast as 3458 in it's fastest modes, but still OK for a normal DMM.

The last linearity measurements from MIDI are very promissing, putting it in the 8.5 digit range. My test had a little more INL (and more uncertainty in the tests), but still better than most ready made ADC chips.

For me the important point is getting the INL good enough to allow using an ACAL procedure similar to the 3458, at least for the 6 digit range. This helps expecially for a DIY project with little means to adjust the other ranges. It also helps to get long term stability, which is otherwise difficult without long experience on aging of the parts.  In this sense it is OK to combine a rather high performance ADC with "only" a LM399 reference that limits the performance to the 6-7 digit range. After all the ADC circuit is still relative simple / low cost, more comparable to the ADC in the 34401 or Keithley 2000.

[MiDi]

Comparison of different run-up versions:

Full-range:



Run-up V, P, R showing curves bent downwards, while Q & W seem to be quite linear.


Problematic region V vs. W (same fixed time 18/18, W has half the modulation frequency of V):



Problematic region P vs. R (same fixed time 8/8, R has half the modulation frequency of P):



Problematic region R vs. Q vs. V (same modulation frequency, but different fixed times R: 8/8, Q: 12/12, V: 18/18):

[Kleinstein]

The run-up versions R, Q and V are with the same frequency (and thus similar DA effect expected), but different (increasing) minimum time for the short phase. This makes the settling of the integrator more important for case R and less important (more time for settling) for case V.
AFAIR the mode V already has a slightly limited full scale range and there is no real need to use the very short pulses like in case R.

Comparing the critcal range for V and W, there is some imporvement, but not directly a factor of 2. So the INL errors more looks like a mix of several effects ( DA and some settling/ switching related part).

One more parameter to change may be the integration time at a piece. At least 2 and maybe 4 PLC at a piece should work with only little more noise and may lead to slightly better INL.

[miro123]

I have an question
How the INL test performed?
 - startup time / stabilization etc.
 - steps sequence
 - measurement equipment settings
 - PC post processing.
 - timing
 - logging information - temperature , at which point to sense temeprature, humidity, atmospheric pressure
To many questions. Isn't it? :-)

[MiDi]

I have an question
How the INL test performed?
 - startup time / stabilization etc.
 - steps sequence
 - measurement equipment settings
 - PC post processing.
 - timing
 - logging information - temperature , at which point to sense temeprature, humidity, atmospheric pressure
To many questions. Isn't it? :-)

To answer the last question first: no 

startup time: ~220s
stabilization: 45s settling of 4th order LPF (postprocessed), ~400s measurement / ~4500 values for each step (as 3458A is slower than ADC, only every 2nd ADC cycle is captured quasi isochronously)
steps sequence for +-11V (see attached charts): 500mV steps (~440mV @ input), 4x ramp down & ramp up (8 ramps), +-1.1V/-300mV: 10mV/1mV steps 1x ramp down & ramp up (2 ramps)

Settings 3458A (connected to the input of ADC):

Code: [Select]

PRESET FAST
DCV {int(range)} #10V or 1V, depending on range of source (constant over one run)
AZERO ON
TARM HOLD
TRIG SYN # only capture data on read
NPLC {int(nplc)}
FIXEDZ OFF
ARANGE OFF
NRDGS 1,SYN
MEM OFF
END ALWAYS
DELAY 0
TARM SYN # only capture data on read

Settings K236/7/8:

Code: [Select]

F0,0XB{float(Source.start_value)/1000:7f},{Source.range_set},0X # Function: F0,0 = source V, B: Range setting 0 = Auto, 1 = 1V/nA, 2 = 10V/nA, 3 = 100V/nA, delay = 0 in ms
H0X # only with immediate trigger it sets the output
N1X # N1 = operate
O0P0Z0S3W0L10E-3,8X # other settings O0 = local, O1= remote sense, P5 = Filter 5 = 32 readings, Z0 = suppression disabled, S3 = 50Hz 20ms integration time, W0 = disable default delay, L compliance 0=auto range

Settings ADC:

Code: [Select]

[init()] #reset, initialise & gain corrections (k factors)
A # mode: A=AZ
[run-up] # run-up version W, Q, ...
[input_ch] # input channel of mux (0..7)

Post-processsing for one staircase is as follows (excerpt):
- Linear regression for dmm & adc
- Scaling adc from slope ratio of both regressions (gain normalization)
- Offset correction for adc
- Diffs between adc & dmm on a per sample basis gives INL (correlated)
- Aggregation of n Diffs to one point for INL

From the results of the single staircases (e.g. 8 ), the outliers are sorted out and the remaining good staircases are aggregated for final chart

Timing between 3458A and ADC is quasi isochronously, so we get correlated value pairs (triples for ADC AZ), see details in former post.
Side-note: this was a major development  task, with all the oddities of UART-to-USB-adapters, incorporating a PLL and much more little things you never dreamed of and gets you nightmares...

Temperature (humidity, atmospheric pressure) is usually stable enough for one staircase (usually <0.1°C - lab is in basement), limiting is probably most the drift/LF noise of the LM399.

excerpt of the python code to generate staircase e.g. +-11V:

Code: [Select]

src_set_values = collections.deque() # list of values for voltage source (K236/7/8), each value for one ADC cycle

# +-11V
range_set = int(2) # range of K236/7/8 - 1: 1V, 2: 10V, 3: 100V, 4: 1000V
factor = int(10**(int(2-range_set))) # multiply start/stop value for stepping in range: 1: *10, 2: *1, 3: *0.1 = *10^(2-[range])
stop_value = int(12500) # gives ~11V on ADC input due to 4th order LPF (4x2x1kΩ, 4x220µF)
stop_value_range = int(stop_value*factor) # max value in range-steps of K236/7/8, for 10V range: factor = 1 (see factor)

#Staircase +-11V
for _ in range(5000): # 5000 * ADC cycletime initial value (~220s +11V)
src_set_values.append(stop_value_range/(1000*factor))

step = int(500)
repeats = 2
for _ in range(4): # generate staircase with steps of 500mV with 2x500 values for each step (440s) going from +11V .. -11V .. +11V repeated 4 times
for i in range(stop_value_range - step, - (stop_value_range + 1), -step):
for _ in range(repeats*step): src_set_values.append(i/(1000*factor))
for i in range(-(stop_value_range - step), stop_value_range + 1, step):
for _ in range(repeats*step): src_set_values.append(i/(1000*factor))

src_set_values.append(0) # set source to 0V

Test-Setup (old picture, cable to 3458A not installed):

[branadic]

Any updates?

-branadic-

[Kleinstein]

Any updates?
-branadic-

Currently no real news:

The software (for the ARM based version) needs a rewrite to include full control for the amps an ohms part. The current version lacks some of the relay control. My first try on a rewirte failed half way through.
For the 2nd try I have the ideas, but no code yet. It's not about the ADC part itself, but the tricky part is having things like a dual measurement and the ACAL procedure without getting too much code.

The ADC part seems to work fine: low noise (about on par with the 3458 at 1 PLC) and from MIDIs measurements the INL also looks good already at 1 PLC and a little hope that it could even get a little better with 4 or 8 PLC integration at a time (not yet tested).
The ACAL procedure still has a little more than hoped for difference between the positive and negative side, though still not too bad. It could well be the amplifier part that has problems.

The DMM frontend for the main part works but still has 3 issues:
First is with leakage at one of the reed relays. I get very slow oscillations when measureing the voltage at a high impedance source (e.g. > 5 M) at the ohms source terminal. Without the relay the lowest current range (some 2 µA FS) is missing. The problem looks fixable with an additonal CMOS switch and maybe a different relay.

A second issue is a little unexpected extra noise at the front end, like some hum or effect of supply ripple adding some 30 nV of low frequency noise to the input. So while the higher frequency noise looks good, over longer time the noise does not average out well. I suspect the DCDC converter with it's spread spectrum part that does a modulation at some 50 Hz and may thus give me a low beat frequency. The DCDC converter (SN6505) part is definitely a part to change - it is currently out of stock anyway.

The more serious weakness is with the 200 mV range of the voltmeter front-end: it too does not like a high impedance source. With more than some 100 K it tends to oscillate. I can shift the limit a little with more capacitance at the input, but no easy fix so far.
I got an idea (actually 2 versions) to modify the input section so this problem should no longer happen. It somewhat interferes with ohms readings (the ranges are cut in half and the high ohms may have a little more drift), but otherwise should work, with only slightly more noise in the 200 mV range. The change for 1 version is small enough to try as a bodge to the existing PCB. The other, more clean version would likely need a new PCB.

[Anders Petersson]

Happy three year thread anniversary!
Do you have a target specification to bring us newcomers up to speed on the project scope?

[Kleinstein]

There is no real target specs. There was a rather modest one at the start of the project, looking for something like 5 µV noise and 1 ppm of INL to make it a usable 6 digit meter while keeping the circuit simple. It by now well exceeded that.

By now with small refinements (manily better resistors, layout improvements, reference filtering,  74AC74 for synchornization and the LV4053 instead of HC4053) the noise is down to about 500 nV (for 1 PLC AZ mode in the 10 or 20 V range) and thus 7 digits and more with averaging.  From the calculations the noise is not expected to go below some 430 nV with this circuit. So there is still a little noise not accounted for (e.g. supply ripple, mains hum, additional jitter), but not that much anymore.
The INL looks good enough (likely better than 0.2 ppm of FS), but the measurements at that level are hard. A minimum target for the INL is to have it good enough to use the ADC to link the DMM ranges to each other with good accuracy.

I consider the actual ADC part finished - maybe a few more INL tests and maybe SW for faster than 1 PLC conversions, but not sure if this would happen.

For me the main point now is more the DMM front end part, that is DC only. The front end so far is for ranges of 400 V(~ 300 V because of relay rating), 20 V, 3 V (using an on hand resistor, should be 2 V), 200 mV, some 1 A, 100 mA, 10 mA , 1 mA, 300 µA, 30 µA, 3 µA with limitations, optional 2 µA and lots of ohms ranges from some 20 Ohms (10 mA test current) to some 2 Gohms (8 nA test current - but limited stability, may change to 1 Gohms). In principle the calibration should be to 1 voltage and 1 resistor. The amps and Ohms part is not yet tested in this respect. The SW still needs quite some work.

The main limitations are missing AC functions, limited maximum voltage and somewhat limited protection and so far no display, but data send to the PC only, some even in a raw format. E.g. the ACAL part needs support on the PC side.
The voltage ranges are still limited by the LM399 reference. Similar the resistance reference is a plastic case foil resistor only - so not very stable either, but Ok for a proof of concept.