Building your own voltage reference - the JVR

[dietert1]

Yes, the TC of a diode in the drain path arrives at the reference output with some attenuation, which is very interesting. In order to get the required fraction of 0.36 i would need several diodes, maybe 5 or 10. To get the TC sign correct, the diodes will not be in the drain path, but in the intermediate supply divider. Will try that later.

Regards, Dieter

[DeltaSigmaD]

The JVR reference circuit is known at least since early 70s, but it wasn't used in measurement equipment because its initial reference voltage has huge tolerances. However, it is reported in this forum that the stability of the JVR can be amazingly good. The pressure to find better references is high, so the JVR should be analysed as low power, low noise reference in this new light of stability.

Kleinstein and dietert1 discussed the temperature dependency of the JVR. I performed some simulation experiments with LTSpice. The first diagram Fig.1 shows a temperature compensation for a JVR, so that the residual drift has a forth order shape. The reference voltage deviates less than 4 ppm from -20°C to 57°C. It is possible to move the minima closer together in order to get an optimally flat zone, see Fig.2. However, this theoretical result is too good to be true: as the precision of R1 and R2 shows, a perfect matching of the characteristics of J1 and Q1 is essential to obtain this low temperature dependency. I assume that such tight matching can be hardly realised in practical circuits, or it will need days or weeks of work. Assuming this adjustment can be obtained, it will be complicated to ensure that J1 and Q1 chips have a temperature tracking better than 3 mK. The reference voltage is defined by the combination of 3 large currents, and good long term stability cannot be expected therefore. Other simulated circuits with third order residuals are not better in this aspect. 

If the allowable working temperature range is not too large (f.e. with battery-operated hardware), the temperature of the reference JFET can be measured and its drift is corrected by software, so that drift compensation by analog hardware can be omitted. Long-term stability is the remaining problem. Fig.3 shows two 10V JVR reference circuits without compensation. The lower circuit uses an OP amplifier to get the 10V value, while the upper circuit uses JFET J3 for amplification and the OP only as buffer. The simulation shows that the noise of the reference alone is much lower than the noise of the OP. Therefore, the upper ref should be applied for low noise, even if its adjustment (drift maximum and voltage) is more complicated. C4 reduces the high fequency noise to the noise value without amplification. 
 
Assuming the LTSpice JFET models are correct, the JFET reference has very low noise. The buried Zener references have a sharp break-down, while the JVR has a soft working point, even softer than of bandgap references. The depletion zone of the JFET has a large volume, while a Zener reference relies on a limited set of hard punctual microplasmas, which must be very sensitive to interstitials, voids, impurity clusters etc.. Please see Zener microplasma action at Richi's Lab - unbelievable microscope pictures there. 

The essential point of the circuit Fig.3 top is that only 2 parts must have utmost precision. Since no heater is applied, there will be no temperature hysteresis with power failure and the temperature gradients around the reference JFET can be kept very low (Kovar feed-throughs at hermetic case!). Is it possible to obtain long-term stability with a soft working point? How large is the temperature hysteresis of different JFET types? The next step is testing of real JVR hardware, which includes the JFET case temperature measurement.

[Cerebus]

Assuming the LTSpice JFET models are correct, the JFET reference has very low noise.

Sadly this isn't the case. It isn't LTSpice, or even spice in general that is to blame, it's the models. I don't think I've yet encountered a single BJT or JFET model that actually properly populates the model parameters that allow spice to model \$\frac{1}{f}\$ noise properly. With those parameters at their defaults you always get optimistically good results for \$\frac{1}{f}\$ noise.

[Kleinstein]

The 2 nd order TC is relatively large. So the numerical correction for the square part is not that easy, if the range gets larger.
The analog compensation is tricky, as this often also give quite some linear contribution and thus needs to be quite stable.
I compared J111 (similar to 2n4391) and J113 (similar to 2N4393) they both showed a comparable 2nd order effect at around 3 µV/K². So inprinciple one could use 2 similar JFETs with different theshold and only use the difference - so kind of a discrete version of what AD called the XREF referencce. The drain voltage seems to have some effect also one the 2nd order TC, though not enough for a full compensation.

For ultimate stability, temperature stabilization is likely the way to go. Even only a crude temperature stabilization is quite effective against the square effect. Trimming the linear TC to some 5 ppm/K is not that difficult, so that the requirements for the oven can be moderate.
Trimming the 2 nd order compensation can be quite trick, it can be done, as shown with the Solartron 7071 , but it is quite some effort.

The large scattering in voltage level is a problem. Using resistor gain is tricky, if the adjstment range is larger. This does not get much better when the adjustment is done like in Fig3 combined with the Ref. itself. It saves 1 resistor, but the demand on the resistor that needs adjustment also goes up.

For a DMM or high resolution ADC a variable reference votlage to start with may not be that bad. Some designs measure the ref. voltage directly by the ADC to adjust / check the ADC gain factor anyway. This step can tolerat a large range, as long as it is well within the ADC range. It would be only 1 gain stage to set the working ref. voltage to the ADC. I am actually considering a JRV ref. for my ADC circuit  - availabilty of LM399 and LTZ1000 is currently not the best.

The simulated noise is not especially accurate, epsecially not for the 1/f part.

However the measured noise also looked good, at least for the 2N4391 and J111 that I checked.

[dietert1]

Here a little report of my recent tests with a JFET pair prototype.

Regards, Dieter

[Kleinstein]

The circuit looks a little odd at 2 details: the capacitor C3 is quite some capacitive loading to the OP IC1 this does not look right.
The ouput amplifier looks like it can tolerate some capacitance, but having already 10 µF (C11) allready looks like pushing it close to the limit.
In my test I see very little higher frequency noise - so there is likely no need for most of the caps, at least not that large. The datasheets also suggest vers little higher frequency noise.

The OPA140 is a really good JFET OP, but it can still have quite some 1/f noise by itself. The more suitable choice for the amplifier would be more like precison BJT baded ones. So more like the classic OP27 or OP07.  Modern higher performance ones (e.g. OPA207 or AD8676) are also possible, but likely not needed.
The ouput impendace (some 150 Ohms+R2) should be low enough to drive a BJT based OP with no problem.

[dietert1]

Yes, there is a more complete schematic as well. The schematic i showed is "schematic" and was meant to show my variant in contrast to the above LTSPICE models. Not meant for copy-kids. Meanwhile i think i will make a board and then use a chopper amplifier like OPA2189. Also the diode signal should not be brought out on a wire, but with a buffer with some gain (bridge circuit).

Regards, Dieter

PS: The divider for the TC correction signal can be made temperature sensitive, e.g. by using one resistor with a certain TC. That becomes a multiplier for the TC correction signal to generate a second order correction term. Just an idea.

[IconicPCB]

Dieter,

Thank You for the report.
For some reason I am under the impression that in the two fet cascode like structure the fets should have different pinch off voltage ratings.

Specifically the upper fet should have pinch off voltage which is typically twice the pinch off voltage of the bottom fet.

Expected device selection upper fet 2N4391 lower fet 2n4392.

Please consider

[dietert1]

Yes, it appears like a cascode, but the upper JFET has an elevated gate voltage. In my prototype the lower FET runs at Ugs = -5.6 V and Uds = 4.4 V. The upper JFET runs at Ugs =  -4.4 V and Uds = 3.3 V. If i exchange them it should still work, except with lower current.
This proposal was meant as method to overcome the large uncertainty in pinch-off voltages by selecting pairs of JFETs. Think of two 5 V zeners. Imagine you could  only get bad zeners with a specification of 5 +/- 2 V. Then you could combine a 4 V one with a 6 V one to get 10 V without throwing away zeners.
Somewhere in this thread Kleinstein proposed to search for JFETs with 10 V or near 10 V pinch-off, but i haven't found any. I even ordered a batch of BF247C which are specified for up to 14 V pinch-off, but again nothing like 10 V.

Regards, Dieter

[Kleinstein]

The circuit is essentially 2 of the JRV references in series. 2 in series give more choices with the voltage.
The more unusul part is the diode use to compensate the residual TC  - the usual way is by adjusting the resistor to set the current. The diode may give a little more flexibility with the voltage, though also a high 2nd order TC.

One could combine 2N4391 and 2n4392 to get a special target votlage like 10 V, though there is a tendency that the 2N4392 would need a little more current to get near zero TC. So one may want some extra resistor to get both FETs in the range of low TC.

10 V from a single FET would be rather extreme - this would be more like a possible target if special fets would be designed for this purpose. The largest I have found so far is one J111 with a little over 8 V. The voltage can vary between batches and also somewhat (e.g. +-500 mV) inside a batch.

[dietert1]

No, 8 V may the pinch-off voltage, but if you increase current to get near zero TC, you will have more like  6 or 7 V. Getting 10 V with one JFET was fantasy.

I am using a diode for TC compensation because for me adjusting TC by JFET current didn't work. Above i reported my experiments with J105 JFETs that did not reach zero TC at more than 5 mA. And from my discrete bandgap reference experiments with diode chains i learned that currents in reference elements should be small. Otherwise there will be the bond wire weakness. If you assume that a bond wire is 10 milliOhm, then 1 mA contributes 1 ppm. A common 1 mil bond wire has about 50 milliohm per mm of length. Recently i found a 2N3055 with redundant bond wires to the emitter - both completely open.

Kleinsteins statement about "high second order TC" is fantasy as well. Please look up the numbers and diagrams above. The temperature sweep in my little report shows less than 1 ppm curvature between 20 and 28 °C. So this is as good as any temperature compensated zener, except with a much smaller linear compensation in case of the JFET.

Regards, Dieter

[Kleinstein]

Finally got a step further with an oven for the JRV reference. At least at the sensor used for regulation the temperature is quite stable (some 10 mK_pp). 
The oven is some 32x32x20 mm with 2 mm (0.6 mm one side) aluminum at the outside, where the heater is attached. There is some isolation with bubble-warp, just for the first tests.
The set temperature is relatively low, at some 30 C or so. I may want a little more isolation and a slightly higher set temperature.


The curve shows the measurend voltage and heater current (15 V voltage).  At some 2300 s the whole oven is covered with some paper - this likely caused the power slowly going down.

The noise and medium time stability looks good - as far as one can tell in comparison to a LM399 ref.
A little of the higher frequency noise is from the ADC (some 1 µV_pp for average over 12 conversions at 1 PLC). The pop-corn like jumps (~2 µV) are larger than with the 2 JRV ref. test before (~0.5 µV). Still not sure if they are from the LM399, as the jumps there often looked larger (e.g. 4 µV). Still the overall noise looks good, given that it includes an LM399 (filtered to some 5 Hz - but this should not help very much).

[Kleinstein]

Comparing the JRV to a meter with LM399 reference is not really sufficient to judge the noise at this level. So I added a 2 nd JRV type reference to the same ofen (found just enough space to fit) using the same drain voltage and without buffer.

The curve shows the voltage of the 2 reference measured in parallel with the same ADC / ref. The points in the curve are for the average of 24 conversions at 1PLC in a fast sequence. So not exactly at the same time but very close and overlapping. Each point represents about 2 seconds.

In the initial part the temperature is likely not yet full stabilized.

The curve shows the noise from JRV reference plus the LM399 (seems to be a rather low noise one with only rare large popocon type jumps) at the ADC. There is some correlation in the noise, but only partially. Much of the noise seems to come from the JRV references and not the ADC or LM399. The ADC contribution should be essentially white noise of some 0.8 µV_pp.

The noise of the 2 curves looks a little different from what I saw in the direct difference on the bread board. So I checked for excess noise of the resistor type (Susumu RR - thin film 0805 size 25, ppm/K specs) used for th source resistors and the amplification for the drain voltage. The test showed low noise (better than -50 dBi noise index, which is about the limit for my simple test setup - DC bridge with NiCd batterie for floating bridge drive and AZ OP for amplification). So there should be essentially no excess noise from the resistors. It would take rather noisy resistors (e.g. -10 dBi range) to see the resistor excess noise at the JRV output as the resisor noise is attenuated about 30 times.

[dietert1]

Would you tell at what source currents the JFETs run and the temperature of your oven? Can you run a difference measurement, so the LM399 noise is out?

Until now i have only one ovenized JVR and my estimate would be about 2 uVpp. Will also make a prototype with two JVRs to get the difference measurement. Also with two of them, the average should have less noise..

Regards, Dieter

[Kleinstein]

Both FETs use a source resistor of 6.191 K nominally. For both this is a resonable good trim to low TC, though I still need to measure the voltage versus temperature curve.
So the current is at 1.1 mA  resp. 1.13 mA. The  drain voltage is at 4/3 of 6827 mV thus 9.1 V.

The temperature schould be at around 25-30 C, so a little above room temperaure, but not very much. The temperature is stable and like with the curve before there is no real correlation between heater current and ref. voltage.  For the initial tests on the bread board I also had a noise level more like 2 µV_pp, though for a shorter time frame.

A direct difference reading is a good idea. I can at least plot the difference from the same data file (see atachment). So still both conversions, but at least without much of the lower frequencey noise of the LM399. At the ADC there is some low pass filtering (2.2 Hz cross over) for the LM399 reference, so the higher frequency part of the LM399 noise is suppressed quite a bit. A direct difference measurement would be slightly better, but needs a new run. For the resistor noise measurement I have a difference amplifier anyway - so this would be relatively easy, just needs time, so maybe tomorrow.

edit : had the wrong curves with difference to LM399.
        There seems to be something slightly wrong with the scale factor of one of the curves.  The 2nd ref should be more like 6927 and not 6977 mV. It does not change much with the dift or noise.

The noise is still a little higher - but given the relatively long time (some 3 hours)  the difference is not that large. The timescale for the curves is a bit longer than the usual 0.1 - 10 Hz windown often shown in data-sheets.

[SilverSolder]

How does the noise compare to LTZ1000?

[Kleinstein]

How does the noise compare to LTZ1000?

Over short times (e.g. 10-100 s windows)  I would consider the noise comparable to the LTZ 1000, for the white noise part the noise is even considerably lower (some 5 nV compared to 40 nV). However for the longer run (e.g. 1 hour) / lower frequencies there is higher noise (some 3-4 µV_pp compared to maybe 1.5 to  2 µV für the LTZ).

For most refrence applications the longer time scale is relevant, not so much the very short time. So the usual 0.1 - 10 Hz  (or peak to peak noise over a 10 s window) specs for low frequency noise are more like convenient to measure and not that close to real world use. For real world it would be more like 0.1 -10 mHz.

For the long time scale I am still not sure if the oven is good enough, but chances are it is. The LTZ starts with a relatively high TC (some 50 ppm/K) and thus need a very stable temperature control. The JRV can be adjusted to a low TC like 1 ppm/ K range to start with and than get away with a less stable oven. So different from the LTZ the set point for the oven is not so critial - it is the resistor at the source that is critical for the long term drift. Also the amplification for the drain voltage seems to need good resistors - my inital crude meassurements do no match up the datashett numbers as I understand them. This could be in part because the Fets are really high threshold ones, not the more average ones.

[Kleinstein]

I did the test with a direct difference measurement.  The difference signal is amplified by an AZ amplifier in a way that the ADC switches between +21.8 times the signal and -21.8 times the signal. This gives an AZ mode with near 100% sampling and 2 PLC data with 25 reading per second. I used the same amplifier for resistors noise testing an it was low noise and low drift there. So the ADC and amplifier noise should be only a very small part. The buffered reference is use for the "ground (low impedance terminal of the amplifier)" the other ref. is  not buffered and has some 68 pF+100ohms for filtering at the AZ OP.

It took quite some time for warm up - so that curve starts at 4000 seconds. It seems the TC adjustment is not that good as I thought.
The initial data look good, but later there is quite some nasty up and down. It still looks more like Popcorn type noise with relatively fast jumps, not really like a more slow drift or smooth variations as expected for a thermal effect. So at least one of the 2 reference is not behaving well. Over some short parts it still looks OK, but as a whole this does not look good. The shorter term part is still comparable to the indirect difference measurement reading both voltage separate. So it does not like the amplifier or oven is the problem.

[DeltaSigmaD]

The 3rd order compensation of the temperature dependency of a JVR (as described Jan 26th) was verified in hardware. The compensation circuit was largely improved. A first prototype yielded a 5V voltage with 3.5ppm stability from 20°C to 32°C, see attached diagram. The 1 day drift is also within a 3.5 ppm box. More details can be found in the attached paper. Next, the stability over longer time will be measured. Note: the Keysight 34470A is used for reference voltage measurement.

[dietert1]

Nice experiment, thanks for the report. As far as i understand the transistor circuit works similar to a bridge circuit that allows control of the curvature of the base-emitter diode temperature curve. I mean the real temperature sensor is the base-emitter diode of Q1. Is that correct?
Did you think about giving Q1 a Miller capacitor to calm down it's operation point?
Also it appears to me that your FET is running at about 2.5 V of Ugs. The gain inherent in R7 R19 R8 should be a little less than 2. Did you try to find a FET with a higher Ugs? This would also help with noise.

Regards, Dieter

[DeltaSigmaD]

The base-emitter diode of the bipolar transistor is working as nonlinear temperature sensor. The zero TC working point of the JFET is shifted to a particular position so that an agreement of 1st, 2nd, and 3rd order can be obtained at the working temperature. That is the reason why there is a power-on drift of the reference voltage.
The miller capacitor may improve the high frequency noise. But, if two capacitors --> lowpasses are in the feedback loop, there might be oscillation. The cap values must differ by more than one order of magnitude. I will place a Miller cap next time.
There is no free choice of Vgs, I could not order the JFETs I would prefer. The reference voltage gain by R7 R19 R8 has no effect on noise above about 10 Hz. Of course, a higher Vgs would be better. Stacking of JFETs is questionable: stacking is better if we are in the white noise region, but this noise contribution is filtered out anyway. If we have 1/f-noise or even random telegraph noise, stacking is not helpful since noise is added (sum, not sqrt(sum)) - correct me if this is wrong.

[Kleinstein]

Even with RTN type noise using more FETs helps. The jumps are non correlated and with "averaging" the individual contributions one gets an even linear reduction in the step size. So with 2 refs in series the jumps don't get larger, just more frequent. So using more FETs would also help in the RTN regime range. For a certain time range the peak to peak noise may not go down, but the RMS noise still should give the the normal square root N reduction in noise, as the parts are uncorrelated. More frequent smaller steps may be even preferred over rare large steps.
Stacking can make the TC compensation more tricky though.

The fets have quite some scattering  ( I got 2N4391 with around 7 V ref voltage, while Dietert got some more around 5V), but there is still a choice in the types.  The 2N4391 should be mainly be in the 4-8 V range. 2N4392 would be more like 2-5  (have not checked the exact numbers). So one has some choice.
The 2N4416 is a more lower threshold fet and also lower current and thus maybe better for battery operation.
It is also one of the few more affordable ones in a hermetic case.

It may be possible that the TC correction does not work as well with a high threshold FET. At least the rather high (7 V range) threshold fets may behave a bid different from the usual models. There may be also a slight different between different types: the process 50 of the 4416 is more like made for RF use, while the process 51 for the 2n4391 is more made for switches. These types may differ in series resistance in addition to the actual FET and this can be part of the temperature dependence.

There may be even some advantage in not having too high a voltage per FET: at least for the normal amplifier operation there are curves in data-sheets that show that the low frequency noise goes up if the drain source voltage goes up, especially higher than some 5 V. For me it is not clear if the drain source or maybe he drain gate voltage is the relevant voltage. In my test I have not seen a large difference between J113 and J111 / 2N4391 , but RTN noise is not that reproducible and can vary between units.

[IconicPCB]

I think process 52 is better suited to the JVR needs.

[dietert1]

Can you tell us how you arrived at this opinion?

Just found this description of a JFET selection setup and results: http://www.geofex.com/Article_Folders/fetmatch/fetmatch.htm
I think he is correct in not looking at the pinch-off voltage, but at a useful operation point.

@Kleinstein: I looked at four 10x batches of JFETs: J105, 2 batches of 2N4391 from different sources and a batch of BF247C.

Regards, Dieter

[Kleinstein]

The process 52 looks good, as it is used for relatively low noise audio use. So one can expect a low noise. The other important paramterer is the current range where to expect low TC.
From the typical graphs in Fairchild AN6609 one would expect them to get low TC at some 0.2 to 0.5 mA , though it is not accurate to tell from the graph. There is also more than just the mask  - the doping can also effect the properties.

The problem may however be to get suitable ones with a not too low Ugs, especially if one wants a hermetic case.

The process 51 (e.g. 2N4391) can also provide low noise, though at a higher current. Still some 1-1.3 mA is not that bad. It may not be the best choice for battery operation, but higher current helps with low noise. The nice thing is that the 2N4391 is readily avialable at a relatively good price.

Higher current fets (e.g. J105) may need to run at so much current that self heating gets a real problem.

For amplifier use there seem to be a preference for a relatively low threshold at some 0.5 to 1 V. So especially the lower noise types are usually not a vailable with a higher threshold more useful for JVR.