Building your own voltage reference - the JVR

[SilverSolder]

If the design of the JFET reference is standardized, it might be possible to automate the tuning of it?  There could be digital pots on the board to facilitate this, for example.

[Kleinstein]

For the simple Fet based refrence tuning 1 resistor is not that difficult. From the FET data books just linked a few posts before there is a approximate formular for the TC as a function of the fet current:   TC =~ 2.2 mV/K * (1 -  sqrt(I/I_0))    , with I_0 the looked for current for zero TC.   Chances are one can find a good resistor with only a few iterative steps.
With just a simple adjustment, one may need a kind of crude oven to get a low TC over a larger temperature range.

For the multi point adjustment, to also compensate higher order TC things get more tricky. The part around the BJT should reasonable well follow the usual spice models, so one might get away with a crude resistor choice and then a temperature run in an oven to than calculate suitable resistors for the remaining 3 resistors that may be accurate enough. digipots are OK as a divider, but often not good as a variable resistor. With not too large a temperature range, one could get away with less trim (e.g. only the 2 nd order), or possibly the same resistors for a whole batch of similar fets. The higher order TC part may not scatter that much as the voltage. Chances are actually good that it is relatively constant for a given type of fet.

Another weak point with the JVR is that one never knows up front which voltage to get. So one may also need to adjust the gain, or select FETs with the right voltage.
Some 4 - 8 V is quite a large range for a single type of FET (2N4391).

The 2N4416 may not be that bad a choice for battery operation, as the current is relatively low, maybe allready too low to get really low noise.
The 2N4391 is also not ideal - also has a relatively short channel and thus a relatively high sensitivity to the drain voltage. It is acceptable, but still also needs good resistors to generate the drain voltage.

The observation about the temperature is interesting. I had a similar observation on cool down of the oven from elevated temperature, that confused me. Attached is a graph showing the voltage change of my reference in the oven. The jumps of up to some 15 µV look bad, especiall compared to the rest of the noise. The readings are relative to a relatively low noise LM399 -  so some of the noise (specially the higher frequency part) is from the LM399 and also from the ADC.

[MK]

Another source of noise that is batch dependant is G-R (generation-recombination) noise caused by trace amounts of other elements, the GR noise comes and goes at different temperatures depandant upon which stay element is causing the issue.

[IconicPCB]

As mentioned in the earlier post I had contacted interfet with the view tosourcing less expensive options.

The response from Interfet sales eng is as follows:"...

Interesting project. We Have 2N4391 in stock at mouser if needed to prototype.  https://www.mouser.com/ProductDetail/InterFET/2N4391/?qs=M%252BdZJzgoW%2FVlkPfqcj1FRA%3D%3D

 

Nice app note for biasing to zero drift.

https://www.interfet.com/jfet-datasheets/jfet-an-107-interfet.r00.pdf


We can customize matched pair solutions and steer you toward some more of our higher volume parts. The IF1320 and IF4500 are more higher volume parts. And they are in the ballpark of the 2N4391-3, J111-3, and J108, J109 parts.

..."

He had also included the plot  Variation of Vgs with temperature at zero TC bias.

It is beyond belief ... or at the very least my comprehension.

[IconicPCB]

National Semiconductor
NOS

2N3684

N-JFET
Low Noise AMP,
V(BR)GSS=-50V(min),
VGS(off)=-2V to -5V at VDS=20V,
IDSS=2.5mA to 7.5mA at VDS=20V,
rDS(ON)<=600 OHM at VDS<=0V
in TO-72 PKG

Bulk buy US$0.52 per piece.

Interest invited

[dietert1]

I'm getting a bit lost. You proposed to operate the JFET as a constant current device (in the saturation region). In that mode Ugs is small and the control potential is hidden inside the device. Saturation current for a 2N4391 is 50 .. 150 mA and i understand that you propose a different JFET with higher channel resistance.
Now that TC compensation is a different story. It means operating the JFET close to Ugs,threshold. Or can we get TC compensation in the saturation region? Should we control Uds?

Regards, Dieter

[Kleinstein]

The 2N3684 seems to be a small fet (process 52)  maybe a little similar to the J203. My crude estimate for the zero drift curent would be some 200 µA (typical Idss for the low threshold brother 2N3687). The datasheet I found is a bit confusing, as it gives IDss of 0.1 - 0.5 mA, but also  Gm > 0.5 mS, which would suggset a higher current.  Noise specs are more on the high side.

So it would be something for a low power reference, not so much a very noise version, though the relatively large input capacitance may help.
There is also a risk to get a relatively low votlage - chances are a batch can be all similar. So Bulk buy is some risc.

IF1320 and IF4500 are low threshold devices and thus not really suitable for a JVR. They may be nice amplifiers. The choice of high threshold devices is not that large, as low noise amplifier more like prefer low threshold and with improving manufacturing precision, there is a chance to get fewer batches with lower than intended threshold.

In an Phillips DS I found an interesting graph, showing Ids versus temperature. There it looks like the 2nd order effect changes quite a bit with current. So version for Dietert with the diode an the low side may not be so bad after all and may even reduce the 2nd order effect, by operting the FET at a slightly lower current.

[dietert1]

After reading some of the documents linked above, i think i was trapped with wrong assumptions and results before. As i did not yet have the recommended 2N4391 when i started experiments, i used a batch of J105 we had left from repairs. The result was a positive TC up to drain currents of more than 5 mA. Also there was the remark of Kleinstein, that we should try to find a solution without the requirement to fine tune the precision resistor in the source path. That made me go away from the original proposal.
I learned that zero TC operation of a JFET involves compensation of a -2.2 mV/K TC, which is of the same magnitude as in the compensated zener reference.

Some days ago i tried the zero TC adjustment again with a 2N4391 and - surprise - it arrived near zero at about 2 mA. Perfect. TC also depends on the drain voltage: The lower the drain voltage, the lower TC. This way one can adjust the same 2N4391 to zero TC at 1 mA drain current. Then the zero happens at Uds around 0.3 V. At 2 mA the zero happens at Uds = 2 V, at 2.5 mA at Uds=7 V. Of course, these numbers will be different with another 2N4391.
The JFET will be in saturation anyway (near cutoff). Measured feed through for small voltage variations from drain to source was 0.14 at Uds = 0.3 V. Running the JFET with a small "detection" voltage along the channel may be a good solution.
Will report some measurements later. Datasheet curves are of little use due to lack of precision. This application is very special and nobody does the TC characterization to ppm level. It's a setup that supports drain current variation, Uds variation and temperature variation and precision measurement of each parameter. How can one measure the JFET chip temperature? Maybe using the gate diode in forward mode..

Regards, Dieter

[IconicPCB]

On JFET noise; I am under the impression that the noise sources in a JFET increase with drain  current.

Should we therefore not look for devices in the lower "portable equipment" range of drain current?

[Kleinstein]

Normally the noise goes down with larger devices, as they are internally a bit like many small ones in parallel.
For the JRV use the current density is kind of fixed to get a zero TC without much extra compensation.
One can do small changes via the DS voltage, but this should not be very much, unless one would go down very much (like the 0.1 V range). I am already a bit surprised that the shift that Dietert reported for the 2N4391 is so large (1 mA at 0.3 V to 2.5 mA at 7 V).

There are curves in some FET data-sheets that show that the noise goes up the DS voltage higher than some 5 V, though not much effect below 5 V. However I am not so sure how reliable those graphs are - they looked too smooth to be actual measured values.

For testing some lower current devices may have an advantage, as they have more noise and thus make the testing easier. There is also a larger chance to find a defect free device with smaller ones, though not sure if this is in reach at all.

The problem with higher current devices like the J105 is that the heat dissipation gets quite large - not so much in the FET, but for the resistor and the overall circuit. The drain source voltage can be kept relatively low (e.g. 1-2 V range), so that the fet itself does not see that much power dissipation.

[IconicPCB]

Opinions sought on suitability of 2N4091 devices.  A process 51 ( National Semiconductors ) device.

[dietert1]

The Interfet datasheet says cutoff voltage is 5 to 10 V. A Microsemi datasheet found on the web says Rdson = 30 Ohm at 1 mA. So it appears to be similar to the 2N4391 and suitable as a JVR. Maybe same process and same selection category means "another name for the same".

Regards, Dieter

[IconicPCB]

Yes... both come from the same process family.

Available for a sub USD1.00 in reasonable quantity( tens of pieces not hundreds).

[Kleinstein]

For practical purpose the 2N4091 is identical to 2N4391. The specs are essentially the same with slightly stricter upper limits for the 4391, but this could be just different test limits.
The J111 is also essentially the same (though usually TO92). I have seen a DS for the 4391 that tells to look at J111 for the typical curves.

Chances are die difference can be larger between parts from different manufacturers.

At least some of the 1/f noise is supposed to be due to impurities and these can be different depending on the source.
For the now obsolete BF862 there were reports on differences between 2 different Phillips fabs.

[DeltaSigmaD]

More results of my JREF project, please see Reply#243 at this topic. The results are somewhat mixed.

Results of analog compensation technique

1. A number of temperature-compensated JREFs were assembled and tested. The spacial separation of JFET and BJT (temperature sensor) induces a 0.8 ppm position dependency of the compensation and therefore also of the reference voltage. The output stability and noise is analysed by the calculating the Allan deviation of the reference voltage. Fig.1 shows the Allan deviation of a 10V reference with a 2N4391 JFET measured by a Keysight 34470A (after an 1 day warm-up) before final adjustment. The classical Allan deviation is green, AVAR is red, and MVAR is blue. A yellow slope in the double-logarithmic scale can be added to show the exponential law of deviation. The JRef noise is close to the K34470A noise at about 5s. The circuit also shows a linear drift (slope +1 at right end indicated by a disappearing distance of AVAR and MVAR) even while it is temperature-stabilised at the zero TC point. This drift is caused here by the very slow relaxation of the 2N4391 after a thermal 20 K step. Fig.2 shows the Allan deviation of a 2N4416 5V reference (Siliconix, 39 years old) in a non-stabilised room environment. The noise of a RF JFET is higher, but the complete circuit had +2 ppm drift within 2 months (measured by the K34470A, caution: specification +/-14 ppm in 2 months) and no significant hysteresis. The reference voltage is within 2 ppm about 5 minutes after power on, and within 0.4 ppm after 4 hours. Unfortunately, the JFET was selected not carefully enough: it shows some random telegraph noise (RTN) of 1 ppm, see Fig3.

2. The third and forth order compensation of the temperature dependency of a JREF reference by an analog circuit is possible, very stable, and it doesn't add significant noise. Within a 18°C to 35°C range, a temperature dependency of <0.2 ppm/K can be obtained. But, the adjustment of the analog compensation is difficult. In practice it is very complicated (if not impossible) to distinguish thermal hysteresis, drift of components such as resistors and trimmers, and circuit temperature gradients from the real thermal drift of the JFET reference voltage. The essential point is that modifications of hardware are required to adjust the compensation, but the thermal conditions are changed when you are performing these modifications. If you change a trimmer position, you have to wait about 1 hour before you can measure its effect precisely. Then you have to measure the reference voltage at >=5 temperatures. The available working time limits the number of different JFET types which can be tested. I have no realistic idea how to automise the adjustment. The adjustment is so much work that the analog adjustment technique is refused even while it is working well in a limited temperature range.

3. Several different JFETs were tested for low frequency noise by measuring the Allan deviation of a suitable reference circuit. No JFET was found which had only pure white and 1/f-noise. Even parts of the same type, manufacturer, and lot differ extremely with regard to low frequency noise like Random Telegraph noise (RTN). Concluding, all JFETs must be selected for minimum low frequency noise. According to my experience, <5% of JFETs are suitable as reference. Unfortunately, the RTN depends on temperature, working point, thermal history, and so on. A JFET selected for low noise might have high noise at a differing working point. You need luck. Even zener refs are not better in this point (potentially excluding the LTZ1000).

4. Some 4391 and 4392 JFETs of different manufacturers were analysed (Central Semi and dsi with lower noise, other m. were not available at this time). These JFETs had relatively low 1/f-noise superposed by a varying amount of RTN. However, the tested devices had a thermal hysteresis >5 ppm with 10 K steps and a relaxation time constant of many hours, which property prevents the application as reference. Please consider that 439x JFETs of other manufacturers might be better. The tested 2N4416 JFETs (original Motorola, 30 years old, and Siliconix, 39 years old) had a thermal hysteresis <1 ppm. RF-JFETs, which have separate pins for gate and case (4 pin JFETs as the 2N4416), must have any isolation layer between gate (mostly the JFET die) and case. The long-term stability of the Siliconix 2N4416 reference seems to be very good. It is an obvious guess that this layer reduces the thermally induced mechanical stress on the JFET die. It would be very interesting to know more about this subject. 

Current status of the project

A new battery-operated JREF circuit will be tested soon (new PCBs are already delivered), which uses a digital compensation technique of the JFET reference voltage drift. The reference voltage is adjusted at several temperatures by generating an adjustment voltage. It is planned to use a third order interpolation parabola or spline between the temperature points. The JFET sees identical surrounding conditions at adjustment and normal operation except the surrounding temperature. It is interesting that the REF70 of Texas Instrument also uses a certain kind of digital compensation of the reference drift, however, it seems that the REF70 uses a completely different technique.

[Vtile]

Could it be possible to find "extra pure" samples by deep freeze the samples? If the RTN etc. are increasing at low temperatures one would assume that testing the samples at low temperatures could be beneficial.

Also have one tried (or come across of public information) effects of cryogenic bath for JFETs , ie. liquid nitrogen (~77Kelvins). I have a few possible outcomes in my mind. First it must be destructive for big percentage of components because of (micro/macro)mechanical stresses and shock, but what happens to those that would survive, would they be the best samples (as randomly manufactured) of lot. Assuming the RTN are partly from mechanical flaws of die. Would it possibly permanently change the silicon (assuming this is doping related) micro structure. Would the resulting samples be garbage.

Just random thoughts without (any) knowledge.

[DeltaSigmaD]

JRef: Comparing noise of references by measurement of Allan deviation

The temperature dependency of JFET noise was analysed in the paper of J.W. Haslett, E.J.M. Kendall: "Temperature dependency of Low-Frequency Excess Noise in Junction-Gate FETs", IEEE Transactions on Electron Devices, Vol.ED-19, No.8, August 1972. Even if this paper might be outdated in some points, it is very helpful to understand the JFET operation better. A coarse estimation leads to the guess that a single trap in the depletion zone is sufficient to be a source of RTN with 1 ppm amplitude. In this light it is obvious that you cannot expect common rules to select JFETs, for instance the measurement at one temperature to derive the expected noise at another temp.

It is interesting to compare the noise of bandgap, zener, and JFET references. Modern Bandgap references such as LT6655 have low noise, but relatively high long-term drift. Even good buried zener refs such as LT1236-5 show RTN, see Fig.4, the corresponding Allan deviation shows Fig.5 (linear drift was removed). The RTN noise is almost hidden here in higher frequency noise, if no additional lowpass is applied. One could argue that the LT1236 already gives better noise than the JRefs, hence why using JRefs?

According to my measurements of Allan deviation, the noise contributions of references can be distinguished in the following components:
1. white noise: no problem, can be filtered out, low enough. Note: Allan dev. exponent -0.5.
2. 1/f-noise: if this noise is filtered, you have a constant uncertainty indepedent on averaging time. This noise is low enough with many references.
3. a region with a +0.25 exponent in Allan deviation: this noise region is produced by the superposition of a larger number of weak RTN sources, see f.i. the paper above. The longer you are filtering, the higher uncertainty you get. This noise must be minimised e.g. by selection. Even good zener refs have a wide spread of this noise within the same lot and type (my experience).
4. random walk: this noise is generated by the integration of "white" noise over time. The random walk is the most important characteristic for the long-term stability. The "long-term drift" of many references looks like random walk, for instance LT1236 or Ref70, where an additional relaxation is superposed. Refs cannot be selected for this noise due to the extremely long duration of selection. Note: Allan dev. exponent +0.5.

Datasheets of references only talk about white noise (e.g. 0.1 to 10 Hz noise), sometimes even about 1/f-noise. But I never have seen specifications or measurements of the most important contributions, noise 3. and 4. You have to measure it yourself. The fine thing with Allan deviation is that you can distinguish these 4 noise contributions by analysing the slopes of the Allan deviation you measure. Additionally to the noise above, we also have exponential and linear drift of references. Both contributions are indicated by a +1 exponent slope of Allan deviation. In this region the difference between AVAR and MVAR disappears or changes its sign slightly.

Now the essential point: I have the impression that the JRefs have a lower Random walk component than zeners or bandgaps. If true, this would be reason enough to use JRefs. I urgently hope that this first impression (only 4 months) can be verified in future. We will see.

[Kleinstein]

If the noise changes with temperature (more than just a normal ~ T or sqrt(T) behaviour), than higher order TC compensation may not be a real option for lowest noise. So one may have to use an oven for a stable temperature to operate the reference in a sweet spot region.  The temperature stabilization would than be more than just for the TC, but also to avoid higher noise, to keep the FET operating more at a sweet spot.
Beside the temperature the drain source voltage would be a 2 nd parameter to choose for the operation point. One has at least some freedom there. So far I have not seen an obvious advantage of larger ( ~5 V)  or small (~0.5 V) voltages.
A different temperature or different DS voltage will shift the region that has a very high effect, so that single long lived electron states could cause strong RTN noise. So the same FET may work well at 1 temperatur and be noisy at another.

For the JFETs the white noise is no problem, but I am not so sure about the 1/f noise.

With the test from the difference of 2 JFETs even what looks like 1/f noise seems to be the superposition of many RTN sources, just with rather small size (200-300 nV).

[SigurdR]

No, en goes down with higher Id.
en ~sqrt(sqrt(Id))
so only to the 4th power

I run my JFETs as close to Idss as possible without increasing Pd too much as heat is a JFET "enemy". Low Vds is thus often used.
But capacitances go up with lower Vds.

Gate current goes up a lot with temp, and gate current we do not want.

JFETs are great for low noise applications - especially above 10Hz.
I have used them for decades for low noise phono amplifiers. Especially the Toshiba types (that now are discontinued) or the BF862 (disc.) or the ones from Linear SYstems (2nd source to some TOshiba types).

Researchers seem to like the IF3601/2 for their ultra low noise even below 10Hz.

On JFET noise; I am under the impression that the noise sources in a JFET increase with drain  current.

Should we therefore not look for devices in the lower "portable equipment" range of drain current?

[Kleinstein]

For use a a reference the drain current for a given FET can not be changed much, as this effects the temperature coefficient. So the current is fixed be the need to get near zero TC.
To get a useful reference we also want a FET with a reasonable high threshold, like 4-8 V, as the noise is kind of relative to the threshold voltage minus some 0.6 V or so.
The JFETs used for the low noise amplifiers are usually rather low threshold, e.g. in the 0.5-1.5 V range and thus not useful as a voltage reference.
Increasing the current helps a little with the white noise, but even less with 1/f and other LF noise. So for very low frequency amplification one more like wants a rather low current to limit the heating and thus reduce thermal effects. It is more about using large area FETs or multiple in parallel and than less current per FET.

One can use some results from amplifier, but even here the data often do not extend much below 10 Hz and for a reference we care about the lower frequencies only. At 10 Hz the JVR is usually very good, the tricky part is the long time scale of hours and more. Even the usual 0.1-10 Hz range is also still good. My estimate for the 2N4391 I have tested is somewhere in the 1 µV_pp range as a typical number.

[Alex Nikitin]

It is good to see so much work done on the JVR, looks very interesting. I was more or less off the forum for almost a year and a half, however now I am planning to be more active and can only add that my original JVR unit is still running 24/7 and I can not see a substantial drift (still below 5ppm compared with my 731B and several calibrated meters, including 3458A Option 002) .

Cheers

Alex

[d-smes]

@Alex,
Welcome back!  It seems all your attachments before Post 102 (and some after) have disappeared.  Would you be so kind as to re-post your original circuit and some of your more interesting trend data?   Thanks!

[H202]

docs1

[H202]

docs2

https://www.scribd.com/document/529788436/ED-DC-Amp-Design-With-FETs-Zero-TC
https://www.scribd.com/document/529788585/ED-Stabilize-T-to-1e-5-Deg-With-Linear-DC-feedback

[dietert1]

Seems like in 1966 a TEC was an available part and called "Frigistor".
Yes, back to the roots. Yet there has been some progress. While those inventors had good ideas, they did not have the means to fully explore them. Today even hobbyists can make automated, all digital curve tracer setups that work to 1 ppm or below.
My logs of a dual JFET 10 V reference i made early this year (see above) exhibits a steady drift of 130 nV per day (4.75 ppm/year), without any indication of relaxing. Deviations of the daily averages from linear drift ("noise") are 430 nVrms (0.043 ppm), while the setup is good for 100 nV or better.

Regards, Dieter