Building your own voltage reference - the JVR

[Kleinstein]

One still needs the OP-amp to do some amplification of the source voltage. So one would either use the amplified votlage from OP-amp or the source votlage without gain, but a bit higher impedance ( the resistor and some 150 ohms  (1/gfs) from the FET.

So far I found the compensation of the 2nd order effect tricky and prone to add drift.  So my preferred way is a regulated temperature.

[iMo]

Yes, it's great to use the second JFET for TC adjustment (on-chip sensor). What would be the reference voltage?

I've just tried with my dual jfet DGN349 (bootstrapped by an OP07, standard wiring) and I get around 0.75V at 0.4mA Ids.. (max 0.86V with 5k resistor).

[dietert1]

That low reference voltage is a disadvantage for many applications. In my case i want to add a 10 V gain stage, to make it into a 10 V lab reference.

Regards, Dieter

[EC8010]

I discovered this thread yesterday and read all of it. A few thoughts:

The reference holds a constant voltage across a resistor. Therefore, the reference circuit is a constant current source, even if MacHattie didn't say so. That being the case, if you want a larger reference voltage (perhaps 10V) all you need do is add another resistor to 0V below the junction between gate and source resistor. Obviously, it needs to be a resistor with minimal drift. You still need a buffer to avoid loading, but it can be unity gain. You save one precision resistor.

I have measured J112 noise at 1.65mA. White noise is 1.4nV/root Hz, with 1/f noise corner at 13Hz. It's quite quiet. BF256B/2N4416 (at the same current) is rather noisier; 3.3nV/root Hz.

I flashed up cascode circuit using two J112 and decade resistance box. Measured current for minimum temperature coefficient is dependent on VTO as others have suggested from theory. With VTO = -3.55V (average value from my batch of J112), current for minimum tempco was 2.975mA using the two FET cascode circuit. Smaller VTOs had larger currents for minimum temperature coefficient.

SPICE simulations of the cascode circuit will be poor because SPICE models the transition from resistive region to saturation region too sharply. Let alone whether the SPICE model vaguely matches the particular FET you test.

I monitored cascode reference voltage on 34470A (7 digit DMM). Once circuit had settled, voltage was quite stable but trend plot showed popcorn noise (voltage steps typically of 1uV). I have not yet tested to see if that's an isolated example or whether all my J112 suffer.

Despite all the previous caveats, the JVR looks to be worthy of further investigation.

[Kleinstein]

1 µV steps for the popcorn noise look quite large - not sure how the use of 2 fets is effecting this. In my tests I had steps more like 0.25 µV for J111,J112 and 2N4391. The noise (especially the 1/f cross over and frequency of the popcorn jumps) may vary between units / manufacturers.

With relatively similar noise for the J111 and J112 it makes relatively little sense to use 2 x J112 in series, as a single J111 would give a comparable voltage, but with than less noise than the 2 FETs combined.
The 2N4391 is attractive as it is available in a metal case.

A point to watch is that there is often still quite some 2nd order TC. So one has a low TC only over a limited temperature range.

[ch_scr]

I've stumbled across a "historic" reference (well, 1980) to the idea, only downside: it's in German. I've also attached a rough-n-ready translation that should hopefully be enough to get the gist of it.

[dietert1]

After an observation period between April 2nd and May 8th i calculated these noise levels comparing hourly to 24h averages (all 10 V references):
LTFLU1      0.13 uVrms
Dual JVR   0.37 uVrms (in oven as shown above)
ADR1399  0.28 uVrms

The LTFLU1 has half the noise of the ADR1399 as it is a 4x array.
Considering parts cost the JVR is a very interesting solution and probably its noise could be reduced reviewing my original setup. Don't know whether the dual JVR should be considered an array. I think its noise is less than that of a LM399.

Regards, Dieter

[EC8010]

I wouldn't have thought that operating as a cascode would affect noise of the voltage across the source resistor but I will experiment. (And grab some screenshots of popcorn noise.) Over the last few days I've been working to improve my measurement capabilities:

I used an eight decade 0.1% resistance box to determine resistance for minimum JVR tempco, but it was a modern one using metal film resistors over ten ohm and the switches aren't wonderful (might be producing popcorn noise). I have a much older 0.1% four decade box that uses only wirewound manganin resistors (minimal excess noise) and wonderful switches with multiple wipers onto brass studs, but (being wooden) it's unscreened. I've just made and fitted a foil liner that folds over the top edges of the wooden box to make electrical contact all round with the metal fascia, to give a screened enclosure (minimises hum). I'd have replaced its terminals with BNCs (as I did on other box) but that would require too more metalwork for this box than I'm prepared to do.

I monitored JVR current, but the standard deviation of the current measurement was much higher than expected from the standard deviation of the voltage measurement, suggesting that the low current ranges of 344xx series DMMs are a bit noisy. Next job is to make a transimpedance amplifier using; OPA1641, wirewound feedback resistors, and LT1010 buffer to minimise heating in the op-amp. Using 1k, 10k, and 100k current conversion resistors, I can have 10mA, 1mA, and 0.1mA FSD on the 344xx's basic range of 10V. Should be quieter and allow better measurements. And have negligible voltage burden.

I will power JVR from 12V 2Ah lead-acid battery to eliminate mains-borne interference. Also, lead-acid battery is much quieter than bench supplies.

[Kleinstein]

The HP34401 noise is in most ranges higher than a J111 / 2N4391 base JVR reference. This definitely effects the current range, but even the 10 V range may well be higher noise. From my tests the noise if the 2N4391 is somewhat comparable to the LM399 ref used in the 34401 or similar meters, though a bit different shape in the time domain (LM399 has white noise plus relatively rare but large popcorn noise jumps between 2 levels, the 2N4319 is lower white noise, but more, smaller jumps with also more steps). So even with a perfect TIA one would not be able to really see the JRV noise directly with the 34401. The best chance to look at the noise would be having 2 JVRs and looking at the difference in the voltage in the 100 mV range (maybe 1 V range could work).

[EC8010]

I have a dedicated low noise (<1nV/root Hz) set-up for measuring noise, so I'm not worried about the basic noise of the the 344xx. It's just that I've discovered the current measurement weakness and can do something about it. A year ago, I experimented with a REF102 10V reference and logged it over >1000hrs. It had a little popcorn noise <-120dB, which was observable on the 34470A's 10V range on a trend chart and also on my noise measuring set-up. Yes, I've used the technique of looking between two voltage references to give a 3dB increase in signal to noise. For the moment, I'm just using the DMMs to see low frequency trends. Once I'm happy the set-up is good, I'll bring the big guns to bear. I'm interested in the circuit more as a low noise two-terminal CCS than as a voltage source. But observations as a voltage source are a convenient way to start.

[Kleinstein]

The current from the JFET depends on the drain voltage. Especially with FETs with a high threshold the drain voltage has quite some effort. This is why the reference is nomally used with a bootstrapped voltage for the drain. As a minimum solution one would have something like a J112 as the main reference to set the current and a J111 (higher threshold) to get a stable drain voltage in a cascode like circuit.

[magic]

As a minimum solution one would have something like a J112 as the main reference to set the current and a J111 (higher threshold) to get a stable drain voltage in a cascode like circuit.

You could use any random FET with the gate bootstrapped to the source of the reference FET.
If the cascode FET is matched to the reference FET, you will even get some stability against temperature for all the same reasons as why the reference is stable.

Note that reference drain voltage ripple/drift will only decrease by the ratio of the common source voltage gain of the cascode FET. And I seem to recall from Horowitz&Hill that it tends to be maybe a few hundred tops for typical JFETs. It will surely decrease if there isn't enough drain-source voltage across the top FET, for whatever value of "enough" is enough.

edit
The same "a few hundred tops" limit also applies to PSRR of the reference itself.

[dietert1]

Can you say "a few hundred tops" in other words? For those who did not study the AOE. Thanks.

[EC8010]

The current from the JFET depends on the drain voltage. Especially with FETs with a high threshold the drain voltage has quite some effort. This is why the reference is normally used with a bootstrapped voltage for the drain. As a minimum solution one would have something like a J112 as the main reference to set the current and a J111 (higher threshold) to get a stable drain voltage in a cascode like circuit.

Surprisingly, a higher threshold device isn't the best choice for the upper FET. You'd have thought it would be because it ensures that the lower FET is clear of the resistive region. But I measured source impedance of two-FET cascodes with high and low VTO devices and found that the highest source impedance came from using a pair of low VTO devices. It seems that r_d falls faster than g_m rises as VTO rises. My initial tests were with a cascode using J112 from the same VTO bin for exactly the reason that magic stated.

But I think I disagree with your common source voltage gain argument. Given that we don't have an explicit load resistance, it's better to treat the circuit as a CCS. Even with J112 (in a two-FET cascode) it is possible to achieve an internal resistance of 1M, so that gives a rejection of 1,000,000/1,000 = 1000. Adding another FET on top (as per MacHattie) makes it even better. But even an attenuation of 1000 might not be enough, and that's why I'm looking to improve my experimental set-up.

[magic]

Can you say "a few hundred tops" in other words? For those who did not study the AOE. Thanks.

Less than one thousand

I looked it up, it's table 3.7 in the 3rd edition, parameters of some common JFETs. It includes maximum attainable common source gain, presumably measured by the authors, analogous to μ of vacuum tubes. They call it "Gmax" and it's a 3 digit number for all listed types, 100 for J112.

Gmax they define as: Gmax=gm/gos, the maximum grounded-source voltage gain into a current source as drain load; Gmax is proportional to VDS (tabulated values are at VDS=5V), and for most JFETs Gmax is relatively constant over varying ID.

Where gm is, of course, the transconductance and gos is the output conductance of the drain.


My logic as to how this is relevant is simple: 1V change in drain voltage results in gos change in drain current. This must be countered by gos/gm change in gate-source voltage to maintain the same or approximately the same drain current. Hence the change appears at the source divided by μ a.k.a. Gmax, provided that the circuit between the source and gate has reasonably high output impedance on its own.

I would therefore expect each cascode layer to increase output impedance by the factor of μ.

[EC8010]

I would therefore expect each cascode layer to increase output impedance by the factor of μ.

And so would I. I hadn't measured μ for J112 - 100 is disappointingly low. But it was originally intended as an analogue switch. Still, add enough layers and it will be fine.

As a general comment, AoE 3rd Ed. is superb. And "The X Chapters" is even better. Anyone who finds AoE 2nd Ed. useful will love them.

Low noise transimpedance amplifier is on the schedule for today.

[EC8010]

As I suspected, my previous test setup wasn't brilliant. Source resistance is now all wirewound resistor decade box (negligible excess noise). Power is 12V 7Ah lead-acid battery, and the popcorn noise has disappeared. Source resistance is super-critical for minimum drift; presently set to 1k116. Although the two J112 are from the same VTO bin (-3.5V to -3.6V), they weren't matched. It's quite possible that lower thermal drift would be achieved by matching VTO.

[Kleinstein]

Most of the JFETs also show quite some square part in the votlage vs temperature curve. Trimming the source resistor only trims the linear TC and thus the TC over a rather small temperature range.
To get a really stable voltage one would need either additional square law trim (which is tricky) or some temperature regulation.

[EC8010]

I fear you are absolutely right. Leaving it running, its drift spans 33uV, or 10ppm. And it was really finicky to get it to that level.

[iMo]

That drift might have come from your decade box..

[EC8010]

Yes, although my box is 0.1% tolerance, that would be enough. 15 hour drift now spans almost 0.1mV. A 0.01% metal foil resistor would be better, but a 1k 0.01% main resistor would need a 110R 0.1% resistor in series, plus a 1% to trim the last bit of current. I'll have a look at the noise later, but considerable improvement would be needed before it could really be deemed to be a voltage reference. Looks like J112 is not a suitable choice for JVR.

[iMo]

Try to made your ~1k1 resistor of couple of ser/par resistors with lower TC, like <25ppm, and then finetune the final value of the "resistor" such you compensate for the TC of the jfets "including the resistors" as well.
The jfet's TC shape allows to compensate out the TC of the resistors too..

[Kleinstein]

There is no need for low tolerance lke 0.01% resistors. The point is getting low noise (little excess noise) and low drift (versus time). Already the resistor TC is less critical as one would trim the combination of resistor and JFET for a low linear TC.  I got good results with the Susumu RR SMD resistors with low excess noise to a level (some 45 dBi) - well good enough for the reference.
The usualy way is anyway to have the main part of the resistance from 1 - 3 stable resistors and than have additonal less critical trim resistors. The final one to choose for the trim can be about any type as it has little effect.

The J112 is not that bad, mainly limited with the plastic case that can make is susceptible to humudity effects. So far my favorite is the 2N4391, as one of the cheaper ones in a metal case and relatively well available. The current (1-1.5 mA) and voltage (around 5-8 V depending on the batch) are reasonable.

[EC8010]

At the moment, my resistor is a decade box 200mm away from the JFET, and therefore at a different temperature, which won't help matters. Now that I know roughly what resistance is needed, I could put smaller fixed resistors adjacent to the FET, reducing the temperature difference, and maybe cancel one tempco with the other. Maybe. On the bright side, although the J112 reference drifts, it is low noise. Sufficiently low noise that a 5nV/root Hz pre-amplifier isn't quiet enough to measure it and I need to finish the tidy version of my 0.8nV/root Hz x5000 pre-amplifier.

I looked up 2N4391 and it looks to be a metal can version of the J111-3 series, but way more expensive. Fiddly and needing selection to work, I can perhaps accept, but not fiddly and expensive.

[dietert1]

Our dual JFET reference runs inside a pretty cheap IP66 aluminum enclosure that also serves as an oven (RS PRO 190-1860). With a used desiccant bag inside, relative humidity settles to a near constant value after some days. Don't start with dry desiccant, though! I saw variations less than +/- 0.2 %RH. In that ambient the J111 with its plastic case performs like a 2N4391 with its metal can. Same with resistors: No need for metal can resistors.

I used a flat cable with epoxy to make a (near) hermetic cable feed, see https://www.eevblog.com/forum/metrology/the-ltflu-(aka-sza263)-reference-zener-diode-circuit/msg2637174/#msg2637174. The Peltier element is outside of the bottom (invisible). Later i glued an NTC into the aluminum cover of the flat cable.

Regards, Dieter