### Author Topic: Design considerations for 8.5 digit front end  (Read 6521 times)

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#### sahko123

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##### Design considerations for 8.5 digit front end
« on: January 27, 2023, 12:44:18 am »
Context: I am designing an 8.5 digit ADC with surrounding voltmeter with a novel self-calibration technique as part of my final year project. (about which i will share but not until the project is finished).

As part of the ADC I need an input buffer and believe an ADA4625-1 unity gain buffer should be sufficient. Mostly because this is more about the ADC and getting a +-10V voltage digitized as accurately and precisely as possible. The following project would be about getting other functions such as I and R along with various voltage ranges but for now the ADC is the priority.

does anyone have any suggestions on the input buffer or should it be more than enough for the project at the moment?  Is there anything Im missing? or should this suffice?
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#### coppice

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##### Re: Design considerations for 8.5 digit front end
« Reply #1 on: January 27, 2023, 01:06:07 am »
Lets says 8.5 digit means a maximum count of +-200,000,000. The step size for 10V would be 50nV. An ADA4625-1 seems to have a offset voltage spec of 80uV typical. Does that seem suitable? Even if you are frequently self calibrating away that offset, just how well temperature controlled would the op-amp need to be tame its offset voltage drift to 50nV between calibrations?

#### sahko123

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##### Re: Design considerations for 8.5 digit front end
« Reply #2 on: January 27, 2023, 01:13:51 am »
The offset voltage of 80uV I should be perfectly fine. but the tempco can possibly be better. The typical is actually +-0.2uV/C with a maximum of 1.2uV/c
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#### iMo

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##### Re: Design considerations for 8.5 digit front end
« Reply #3 on: January 27, 2023, 11:48:35 am »
FYI - not targeting 8.5digits, but an attempt to find a simplest way to create an AFE for the high-end single chip ADCs.

#### Kleinstein

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##### Re: Design considerations for 8.5 digit front end
« Reply #4 on: January 27, 2023, 12:01:07 pm »
The offset (and drift) is one of the lesser problems if the front end does some kind of auto zero by switching between different inputs, including a 0 V (or similar).  The CMRR could be a liniting factor for the linearity.  With typ. 130 dB this not enough to guarantee better than 0.3 ppm INL. However chances are that much of the CMRR is still linear - so from this side it can be just acceptable, though not great, when hunting for possible sources of INL.
Another important parameter is theg gain, as this effects how good the OP-amp can compensate for internal nonlinearity, especially the output cross over. Here the ADA4625 is quite good - though the cross over error could still be a point to whatch for. With the OPA145 I was able to see that type off error. Adding a constant current load can avoid the cross over error by operating the output in a class A range.

For a buffer it is relatively simple to use a bootstrapped supply and this way essentially eliminate the effect of the CMRR.

An alternative buffer would be a Zero drift OP-amp like LTC2057 or OPA189. These usually have very good CMRR and gain, at lest for DC and low frequencies.

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#### miro123

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##### Re: Design considerations for 8.5 digit front end
« Reply #5 on: January 27, 2023, 03:56:26 pm »
1. What are the input parameter/requirements -  e.g. BW, input R and Z
2. What are parameters of of ADC input - e.g. does ADC uses SC circuit? Does the ADC input have constant/or linear R/C/L/Z?
3. what are the requirement for linearity offsets and drifts?
4. ADC input type - single ended or differential?
4. Do you really need such fast opamp? - the higher power consumption and associated thermals could create headache even at the 6 1/2 digit AFE
« Last Edit: January 27, 2023, 04:01:00 pm by miro123 »

#### K-Zoltan

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##### Re: Design considerations for 8.5 digit front end
« Reply #6 on: September 21, 2023, 06:40:46 am »
Here is a drawing with 8.5 digit voltmeter I made.

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#### Echo88

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##### Re: Design considerations for 8.5 digit front end
« Reply #7 on: September 21, 2023, 07:50:31 am »
Did you read up on the HPM7177? The only real OSHW project that i know off that actually shows a complete project with measurements coming close to a true 8.5 digit voltmeter.
You will have to spend plenty of time/money already to design a good DCV analog front end for your ADC, so i assume there wont be time for I/R-measurements.
Do you have the means to measure the resulting specs like INL accurately enough, like multiple 3458A or JJA-access?

If a high impedance analog frontend is needed you could copy the 3458A-frontend like i intend to do in a coming revision of my HPM7177-implementation, as suggested (not tested, work in progress) here: https://www.eevblog.com/forum/metrology/analog-frontends-for-dmms-approaching-8-5-digits-discussions/msg5034982/#msg5034982

#### K-Zoltan

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##### Re: Design considerations for 8.5 digit front end
« Reply #8 on: September 21, 2023, 09:06:07 am »
Here is the nstrument I made

High impedance frontend I used opa1289 and is in a metal case heat to 40 deg. C In place of relays I used optoflash TLP240.
3458 is an old 35 years (or more ?) old instrument full with discrete components. Now there are much better IC than ampifiers with discrete components.

#### dietert1

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##### Re: Design considerations for 8.5 digit front end
« Reply #9 on: September 21, 2023, 09:17:17 am »
For our Prema 6048 inspired design there is a voltmeter front end with a +/- 6V bootstrapped OPA189 or similar as single ended buffer, as the integrator is single-ended, too. There are three input relays for the two input polarities and null. The four ranges may become 24 V, 12 V, 2.4 V and 240 mV. While upper ranges are 1x buffered, for the lowest range the bootstrap gets turned off and there is 10x gain. I think the combination of a chopper-stabilized input amplifier with a relay to recalibrate null once the oven has reached stable temperature should be a good solution. The circuit preserves the "continuous integration" concept of the Prema.
Don't have measurements yet. Boards just arrived while i am writing.

Regards, Dieter

#### Echo88

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##### Re: Design considerations for 8.5 digit front end
« Reply #10 on: September 21, 2023, 11:11:12 am »
Very interesting K-Zoltan. Can you share more of your design?

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#### Mickle T.

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##### Re: Design considerations for 8.5 digit front end
« Reply #11 on: September 21, 2023, 11:43:56 am »
Here is the nstrument I made
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#### 2N3055

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##### Re: Design considerations for 8.5 digit front end
« Reply #12 on: September 21, 2023, 11:52:03 am »
Here is the nstrument I made

High impedance frontend I used opa1289 and is in a metal case heat to 40 deg. C In place of relays I used optoflash TLP240.
3458 is an old 35 years (or more ?) old instrument full with discrete components. Now there are much better IC than ampifiers with discrete components.

Am I confused, or what? There are 8 digits on display... That would make it 7.5 digit meter, or am I wrong.?

#### Ole

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##### Re: Design considerations for 8.5 digit front end
« Reply #13 on: September 21, 2023, 12:03:28 pm »
Am I confused, or what? There are 8 digits on display... That would make it 7.5 digit meter, or am I wrong.?

The Range shown on the thumbnail is the 10V range, which is resolved with 7 digits behind the period. Assuming the range goes only to 9.9999999V it would still be a 8 digit display (as there are 8 fully variable digits).
Assuming the range can go up to 12V it would mean that there are 8 fully variable digits and one that can either be a 0 or a 1.
The first digit, the one that can only be a 0 or a 1, is hidden because it is not needed.

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Yes, you. Have an awesome day!

#### David Hess

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##### Re: Design considerations for 8.5 digit front end
« Reply #14 on: September 21, 2023, 01:34:13 pm »
The CMRR could be a liniting factor for the linearity.  With typ. 130 dB this not enough to guarantee better than 0.3 ppm INL. However chances are that much of the CMRR is still linear - so from this side it can be just acceptable, though not great, when hunting for possible sources of INL.

It is not really practical because of all of the analog switches needed, however Intersil solved the CMRR problem by executing the automatic zero function at the common mode input voltage, so that the automatic zero also corrected the common mode rejection.  Siliconix did not and their designs suffered for it.

Quote
For a buffer it is relatively simple to use a bootstrapped supply and this way essentially eliminate the effect of the CMRR.

I would consider bootstrapping the input buffer for another reason also; it would allow for a gigaohm+ input resistance exceeding 15 volts.  Most designs are limited to 2 volts or maybe 10 volts, but 15+ volts is very handy and something I am looking for in my next multimeter purchase.

Quote
An alternative buffer would be a Zero drift OP-amp like LTC2057 or OPA189. These usually have very good CMRR and gain, at lest for DC and low frequencies.

I think using a zero drift operational amplifier as a buffer would be a mistake because the input bias current and input current noise will interact with the series input protection (and source impedance) to add offset and noise.

The offset voltage of 80uV I should be perfectly fine. but the tempco can possibly be better. The typical is actually +-0.2uV/C with a maximum of 1.2uV/c

The input offset voltage drift specification is tough.  Even my new favorite low input bias current precision part, the OPA140, has a maximum input offset drift of 1 uV/C, which is great for a JFET input but an order of magnitude worse than the best bipolar inputs.  Chopper parts solve this but have worse problems with high impedance inputs.

That means grading the input buffer for low drift, correcting the drift somehow, or correcting the drift with automatic zero which is how most designs handle it.  One place I worked did the first one with a test chamber and marked the top of the parts with the drift.

#### dietert1

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##### Re: Design considerations for 8.5 digit front end
« Reply #15 on: September 21, 2023, 03:54:23 pm »
One needs to do something about low frequency noise. If one does it with autozero e.g. 1 PLC alternating between unknown and null input, half of the input signal gets lost. If one does it using a chopper stabilized opamp, it supports continuous integration, yet the chopper frequency will probably be higher with more noise generated at the input.

I agree with K-Zoltan that we should try and use integrated circuits where possible. There is a large choice of chopper opamps, some with less input current than the OPA189. In the bootstrap scheme one can also try and compensate the input current to maybe reduce it from 100 pA to 10 pA. As i plan to run the meter inside an oven at constant temperature, there is a good chance to make the compensation work. Anyway, 100 pA at 10 V gives 100 GOhm and with compensation one can expect 1 TOhm.

Regards, Dieter

#### Kleinstein

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##### Re: Design considerations for 8.5 digit front end
« Reply #16 on: September 21, 2023, 04:55:07 pm »
There is usually no need to go for the super low noise AZ amplifiers. The input noise of the HP3458 is more like 50 nV/sqtz(Hz) assuming 100% integration. So one can get away with lower input current AZ amplifiers like AD8628, LMP2011 or MCP6V76 and still get a comparable or slightly better noise. These have less input bias and less current noise. However the lower bias types often only comes with a limited supply voltage (e.g. 6 V max) and thus kind of need bootstrapping the supply already for a 10 V range.  With suitable filtering at the input one can isolate it from variations in the input impedance reasonably well.
The very low bias types (max4238, ICL7650, LTC2055) are a bit on the high side with the noise.

Chances are one needs some luck with the amplifier bias and switch leakage to get at least partial compensation or good individual units.

The input resistance is more like a differential thing. So one has some input bias and than an input resistance describing how the input current changes with the voltage. So I would not call voltage range divided by input bias the input resistance.  One usually needs some filtering anyway to keep EMI out and as part of the ESD protection.

In my DMM circuit I have an AD8628 with a BS supply for the main input that works OK.
In my case I got some 6 pA bias and some 300-400 Gohm of differential input resistance with a large part of this likely from PCB leakage (changed with cleaning). For bias I consider this a lucky pick of the amplifiers and switches. Actual values can scatter even with the same types used. I have an MCP6V76 with a high voltage divider and this also works OK.

The choice of Az amplifier (e.g. Keithley 2000 / 2002, Datron 1271/1281 like) vs AZ switching (e.g. HP 3458 and most other HP) is between frequent chopping with small spikes in the AZ amplifier versus relatively low frequency (e.g. 2.5-25 Hz) but usually larger switching peaks. Both have there pros and cons.

#### Echo88

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##### Re: Design considerations for 8.5 digit front end
« Reply #17 on: September 21, 2023, 05:40:17 pm »
I assume the AZ-cycle time can be reduced pretty much when the first amplifier/buffer stage in the AFE (discret or not) can be kept at a stable temperature, like in this paper: https://arxiv.org/pdf/1708.06311.pdf
After the buffer youre free to throw AZ-OPs at it.

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#### Kleinstein

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##### Re: Design considerations for 8.5 digit front end
« Reply #18 on: September 21, 2023, 06:17:40 pm »
The range for the auto zero cycle is usually pretty small:  less than 1 PLC is often problematic as mains hum can cause problems. Also many switching spikes are not that desirable. Without Az amplifier one usually wants to suppress much of the 1/f noise and much more than 1 slow reading (e.g. 100 PLC) is not practical. Often 10 PLC is used as a upper limit. So the main choices are some 1 to 10 PLC for the AZ cycle length, rarely more.

When there is a low drift (in generalle some kind of AZ amplifier) input buffer the AZ cycle behind it can often be 1 PLC, unless the ADC wants more (especially some older multi-slope ADCs). The JFET amplifier with stablilized temperature is more like an oddity and may still have 1/f noise or slow drift (e.g. from stress or aging) and may thus still want some AZ switching in front - maybe just with a rather slow cycle.

The main configurations to look at are:
1) AZ switching close to the input and than non AZ amplifiers (or just 1 amplifier) all the way to the ADC  (e.g. HP DMMs).
This often needs some pre-charge cicuit to limit the swiching spike.
2) an AZ buffer at the input and than AZ switching after that followed by a non AZ amplifier (e.g. Keithley 2000 / 2002)
3) an AZ amplifier at the front and than AZ switching and a buffer or 2nd amplifier stage at the ADC input (e.g.  my DMM circuit, Keithey 2182)
4) an AZ amplifier at the front and than a low drift ADC (e.g. Datron 1281, likely SDM3065, Solartron 7081) with only rare Az switching - if at all
Many of the SD-ADC chips have pretty low dirft and may allow this configuration

One may mix the cases, and not all input paths must look the same - though with most meters it is.
The case with an non AZ buffer at the input is more a thing for electrometers, not so much for a high resolution DMM.

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#### macaba

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##### Re: Design considerations for 8.5 digit front end
« Reply #19 on: September 22, 2023, 09:34:00 am »
If hyper-focused on a small part of the design, an integrated zero-drift amplifier would appear to make sense, however when considering the whole design, integrated zero-drift amplifiers are not suitable for the input amplifier on a 8.5d voltmeter design (and HP agreed). Designs that use zero-drift amplifier on the input are more like "low source impedance digitiser" rather than "voltmeter" (HPM7177 being a good example where it is continuously monitoring LHC magnets in a highly stable temperature environment).

(I'm going to use the term "chopper frequency" going forward, but this could easily refer to the frequency of non-chopper zero-drift mechanisms like autozero, correlated double sampling, and higher order nested zero-drift schemes, as true chopper topology amplifiers are rarely used anymore)

1. IC AZ has no control over the charge injection spikes. With a discrete design, it's easier to have precharge phases. Furthermore, because the chopper frequency of a discrete implementation tends to be lower (1NPLC for example), it's easier to observe the charge injection spikes during development.
2. IC AZ has high input current noise. Good luck measuring high value resistors. Current noise is usually proportional to the chopper frequency. Lower frequency = lower current noise. (therefore you can see the advantage of 1NPLC vs >100kHz...)
3. So the drift of one amplifier is solved... what about the whole signal path? ADCs have 1/f noise too. Even the AD4630 which claims "1/f noise is canceled internally" on the datasheet. So now there are multiple points of the signal chain doing their own zero-drift mechanisms which is a recipe for problems. IMO it's better to do chopping on the whole signal path as one, at a frequency you control.
4. There was mention of "half the input signal gets lost" - there are topologies that avoid this, though I don't think it's a big concern for DMM inputs to have a auto-zero scheme that halves the sample rate. For a modern DMM that only has an IC ADC (no integrating ADC), I think it's sensible to have 2 distinct modes of operation - "NPLC mode" where all the auto-zero/auto-cal mechanisms are enabled, and "Digitiser mode" where they are disabled (perhaps with a single correction at the point where you change modes, and automatically thereafter at any point where the internal DMM temperature has changed 0.1 degC, with an optional user override of this behavior when you absolutely must have a contiguous stream of samples, as in the case of HPM7177).
5. Once you have a discrete zero-drift mechanism in place, other advantages come in too - that analog switch that does the switching between "Input" and "0V" can have another input to a mux that allows the selection of other voltages (like REF+), ideal for self-calibration.
6. JFET front end (whether discrete or OPA140) already has single-digit pA input bias current. Far less compensation required, if any.
« Last Edit: September 22, 2023, 09:39:15 am by macaba »

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#### tszaboo

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##### Re: Design considerations for 8.5 digit front end
« Reply #20 on: September 22, 2023, 09:47:51 am »
Context: I am designing an 8.5 digit ADC with surrounding voltmeter with a novel self-calibration technique as part of my final year project. (about which i will share but not until the project is finished).

As part of the ADC I need an input buffer and believe an ADA4625-1 unity gain buffer should be sufficient. Mostly because this is more about the ADC and getting a +-10V voltage digitized as accurately and precisely as possible. The following project would be about getting other functions such as I and R along with various voltage ranges but for now the ADC is the priority.

does anyone have any suggestions on the input buffer or should it be more than enough for the project at the moment?  Is there anything Im missing? or should this suffice?
My suggestion is to select another final year project. You will only have time to run 1 maybe 2 PCB iterations. There are a lot of pitfalls in designing a 8.5 digit AFE. University teachers don't grade or appreciate the difficulty of the problem, they grade the paper that you submitted. You need to worry about latex, sources, reading publications, and wrestle with MS Word. Not chasing nanovolts. You simply don't have time to do it right anyway, and you are expected to spend most of your effort on the paper, not the circuit
It's an interesting project, but not if you are graded, and not with deadlines. Maybe drop it to 6.5 digit, if you made this for yourself.

#### iMo

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##### Re: Design considerations for 8.5 digit front end
« Reply #21 on: September 22, 2023, 10:21:02 am »
As I wrote earlier - would be great to develop a simple AFE with +/- 12V input range only, as a Proof of Concept.

Targeting complex designs with U/I/R capabilities in multiple ranges means man-years of work with many iterations, with a result nobody would be able to reproduce (for many reasons) or characterize.

Thus a bootstrapped OPA140 (for example), with some switch for calibration/zero, then a 1:10 divider with the final buffer to feed the ADC chip low impedance with a differential +/-1.2V.

I think having such a simple AFE with rock solid performance (which would be fully in pair with any single chip ADC we have got handy, like the ADS1263, AD7177, LTC2500-32, AD4630, etc) would be a great practical achievement here. Also for sahko's final year paper, imho..

« Last Edit: September 22, 2023, 10:37:37 am by iMo »

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#### Kleinstein

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##### Re: Design considerations for 8.5 digit front end
« Reply #22 on: September 22, 2023, 11:05:24 am »
The integrated AZ OP amps are not that bad:
They can use quite some extra effort (more elaborated than the simple precharge) and on chip matching can be quite good with little parasitic capacitance. Another point is that the AZ amplifier are usually chopper stabilized and thus switching with very low voltage at the switches.  So the individual switching spike from the AZ amplifier are considerably smaller than the spikes from switching with the full swing like in the HP meters AZ switching cycle.  Another point is that AZ switching usually uses a short break to let the spike decay - this can be good, if the decay is fast and also bad if the signal source is high impedance / capacitive and stretches the spike to extend beyound the dead time. With the dead time filtering the spike can be tricky as this is just the kind of source that stretches the pulse.

There are meters with discrete build chopper stabilized amplifiers too (datron 1281, Solartron 7081), that can use a moderately low chopper frequency. The reduction in the current noise is for the most part only with the square root of the chopper frequency. It is the input bias that about scales like the frequency.

#### dietert1

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##### Re: Design considerations for 8.5 digit front end
« Reply #23 on: September 22, 2023, 11:29:18 am »
If hyper-focused on a small part of the design, an integrated zero-drift amplifier would appear to make sense, however when considering the whole design, integrated zero-drift amplifiers are not suitable for the input amplifier on a 8.5d voltmeter design...
Back to reality: The Prema 6048 was an 8.5 meter design using a chopper input amplifier instead of autozero and it is on par with the best HPAK meters, once you have the multiplexer, so one can recalibrate null without touching cables. Look for recent statements of RAX. My own experience is similar, except i want an ovenized/humidity controlled meter. At the same time one can try other improvements.

Regards, Dieter

#### David Hess

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##### Re: Design considerations for 8.5 digit front end
« Reply #24 on: September 22, 2023, 11:57:21 am »
3. So the drift of one amplifier is solved... what about the whole signal path? ADCs have 1/f noise too. Even the AD4630 which claims "1/f noise is canceled internally" on the datasheet. So now there are multiple points of the signal chain doing their own zero-drift mechanisms which is a recipe for problems. IMO it's better to do chopping on the whole signal path as one, at a frequency you control.

Does anybody apply chopper stabilization to the whole signal path?

The high impedance buffer at the input is the largest contributor of noise before the ADC, and delta-sigma ADCs, at least the instrumentation ones, do cancel their own 1/f noise.  They even have the same input offset and input offset drift as chopper stabilized amplifiers built on the same process. (1)

Hmm, since the input divider effectively raises the input referred noise of the high impedance buffer, do electrometer style inputs where the input buffer is bootstrapped display lower noise because their divider is after the high impedance buffer?  This could be another reason to bootstrap the high impedance buffer.  I have not noticed that electrometers have lower noise than multimeters, but I have never had both to compare at the same time.

(1) Some delta-sigma converters intended for transducer measurement have a mode where they chop the excitation output with their inputs so they do chop the entire signal conditioning chain, and some multimeters do the same thing in 4-wire ohms mode.

Smf