DIY high resolution multi-slope converter

[wildhog]

Thanks for the quick response.  Do you have an idea as to how slow you do you run-up cycles before DA begins to kill your linearity?  Also, to a first order at least, running the integrator up, then down below ground, then back up to ground should cancel out any DA effects.  If DA is modeled as a parallel RC then this holds.  Have you tried this and do you have a feel for how well it works?  I realize that you want to run the clock fast for a quick conversion, but for linearity there are some advantages of slowing it down (fewer transitions).  The big disadvantage, however, is DA and it's difficult to know the optimal run-up frequency for best linearity. 

Thanks,
Dave

[Kleinstein]

The modulation speed is a compromise: DA related errors and to get a fast rundown a fast modulation is preferred. To keep the effects of charge injection, timing jitter and settling of the integrator small, slow modulation is better. Currently my favorite would be around 60 kHz with 2 tests per period.

For the DA related error, the measurements of the difference of the 2 modes are a good estimate. So with the currently best capacitor I have (TDK NP0) and some 27 kHz modulation (with a single comparator test) the expected DA related INL error is at some 0.2 ppm of the full scale. The error is expected to go down with about the modulation frequency. There is a slight chance that some of the DA error can be compensated by measuring the average integrator voltage - ideally averaged in a way that resembles the DA time constants.  Another point would be a little more waiting in the rundown to reduce the fast DA part.

The integrator control is already going negative and positive in a way to keep the average voltage low. Here it helps a little to read the comparator  early. However the effect is limited. There is a way to use a mode with 2 comparator checks per period to get effectively twice the response - however this requires good symmetry. I had problems with this, but the current program seems to work now. However I still get slightly higher ( +30%) noise with faster modulation (125 kHz). For some reason there seem to be some odd effects of delays and the exact synchronization between the ADC and modulation. A little like that the ADC clock can effect the PWM signal generation. In some cases there is a periodic background that adds to the "noise". So a high performance version may need an extra sync stage (e.g. 74AC74) between the µC and the switches.

Attached is a graph of the average voltage (units  about 7 mV with a zero at 140) in the integrator as a function of input voltage. Curve is point symmetric about 300 mV and should about reflect the effect of the slow DA. So the linear part is only an effect on gain. The two curves are for slightly different run-up versions. The point's off the curves are usually not noise, but part of resonance like structures that is not fully visible with a limited number of points.

The other graph shown the difference between run-up speeds (27 and 81 kHz). The range is the center part of the resonant like structure near 300 mV. The 2 curves are for a poor and a good NP0 capacitor and same software version.

[Kleinstein]

I did some more test with faster run-up, especially going down to 104 clock cycles for the loop. This is the same length as the UART master clock for 9600 baud. In this case there is a strong dependence on the exact delays and phase relative to the UART clock. Depending on the exact delays there is some beat signal that can be quite strong, up to some 20 µV peak and some 6 µV RMS. With the right delay there is relatively low background.  The effect of the phase relative to the ADC clock is also visible and can be controlled with synchronizing the ADC clock - however this does not work well with the UART if the UART is used to receive commands at any time.

So I tried the synchronization of the control signals with flip flops  (currently 74HC74 as a dead bug bodge). The positive thing is that the clock phase of the external AVR clock is about right to use just xx74 flip flops. With the flip flops the dependence on phase between UART clock and run-up no longer has a visible effect. The noise level is about as good as it was before in the best delay case. Still the noise level is somewhat higher (1.2 µV)  than it was with slower modulation (0.85 µV). The extra noise seems to be mainly white noise, as the difference gets smaller with longer integration, where 1/f noise dominates.

[jbb]

I don’t know if it’s a problem to worry about, but you can probably avoid reception of UART characters during the critical parts of the ADC operation by using a GPIO to as an old -fashioned Clear To Send (CTS) line and configure your ‘master’ (PC serial port?) into 4 wire mode (with RTS and CTS). The ADC uC can then simply say ‘not now, I’m busy,’ and the master can handle that in the UART hardware.

Given that you’re now considering additional logic resources, I wonder if a CPLD might be helpful.

On second thought, CPLDs don’t have ADCs and comparators. Maybe a PSoC, then? They have some special configurable logic built in which could be quite helpful

[schmitt trigger]

I remembered an interesting part which could be useful for the input resistor: a SMT chip ceramic thermal jumper. 

Many thanks for mentioning this very useful component.
Earlier this year I had a project with thermal issues which had to be solved rather crudely.

This component would have yielded a very elegant solution.

[Kleinstein]

I don’t know if it’s a problem to worry about, but you can probably avoid reception of UART characters during the critical parts of the ADC operation by using a GPIO to as an old -fashioned Clear To Send (CTS) line and configure your ‘master’ (PC serial port?) into 4 wire mode (with RTS and CTS). The ADC uC can then simply say ‘not now, I’m busy,’ and the master can handle that in the UART hardware.

Given that you’re now considering additional logic resources, I wonder if a CPLD might be helpful.

On second thought, CPLDs don’t have ADCs and comparators. Maybe a PSoC, then? They have some special configurable logic built in which could be quite helpful

A PSOc and  likely also a CPLD / FPGA will also have some coupling from other parts to the exact timing of the control outputs. It only takes a few ps of shift for some 500 transition to cause a 20 µV error. So the external flip-flop is the normal way to avoid this: the HP34401 and many other multi-slope ADCs use such an external flip-flop. It is only needed for the 2 control signals, so only one 74AC74 or similar.

The coupling only gets really bad with special loop lengths (like 104 or 128 cycles) that gets a frequency in sync with ADC clock or UART. This way many transitions can be effected.  Even than, with a careful timing one can avoid larger effects, if the conversions start with a well defined phase of the interfering signal. With a different loop length the effect will be smaller but harder to totally avoid.

The critical run-up phase is active most of the time and currently about 70% of the time data are send - so not so practical to turn off the UART for a longer time. One may however be able to do a sync by turning it off for a short time and on again just before the run-up.     So it is a good idea. This way the UART always starts with the same phase and it is thus relatively easy to find a good timing. The data send can tell the PC when sending is OK. Similar synchronization works with the µC internal ADC - this already works.

The comparator and ADC in the µC don't have to be high performance so a CPLD + external comparator and ADC (e.g. 10-12 Bit) are possible.  I just know the AVRs much better than CPLDs. The project started as a simple low cost µC based version and later turned high performance, without getting too expensive  (BOM costs at some $40-50 including the LM399 reference). There still it the option to use relatively cheap resistors and OPs and still get good (e.g. 6.5 digit) performance.

[wildhog]

When you use the ADC to calculate the remaining charge on the capacitor, the absolute value of the RC time constant becomes an error term.  Have you tried doing a two-point measurement to calculate the RC time constant on the fly to remove it as a an error source?

Also, do you have a sense of what the limitations are of this multi-slope adc configuration?  It looks like you have between 6.5 and 7.5 digits.  Do you think 8.5 is possible with this topology?

[wildhog]

One more question:  the remainder after the run up/run down is measured with an ADC while the conversion has stopped.  But during this time, the output is still changing due to the leakage (the fast switches have significant leakage) at the integrator node.  The output voltage is therefore changing during the ADC measurement.  I'm not sure if the ADC is a delta-sigma (in which case this would be averaged) or a SAR (in which case the output would be sampled at some time) but in either case, I'm surprised that this error is able to be so completely calibrated out.  Sampling at a very precise time would make the most sense for calibrating out an It/C error but would likely be noisy as the full spectrum noise of IC4 is sampled.  Averaging (delta sigma ADC) would reduce the noise of IC4 (as you mentioned somewhere above) but the start and stop times of the ADC would have to be precise and repeatable.

The leakage on the fast switches that you mentioned is 1uA max and you have three of them.  3uA is a lot of leakage and produces a 1mV/us error at the output of the integrator (assuming a 1nF integrating capacitor).  This is a large error to calibrate.  The noise of the leakage current is not specified but surely must affect the total ADC noise. 

Thanks,
Dave

[Kleinstein]

There are 3 main parameters to look at for the ADC: noise, linearity and gain stability.

The noise data I showed are for the 1 PLC auto zero case, so the difference between 2 conversions at 1 PLC. At some 1 µV RMS and +-10 V full scale this is about 7 digit resolution. So it if 7 digits at 1 PLC.  With averaging (e.g. 100 x) the noise is down in the 8 digit range. The noise level is already lower than some 8.5 digit meters (e.g. Keithley2002, ADT6581, Solartron 8081, Fluke8508).
The noise level depends on the switching frequency used in run-up. Slow modulation gives lowest noise (0.85 µV with the current resistors), but also more INL error from DA. So the speed here is a compromise between INL and noise.
Most of the noise sources are known. A convenient way to note the noise is as a equivalent (series) resistor - 1 nV/Sqrt(Hz) corresponds to the noise of 60 Ohms, going up like the square. So the "resistance" values can be just added for different not correlated sources. Calculated back to a single (no AZ) conversion the noise is equivalent to some 600 KOhms (some 100 nV/sqrt(Hz)). Of this the integrator resistors Johnson noise is at 100 K,  the resistor excess noise is at about 100-200K, the critical OP at the integrator about 50 K, the amplification of the references some 20-50 K, the input buffer some 5 K, The final charge reading from the µC internal ADC some 20 K and the switching related effects should correspond to some 200-300K (more or less with a different speed).  The main point's for possible improvements are the resistor excess noise and the switching related part.

For the INL I see mainly 3 main sources: the dielectric absorption, thermal effects in the resistors and settling of the integrator. I think I now understand the DA effect and get this smaller than 0.05 ppm of FS with a reasonable modulation speed. For the integrator settling part his should be in a first approximation some slightly different slope for the positive and negative side. I have to do some more test on this (force the error to be large and visible with very short pulses and high frequency). So far this effect does not look to bad - chances are it's negligible. The thermal effect is question of the resistors - so far it looks good with the NOMCA array. 

Checking the linearity is rather difficult, so far I am quite confident the INL is  < 1 ppmFS and likely better, in the 0.2 ppm range, but I have no way to measure. I can kind of measure the DA effect though and at least the slow part of the thermal effects can also be tested.

With the resistor arrays the gain stability also got quite good, so no real problem there.

So 8.5 digit performance is possible (essentially there  ) in this topology.
The critical parts are the switches and resistors at the integrator input. Of cause it also needs a better reference. It may still make sense to have a very good ADC with an LM399 as this could allow for auto cal in a low cost solution.

The ADC in the µC is SAR type, but relatively slow. The amplifier with MCP6002 is also limiting the bandwidth. So the ADC bandwidth is limited does not see a lot of higher frequency noise. When the final charge is measured the output is not changing much (barely visible in consecutive conversions) - the main reason is still the residual DA and not switch leakage or OP bias.
The xx4053 switches are not tested very much at the manufacturer. So the limiting values are high, but the typical leakage is much better. So even with the specs at 1 µA max, I see a net leakage current in the 5-10 pA range for the 3 switches.  Even if the leakage current would be high, a constant values is suppressed and would act as part of the reference currents. The main point would be that the DA measurement mode would not work that well anymore. If at all leakage would be a problem for the input path. Here it helps that the switch in using bath halfs of the SPDT switch: one sends the input current to ground and thus keeps the voltage low, the other isolates the integrator.
As a possible alternative there could still be the DG4053 switch - lower leakage specs and not too slow.

[iMo]

..So I tried the synchronization of the control signals with flip flops  (currently 74HC74 as a dead bug bodge). The positive thing is that the clock phase of the external AVR clock is about right to use just xx74 flip flops. .

Could you indicate the 7474 wiring, please (just indicate the two signals you synced, 74's clock is the external 16MHz)?
It also means the atmega with its internal xtal oscillator may not work straight with those 7474 synchronizers. So rather go with external canned oscillator as default.
Are you still working with the original schematics, parts and code (except the nomca array and the input buffer)?

[jaromir]

so far I am quite confident the INL is  < 1 ppmFS and likely better, in the 0.2 ppm range, but I have no way to measure.

Not trying to be snarky, but I still remember how confident I was about my first multislope ADC design, up to the moment I started real measurements 

[iMo]

A pity the effort with the pcb bite the dust, I think $50 7digits +/-12V input AD converter would be an interesting playground for experimenters (and I bet a lot of them have got 3458A to provide some measurements).

[Kleinstein]

The extra synchronization is with the 16 MHz clock from a canned oscillator, the signal  from the µC to D inputs and Q outputs to the 4053. With careful timing and not using loop length with multiple of 64 or 104 one could still get away without the flip-flop. A result from this test is that favorable timing cases were about as good as the version with the FF - so the FF is not absolutely needed but it can make things simpler.

A pity the effort with the pcb bite the dust, I think $50 7digits +/-12V input AD converter would be an interesting playground for experimenters (and I bet a lot of them have got 3458A to provide some measurements).

The PCB has some bodges, but except for the extra HC74 this is not too bad.  One of the NOMCA arrays is already includes in the PCB layout (though not very good - a 20 K version and using 2 of the resistors in series is probably better (less excess noise)).
It would likely still need an update to the PCB to have 2 (maybe 3) x NOMCA resistors, an updated buffer, a few more SMD parts, include the bodges and a connector for an optional external reference.

so far I am quite confident the INL is  < 1 ppmFS and likely better, in the 0.2 ppm range, but I have no way to measure.

Not trying to be snarky, but I still remember how confident I was about my first multislope ADC design, up to the moment I started real measurements 

I was at that point of high confidence too, before testing the PCB version to find out that the version on the breadboard was better performance   .  I now have quite some tests with the limited possibility at hand, and the results for the "final" versions looked good:
2 speed run-up versions are withing 0.2 ppm even a low speed. The faster version should be something like 4 times better with DA.
The turn over test revealed some problems with the buffer, that the extra bias mainly solved (though an extra 3rd OP may be better). After that there was very little turn over error - I have to repeat that test with the new version. For the thermal effects good stability gives me good hope there.

One of the next steps would be sending a board to someone with better instruments to do some more INL tests.

[Rerouter]

sorry IMO, life jumps up and pulls you away from your hobbies at random, It is why I released all the design files, as I felt I would get stuck unable to touch it for a while. (being 1200km away from my desktop is not helping things)

[MiDi]

so far I am quite confident the INL is  < 1 ppmFS and likely better, in the 0.2 ppm range, but I have no way to measure.

Does this mean that you are searching for someone that has the equipment and would do the measurements or borrow the equipment to you?

Edit: Question is a bit outdated due to last post before this post was sended.

[jaromir]

.
The turn over test revealed some problems with the buffer, that the extra bias mainly solved (though an extra 3rd OP may be better).

What is the function of third opamp in the buffer?

[iMo]

The PCB has some bodges, but except for the extra HC74 this is not too bad.  One of the NOMCA arrays is already includes in the PCB layout (though not very good - a 20 K version and using 2 of the resistors in series is probably better (less excess noise)).
It would likely still need an update to the PCB to have 2 (maybe 3) x NOMCA resistors, an updated buffer, a few more SMD parts, include the bodges and a connector for an optional external reference.

Rerouter spent an effort with pcb design, and you are going to redo your pcb as well.

What about

a) to consolidate the ADC design (ie. a "final version of the schematics"),

b) then be focused at a more "thru-hole" lower density board, with more space on it, which allows easy routing and good grounding and decoupling, for example a 2 layers pcb 100x100mm (or even 100x160mm) of size (with four 3.2mm holes at the corners), without the power supply on it (ie. it means only with +15V/gnd1, -15V/gnd2 and 5V/gnd3 connectors), it also removes a significant heat source off the ADC board. You may need to make some milling as well (around the LM399, and/or around temperature/leakage sensitive parts). You need space.

A floating 3 voltages power supply pcb could be designed easily by anybody, while the AD board requires pretty experienced designer (especially when "7+ digits" is claimed).

[Kleinstein]

.
The turn over test revealed some problems with the buffer, that the extra bias mainly solved (though an extra 3rd OP may be better).

What is the function of third opamp in the buffer?

The third OP in the bootstrapped buffer would just buffer the bootstrapped OP, inside the FB loop and with the normal +-15 V supply. This same configuration is used by CERN in there buffer for a high end ADC. This 3 rd OP would keep the load to the bootstrapped supply constant and suppress the output stage cross over distortion a had seen in my first try without the bias. It should be even a little better than just the bias.
There would be still the alternative to use only an OPA189 Az OP: it is fast and "MUX friendly" designed. So it should work behind the DG408. In this case the OPA189 would be used because of high gain and CMRR and thus good linearity, not because of the low offset.
With the old buffer I still have quite some current spikes on switching - not sure where they come from.

For me the old PCB design is still good enough. For just 2 or 3 units the bodges are OK - but I would not order more of the same. The current board is 80x100 mm with still some space in between, including space for large (e.g. wire wound) resistors. Some of the chips are THT, but some of the planed OPs (e.g. OPA145,  OPA189, OPA172, ADA4077 as a possible upgrade to the OP07) are not available in THT or much more expensive. The critical switch as THT allows easy changing (in case an LV4053 turns out to be leaky) - however the DG4053 is SMD only. The mounting holes are not at all in the corners because of the Opto couplers (isolation).

For a new layout the main open question is which resistor arrays to use. I have 2 x NOMCA (10K + 50 K) with good TC matching, but it looks like noticeable excess noise. The next step up could be using 2 resistor arrays for the integrator and thus 4 resistors in series each. This should reduce the excess noise (by some 30%) and also reduce the heating effect as the power is spread to 2 chips. The next better solution would be an LT5400 for the reference amplification part. For the integrator this is a little tricky: 100 K is rather on the high side and 10 K is too low for a +- 10 V range. So a really good solution would need more like 3 x 10 K in series and thus 3 x LT5400 for the integrator which starts to get expensive (at $8 each).  2 x 100 K in parallel would be an option too - with the advantage of possibly populating only one. As low cost alternative to the LT5400 (compatible footprint) there are MORN arrays - however with possibly quite some excess noise.

I don't have a problem with the regulators on the board. They are away from critical parts and make the use easier. If really not wanted there is still the option not to populate that part.

[jaromir]

The third OP in the bootstrapped buffer would just buffer the bootstrapped OP, inside the FB loop and with the normal +-15 V supply. This same configuration is used by CERN in there buffer for a high end ADC.

Oh, that makes sense, thanks.
I read a few documents about DS22 and DS24 CERN ADC designs, but I don't remember bootstrapped buffer. Could you, please, share or point me to appropriate document?

[Kleinstein]

The third OP in the bootstrapped buffer would just buffer the bootstrapped OP, inside the FB loop and with the normal +-15 V supply. This same configuration is used by CERN in there buffer for a high end ADC.

Oh, that makes sense, thanks.
I read a few documents about DS22 and DS24 CERN ADC designs, but I don't remember bootstrapped buffer. Could you, please, share or point me to appropriate document?

I thinks I saw this for the Cern ADC too, but could not find it. I found another reference however:
https://www.semanticscholar.org/paper/Comparison-of-Two-Buffers-for-Impedance-Metrology-Kampik-Tokarski/40f8df3e21108a3360cd71deaf188ae748b0b559

[iMo]

2 x 100 K in parallel would be an option too - with the advantage of possibly populating only one. As low cost alternative to the LT5400 (compatible footprint) there are MORN arrays - however with possibly quite some excess noise.

Or 2x LT5400/100k with 3x 100k_A||100k_B..

PS: CERN's latest high-ender is the HPM7177 with the $15 AD7177-2 inside, afaik

[dietert1]

Once more about dielectric absorption: Meanwhile i received some ot those russian Teflon capacitors and compared them to the original capacitor of a HP 3456A. The Teflon capacitor is better, but the difference is about 20 % only, so the measurements in that other thread i linked before appear strange now. Some Styroflex capacitors recently ordered from Farnell were in between.

An intricate measurement that requires some work to get correct results. After keeping the capacitor at 15 V for about 100 msec it gets discharged for about 5 msec. There is a 100x amplifier in front of the scope, so the effect is about 3 to 5 mV, with error (drift) less than 20 uV. One thing that surprised me: The absorbed charge shows up slowly like a small current. Only after some 30 to 50 msec that current will slowly diminish when charge approaches its asymptotic total.

For all capacitors i tested the effect depends a lot on capacitor temperature. Even some minutes after soldering capacitor leads the Teflon capacitor appeared worse than the original capacitor. Bob Pease mentioned temperature in his application notes about "capacitor soakage", too.

Regards, Dieter

[jaromir]

I obtained similar results with my measurement - https://www.eevblog.com/forum/projects/multislope-design/msg2117578/#msg2117578
Russian Ebay PTFE were best, followed by polystyrene, PP and ceramic (probably NP0). MLCC were only marginally less horrible than electrolytics.

[dietert1]

Can you repeat your measurement for the Teflon capacitor without charging it before - kind of a NULL check? I suspect you may have significant negative drift in your circuit. Otherwise i have difficulties since your Teflon capacitor looks like mine. In my circuit the effective amplifier input bias current was 23 pA and i compensated it to less than 1 pA using a 10 GOhm resistor driven by a 0,23 V offset.

Regards, Dieter

[jaromir]

I tried to guesstimate whether bias current is of any significance by "measuring DA" of 500 Megaohm resistor, see attachment. Significant input current would cause voltage drop on the resistor.