DIY high resolution multi-slope converter

[SilverSolder]

[...] One thing that surprised me: The absorbed charge shows up slowly like a small current. Only after some 30 to 50 msec that current will slowly diminish when charge approaches its asymptotic total. [...]

Is that not consistent with absorption being modeled as another capacitor/resistor series pair in parallel with the "real" capacitor?

[Kleinstein]

It is normal that the hidden charge comes back slowly. Usually there are relaxation effects on different time scales, from very fast (sub ns) to very slow (hours).  Especially the classical relaxation in the volume is expected to be highly temperature dependent, like thermal activation and thus exponential change in the time scale.  The main effect expected is that the time scale gets faster, while the absolute size would not change much. There can be an observed change in magnitude as the test usually is sensitive to a certain time window (e.g. 5 ms to 100 ms here,  some 100 µs to 20 ms for the MS-ADC and some 100-1000 seconds for the standard DA numbers quoted in data-sheets).
Effects related to surface charges may be less temperature dependent. These are often the really slow processes.

Due to the different time scales involved the simple capacitor resistor model is not sufficient. It usually takes several RC elements in parallel.
The leveling off to long times could be for different reasons: fewer really slow processes, the length of the charging phase - so very slow processes are not charged up very much and also leakage current that can take over and discharge the capacitor again.

To check the effect of bias current, one could do the test with positive and negative charging before the recovery. The difference should be mainly the DA and the sum (with sign) should be mainly amplifier bias.

For the NP0 capacitors I found quite some difference between models. My currently best one was about 1/10 the DA of the worst. Good candidates to test would be low loss RF capacitors. I have not checked those.
For the PP film caps there can also be difference, as the purity of the PP material can be different. I have also seen different DA values for identical looking older PS caps.

So the Teflon caps also don't look that good. Some 3-5 mV recovery from 15 V is more than I found for the good NP0 (TDK). The time scales are a bit different so take the comparison with a grain of salt.

[Echo88]

Which teflon-caps did you test Kleinstein? Those with epoxy on the tube-ends or those who are pressed as a coilpackage into the aluminium-tube, which is then crimped on the edges?

[Kleinstein]

I did not test any Teflon caps. I was only comparing other people's results given (Dietert1 with 3-5 mV after 15 V (some 0.04%) and graph from the Bob Pease article (some 0.004% at 5 ms discharge). The Teflon cap from Dietert1 thus has about 10 times the DA. So a Teflon cap alone does not guarantee low DA.

Especially the slow processes have a lot to do with surface charges, possible air inclusions or similar.

[dietert1]

I tested both the sealed type with hard electrodes "K72P-6 500V" and the aluminum tube with wires "FT-1 200V", with very similar results. All capacitors were 3.9 nF, same as the capacitor of the HP 3456A ADC integrator.
We have two test reports here in the forum where others measured Teflon capacitors with almost no dielectric absorption effect at all. For me Teflon capacitors looked better than other types of capacitors but not completely different. Don't understand that yet.

Regards, Dieter

[Kleinstein]

There are 2 causes of DA in capacitors: one is the classical relaxation in the volume dielectric. This is usually relatively fast, mainly faster than ms.
The other part is surface charges, like in areas with air inclusions or oil where is surface of the dielectric is free and charge can build up via weak surface leakage.  This second type is often slow but can also extend to the ms range. This slow DA can depend a lot on the actual manufacturing process (e.g. rough foils, cleanness).

If it is for a replacement for the capacitor in an 3456, I would consider a  NP0 capacitor from TDK.  I tested a 2.2 nF one, but they should also be available in 3.9 nF.  Not all NP0s are the same, but at least the ceramic caps are easy to get and cheap. It is also easier to fit a small SMD one (e.g. size 0805 or 1206) than an oversized THT cap.
For me PFTE caps are no longer an option: too large, hard to get and now also uncertain quality.

[Kleinstein]

I did one more short test on the ADC, to see how fast the integrator settles and thus how much time is needed between reference changes, before errors go up.
With the given feedback method (2 comparator checks per period), the reference signal is a slow 50:50 signal at "zero" and increasingly more short positive or negative pulses for a negative / positive input. With a modified program I did a comparison of different length for the short pulses. I compared 8 and 10 CPU cycles (500 ns , 625 ns) to 16 cycles (1µs) as my main mode before. In both cases a small difference shows up: the ADC gain gets slightly higher by 0.55 resp. 0.22 ppm. As far as I can see there was no effect on the linearity down to the 0.1 µV Level.
So even the 500 ns pulses are Ok for the integrator and no real need to look for faster OPs.

The short pulses have an effect, but so far the effect is linear. For the positive and negative side by itself this is not a surprise, as there is only an increasing number of short pulses. The lucky coincidence is that positive and negative short pulse have "exactly" opposite effect and thus the same change in gain for the positive and negative side.

[Kleinstein]

A small update:

It did the same test on the effect of short pulses with a 2 nd board. This board is still without the bodged in 74HC74 for synchronization and using just a crystal at the µC. There are small differences in the decoupling. The effect of short pulse was about 10 time larger with the 2 nd board and a small nonlinearity (still only some 0.3 ppm difference between +9.2 V and - 9.2 V) was visible.

However the short pulse effect turned out to be quite robust against changes to the circuit:
changing the resistors at the integrator (23 K / 46 K and 92 K),
adding asymmetry to the resistors at the integrator (another 270 K to ground),
loading the integrator output,
going from the 2 OP integrator to a simple 1 OP integrator and
changing the LV4053 to a HC4053.

So I still don't know which part of the circuit really determines the effect  . I had expected most of the change above to effect the integrator settling and thus the effect of short pulses. Some did a change visible at the scope, but essentially no effect to short pulses effecting the ADC reading. There is no absolute need of the integrator input to settle before the next switching - as long as it stays linear (that is allow superposition) it is OK.

[iMo]

"Short pulse effect" - short pulse means here the time in the modulation scheme where you a) set refP for Xus, b) you set refN for Xus, right?

[Kleinstein]

"Short pulse effect" - short pulse means here the time in the modulation scheme where you a) set refP for Xus, b) you set refN for Xus, right?

Yes, it is about the short pulse that occur in the modulation scheme during run-up. depending in the signal sign there are short pulses of either the positive or negative reference. The lenght is set by the scheme to some 0.5 µs to 1 µs and for testing I measure the difference in the results with 0.5 and 1 µs pulses. This is kind testing how fast the modulation can be and how much error to expect if the shorter pulses are used (assuming the longer pulses are OK).

The simple picture is that the integrator should have fully settled before the next switching happens - however as it shows this is not really needed. Much of the settling is linear in the sense that superposition is valid and this linear part has no effect, even if not settled.
Even the nonlinear parts effect the gain in (some 800) equally spaced small steps, though independently for positive and negative side. So even that effect can be tolerated if not too large and similar for both signs. So far the effect of short pulses is quite well behaved, though different between the boards. So 500 ns pulses seem to be still OK, especially with the 1st. board.

[Kleinstein]

I looked at a possible front-end to make a voltmeter (and possible DMM) from the ADC. This mainly is some protection, signal switching and an input amplifier. For my first test the amplifier will be a LTC2057 (easy and low noise but relatively high bias and spikes). Later it would likely be an chopper amplifier relatively close to the one in the Datron 1281. The general setup is also similar to the Datron meter, with switchable gain at the input and only a buffer directly at the ADC.

Instead of the more conventional circuit I want to try a slightly odd version where the common input terminal in not fixed at ground, but moving opposite way to the amplifier output. It works in a simulation and AFAIK the concept also worked with an SD ADC (with differential input) in another thread: https://www.eevblog.com/forum/projects/need-advice-for-adc-buffer/msg1627207/#msg1627207
I would not be surprised if some DMMs with SD ADC (e.g. Sigilent SDM3065) also use this concept. At least it would be a logical way to get a 20(26)V high Z range with CMOS multiplexers at the input that are only good for some +-18V supply. This concept also results in low common mode voltage to the differential ADC input, which helps with INL.

The multi-slope ADC has a ground referenced input, but can be used in a quasi differential mode, switching between the positive and negative side instead of input and zero. This way the ADC acts as a differential input ADC with a +-20 V range, though with the limitation of near zero common mode signal and requiring 2 conversions (but no extra zero) for one reading.
The native input range would be good for some +-20V, despite of using only a +-15 V supply. So it looks really attractive - nearly to good to be true. So it there some hidden catch ? For internal cal measurements the ADC would likely need to run more conventional relatively to ground. So I still need to have the fall-back to a conventional fixed (though buffered) common terminal. The attached diagram is for the very basics only (1 gain step), the MUX at the right would be already part of the current ADC board.

The Keithley 2002 has a +-20 V high Z input range, but only uses a +-11 V ADC. So I had some hope to find a similar concept and some ideas there. There is no schematics available and the service manual only gives a crude block diagram. However the description of the self test steps gives more details. Combining the information gives a more detailed, though still incomplete diagram: The circuit seems to use a more basic concept, with an additional divider after the initial buffer for the 20 V range - relatively similar to the 2001 . So not much to learn from it  .

[wildhog]

I would imagine that the CMRR/PSRR of the OPA145 would be quite linear -- this could easily be tested anyways.  If it is, its offset could be calibrated without the need for using the bootstrap circuit.  If it has some gentle non-linearity, it could at least be calibrated in a piece-wise linear fashion.  Did you look into that possibility?

Also, did you consider using a lower noise input amplifier like the OPA828?  You mention that the heat from the buffer amplifier could cause INL errors,  but since the device remains at a constant IQ during the entire conversion, why is this the case?

Thanks,
Dave

[Kleinstein]

The CMRR is not per se linear. It may be in first approximation, but not for sure. I don't think testing is that easy, as the difference i really small and there can be offsets and low frequency noise. So just having a null meter between the input and output of the buffer is not sufficient. It would be more about an lock-in amplifier and modulating the input.
For the input buffer I am more like thinking about switching to an OPA189 chopper stabilized OP. This one gives well better than 140 dB CMRR and gain. So it looks like good enough and is reasonable low power. The other advantage is that the common mode range is larger, so that the +-15 V supply is sufficient. The OPA145 may run in to limits at some 4 V from the positive rail.

The bootstrapped OPA145 itself is reasonable constant power as it runs on a little over 5 V and has not that much current (up to some 200 µA) to drive. It is not about the power changeing during one conversion, but the change with different input voltages.  The parts that provide the supply to the OP have quite some variations in the power: the heat shifts between the positive and negative side. This is why I had the transistor coupled in the initial design. It may still be Ok, but it is one of the few known possible INL sources.

I would like to avoid approximations like piecewise linear, as it would need extra effort and thus high precision instruments to establish the pieces. Without another DMM / calibrator that comes only close to the linearity aimed for, this is not a real option.

The main noise source is not the input amplifier (buffer) and also not the "slow" amplifier in the integrator, which is the most relevant OP. The main noise sources are the resistors (both Johnson and excess noise) and with faster modulation also some switching related noise (e.g. Jitter and variations in charge injection). If not measuring near 0 V the reference is also a pretty important noise source.
So replacing the already good OPA145 / OPA1641 with a more expensive, lower noise OPA827 would not make a noticeable difference.  The OPA827 may still be an option for a single OP integrator, as it is fast and still accurate. This would not be for lower noise, but higher speed.
The logical path to lower noise are better resistors instead NOMCA to reduce the excess noise. Already going from 50 K NOMCA  to 2x20 K in series should give a slight improvement. Besides lower additive noise this might also improve gain variation as a kind of multiplicative noise.
Currently the next step up would be more like a 2 nd LM399 and improvement in decoupling.

[jbb]

The pseudo-differential input trick is interesting but makes me a little nervous. To a first approximation, you get 2 readings, so double voltage and sqrt(2) noise... seems too good to be true.

The ‘inverter’ R ratio shouldn’t be a killer, because the voltage across both arms is measured.  Fitting a compensation cap back to the inverting input is almost certainly required, but could that cause odd behaviour when there is some high frequency content on the input?  There could be practical issues with the ADC ground plane capacitance vs the output of the ‘inverter’ op amp.

All in all, the real question might be “how useful is a 20V high Z range to you?” Some applications might really benefit from it, others not so much. (For example, when I’m pushing for accuracy at work I’m often down in the 0.1 to 5 C region.)

[Kleinstein]

The capacitor at the inverter to slow it down is likely needed for stability - depending on the main amplifiers phase reserve it may work without, but to be on the safe side the inverter should be at least 10 times slower than the main amplifier.

The pseudo-differential input trick is interesting but makes me a little nervous. To a first approximation, you get 2 readings, so double voltage and sqrt(2) noise... seems too good to be true.

The pseudo differential way does not even add much to the noise: the alternative classical method is alternating between the input and a zero reading. So the noise level would be about the same.

There is also another more indirect advantage on noise:
In the classical auto zero mode the input is only sampled half the times and this makes the input sensitive to noise (from the source and input amplifier) from frequencies around 25 Hz (with 20 ms integration). There is the possibility to filter this noise, but an analog low pass filter at some 10 Hz is slow. It gets even worse if the ADC runs at 10 PLC.
With pseudo differential sampling the input signal is essentially sampled all the time. So essentially no aliased 25 Hz noise from the input, though some 25 Hz noise from the inverter.

AFAIK some (if not most) sigma delta ADCs realize there differential inputs this way with 2 internal ADCs. So The idea is not that new.

I know there is a limited use for a 20 V range compared to a 10 V range. However if it comes at a low effort / cost, why not ?
There are a few complications with possible amps or 4 wire ohms ranges, but no as far as I have looked at it is not too bad.
The  "too good to be true" part makes me worry a little, but there is still the fall back option switching the inverter to a ground buffer.
There is some limitations to non auto zero mode, but that is OK for me.

[SilverSolder]

[...]
For the input buffer I am more like thinking about switching to an OPA189 chopper stabilized OP.
[...]

When in neanderthal mode, I have successfully used this amp as an ad-hoc buffer with literally no supporting components at all...  it is an extremely stable and generally likeable component.  It seems an excellent choice.

[MiDi]

[...]
For the input buffer I am more like thinking about switching to an OPA189 chopper stabilized OP.
[...]

When in neanderthal mode, I have successfully used this amp as an ad-hoc buffer with literally no supporting components at all...  it is an extremely stable and generally likeable component.  It seems an excellent choice.

Not sure about that:
https://www.eevblog.com/forum/metrology/emi-measurements-of-a-volt-nut/msg2819014/#msg2819014
and following posts...

[SilverSolder]

[...]
For the input buffer I am more like thinking about switching to an OPA189 chopper stabilized OP.
[...]

When in neanderthal mode, I have successfully used this amp as an ad-hoc buffer with literally no supporting components at all...  it is an extremely stable and generally likeable component.  It seems an excellent choice.

Not sure about that:
https://www.eevblog.com/forum/metrology/emi-measurements-of-a-volt-nut/msg2819014/#msg2819014
and following posts...

Fair point - but how hard can it be to keep EMI out of the way? - it wasn't a problem to me even with a bird's nest approach, but my lab area is pretty quiet EMI wise.

[wildhog]

The  "too good to be true" part makes me worry a little, but there is still the fall back option switching the inverter to a ground buffer.

Why a ground buffer and not just ground?

[Kleinstein]

The effect of just 10 K in series and also the added capacitance does not look that nice. So It does not look such an easy going.
I can have a relatively low and rather constant source impedance for the OPA189, though I definitely don't like 100 pF to ground very much - a little less may be OK with settling.
The OPA189 would still be an option to try. Even if the new ADC board has more like a 3 OP version it would be easy to only populate 1 and add a bridge.

For a bootstrapped OP buffer I found another possible configuration: the input amplifier of the Keithley192 (from the old days when the instructions still included schematics) uses 3 OPs, with the the final OP not just as a buffer but with additional lower frequency gain. So this version also increases the loop gain and this way should have very good linearity, even if the single OPs don't have that much gain.

Why a ground buffer and not just ground?

The ground buffer comes out easy when the inverter is switched "off" at the input side. The buffer for most cases it not inside a critical path, so errors of that buffer should not be that bad. I hope I would need to switch back to ground buffer mode only for some kind of ACAL measurements to measure the amplifier gain and maybe if later added for 4 wire resistance measurements. It would add a little noise, but not much. Offset and output impedance should have little effect. I could use switching at the output, but this would need lower resistance switches and leave the ground return current from the gain setting.

[saturnin]

The Keithley 2002 has a +-20 V high Z input range, but only uses a +-11 V ADC. So I had some hope to find a similar concept and some ideas there. There is no schematics available and the service manual only gives a crude block diagram. However the description of the self test steps gives more details. Combining the information gives a more detailed, though still incomplete diagram: The circuit seems to use a more basic concept, with an additional divider after the initial buffer for the 20 V range - relatively similar to the 2001 . So not much to learn from it  .

The input buffer in KEI2002 may be a composite amplifier which consists of U245 (LT1124) & U249 (LTC1050). It provides low offset, low noise and low input bias current. I guess its topology is as shown on the attached picture. As the block diagram in the documentation suggests, the signal from the input buffer goes to A/D MUX (U222) and then to A/D buffer (U226) which should be very similar to the A/D buffer used in KEI2001.

All of above is only a speculation based on my investigation of circuit topologies used in KEI20xx series. I have a KEI2002 waiting for repair (need ADC board, or ADC ASIC)... If it helps I could check what the real topology of the input conditioning is.

[TiN]

Here is K2002 ADC schematics for reference. 

[Kleinstein]

As similar parts are used I would expect the input buffer of the K2002 to be similar to the AC input amplifier in the K2001. Because of the 20 V range it also needs bootstrapping of the supply.
From the description of the self tests the 20 V range looks odd with an extra 100K-100K divider and extra buffer (U217 (OP97)+likely support by U257 (AD711)).
The rest of the circuit looks rather conventional, with a CMOS MUX and it looks like a single (likely selected for good linearity) LT1007 as the main amplifier.
The odd thing is that there seem to be a direct x1 path (used in self tests) and thus a 10 V range. However it looks like it is not used in normal operation  .
The gain setting resistor for the x50 amplification is the high end sealed BMF pair. The x5 gain uses one of the blue dividers. There is also a precision 1.75 V reference (from LTC1043) - so there may be some kind of ACAL for the 2 V range - at least the HW part is there, for not much other use.
I have a crude circuit plan (for the DCV and amps part) deduced from the test descriptions. I have to redraw it one more time to make it more readable.

[saturnin]

It is as I thought - the input buffer circuitry is basically as shown on the schematic I posted above. It is powered by an isolated DC/DC converter which provides several voltage levels.
As for 20V signal path, the input buffer output is divided by 100K-100K divider (20V -> 10V conversion) and then it is buffered by U217 (OP97). U257 (AD711) acts as a tracking voltage regulator for U217.
There is a direct x1 path. I might be used for low voltage ranges (haven't checked this). Obviously it can't be used for 20V range since A/D buffer (U226) is powered by +/-15V.

I must say reverse-engineering of KEI2002 is definitely not for the faint-hearted. Four layers PCB, buffers, protections and local auxiliary voltage regulators everywhere and on the top of that deliberately misleading service manual (can't believe so many typos can be made unintentionally - thank you Keithley ).

I think the KEI2002 performance can be improved slightly be using modern opamps, but it has to wait until I get functional ADC board to test this.

[Kleinstein]

Attached is the crude plan for the voltage input of the K2002, that I got from the descriptions of the self tests. I have not check this against real HW and there are some contradictions and unclear formulations so take it with a gain of salt.

From the description it looks like some Ohms modes use the x 1 path.
From the board pictures I saw, there is not much unidentified circuit around U226 (the main amplifier). So with just a single OP (LT1007) used as the main amplifier, the achieved INL level is already surprisingly good. For some odd reason the buffer on the divider for the 20 V range got more attention (visible on photos, but not in the test description).

Back to my ADC design: I populated a 2 nd board to do some more tests. The 2 nd board uses just a crystal and no external sync. For some reason the 2nd board shows rather high INL error. With some software version the turn over error is up to 250 µV, so really bad. I don't think this is due to the different clock or missing sync (the first board was OK without the extra flipflop). The buffer amplifier also does not seem to be the reason.  My guess is more with transients at the integrator - though equal parts are used.  To see it positive: the larger errors may help to identify the mechanism that causes so much INL.  However so far not much luck. Changing the resistors at the integrator (20K ,46K and 92 K) has not much effect. Also the noise with 92 K resistors is still at an acceptable level so a single 100 K  LT5400 may be possible with not too much noise.
I also tested another run-up version with zero phases in between. So the reference is not directly going from positive to negative, but with a short zero phase in between. So the steps a spread in 2 smaller ones. The SW gets confusing, but did not really improve things.