DIY high resolution multi-slope converter

[openloop]

On the subject of the power supply:

In Horowitz and Hill, "The X chapters" there is a good treatment of a relatively simple, low noise, low common-mode noise isolated power supply intended for scientific instrumentation.

Chapter 9x.14

Fun read, if (as I assume) you're into that kind of thing.

[dietert1]

After doing some experiments i'm not very impressed with those "X-Chapter" proposals. That converter puts about 0.5 mV of common mode output into 50 Ohm = 10 uA. A 50 Hz power supply i made recently based on a commercial 50 VA two chamber transformer outputs about 3 uArms into ground. That means with a ground wiring of 0.3 Ohm or less one gets below 1 uV of error voltage. And this is 50 Hz, so inductance matters less than at 100 KHz. And there are commercial 100 mH common mode chokes!

Regards, Dieter

[Kleinstein]

The x-chapters DCDC converter does not look very impressive to me either.  When using a forward converter, there is no need to have very good coupling at the transformer. So no need to have the winding as primary - secondary - primary.  It can be simple 2 well separated windings (e.g. 2 chambers, or opposite sides of a relatively large ring core) with sufficient spacing (e.g. a few mm, not just a capton tape). The efficiency may not be great, but probably still better than the loss from linear created sine drive.
I have tested a simple push pull DCDC with a relatively large ring core (some 35 mm OD) like this and it seems to work good enough (no obvious extra noise). However it looks somewhat hand made and not pretty. The coupling capacitance should be relatively small (e.g. < 5 pF) - though I have not measured yet.

With the aim of little capacitance to ground, there is only a limited effect of a common mode choke.

[openloop]

Kleinstein,

In defence of the X chapters: 

So no need to have the winding as primary - secondary - primary.

They do not have that either. All they have is a secondary, sitting between two (not shorted) layers of copper tape (grounded) serving as electrostatic shield.

The efficiency may not be great, but probably still better than the loss from linear created sine drive

They also point out that trapezoidal drive works the same. They say that pretty much anything without discontinuities should work.

With the aim of little capacitance to ground, there is only a limited effect of a common mode choke.

Some form of a ground connection will be provided by the user...   

[openloop]

Dieter,

A 50 Hz power supply i made recently

Well, duh! 
If an old school power supply is an option then sure. All DMMs on my bench are like that.

[dietert1]

I noticed discontinuities from two sources:
a) The primary side will ring when current switches from npn to pnp driver and vice versa.
b) The secondary stray inductance will ring with the rectifier bridge turning off, so it needs a snubber (some nF).

Until parts arrive i used a large 6 mH common mode ring choke. Also one would want some voltage regulation from secondary to the primary side oscillator amplitude. I used a wien bridge with a n-channel FET to get something nice. The FET saves the third OpAmp and it can be replaced by a HF11 optocoupler (+ 2 pF). The stray capacitance of a conventional two chamber transformer is about 50 to 100 pF.

Regards, Dieter

[julian1]

How are the analog switch dgnd pins handled? 

Are they merged as a net with analog gnd (ADGND?), or are the switch gnd traces pulled out to a star ground?

Perhaps it does not matter too much - given relative infrequency of switching and dominance of charge injection noise?

[Kleinstein]

The analog and digital (main) ground are linked at the ground pin of the LM399 reference.  The analog GND mainly goes to low current inputs, so there is no extra star ground used for this.

With hind-side the AGND routing may be more tricky than I though, so a separate path for the divider at the integrator (the only path with more than an OP input) may better use a separate path to the central ground point at the reference. I don't know for sure but things like ground currents (also dynamic, not just static) can be a cause for INL errors.

I don't think charge injection is dominating noise. At least the noise does not change much if the modulation frequency is changed (some 40 kHz to 160 kHz).  So far the 2 larger noise sources are the resistors thermal noise and excess noise from the resistors (NOMCA). Than likely comes noise from the "slow" OP at the integrator (OPA1641), and maybe some not so well understood source like charge injection, supply noise, mains hum or clock jitter.  Anyway ADC noise is no longer the main concern. It is more about improving the INL and finishing a front end and output side software.

[Kleinstein]

 
After quite some time here is a small update on the ADC. Attached a new version of the PC side software. This time for FreePascal / Lazarus  (a free IDE similar to Dephi). The function has not changed very much, mainly the possibility to run with USB-UART adapters and Win7/8/10.

For the ADC board, I still have 2 rather odd effects, that are rather resistant to changes to the circuit:
First there still is some effect, that initially looked like a delayed effect. One reading is to a small fraction effecting the next reading. However ever it turned out that much of the effect is not from the actual ADC reading, but the selected channel at the input mux. The really odd point is that a similar effect is still present with just switching the control lines at the µC, even without the DG408 MUX in the socket.
The effect of the MUX channel is not nice, but as long as it is stable (it is hard to change even if I try) one can subtract it as a channel specific offset.

To get only the delayed effect from the ADC and buffer, but not the mux, the effecting voltage is varied externally. 2 zero readings are compared with different readings before. Reusing a program part made for a slightly different purpose the sequence is  0 V,  variable voltage, 0 V and 7 V reference. Ideally the 2 zero readings should read the same, maybe with a small offset from the different active channels before. There is a small effect of the variable voltage on the next reading, not much, but just visible. For noise reduction the data points are the average over 50 sequences at 1 PLC each. The curve combines data from going up and down in the voltage several times.
A known mechanism to cause such a delayed effect is the slow part of the dielectric absorption in the integration cap. However this should have the opposite sign and is expected to be a little weaker (e.g. 10 ppb range). Chances are the observed effect is something like a thermal effect.

The second odd point is that different run-up version give a slightly different result. The main nasty point here is a slight difference in gain (close to 1 ppm) for negative readings compared to positive ones between two versions with different minimal pulse length. Chances are the version with longer minimum pulse length is less effected, but this is not sure, as only the difference can be measured with high resolution.

[ali_asadzadeh]

Thanks Kleinstein for sharing

I suggest you make a repo for this project on Github, It make it more convenient to see the latest update there.

[ali_asadzadeh]

Out Of curiosity, How much Resolution and sample rate could you get from this ADC,
Also I have found this new cheap ADC from TI ADS131M08IPBS & ADS131M04IPBS, they have 20.3 ENOB @ 250sps, so the questions is Does it worth the effort? or can these new ADC's from TI be used to enhance this  multi-slope converter?

[Rerouter]

I have played with the ADS131M08 before, that spec assumes a perfect power supply with no noise, PSRR drags it down a little, as well as reference drift, for relative measurements they are little unicorns, for repeatable its a little worse,

As a cheaper method you could just build a direct sampling ADC without the slope comparitor using that chip, however scaling the input to a suitable range would be mostly the same including an input buffer as its impedance sensitive,
if you built it well, you have a -1.5 to +3V input range,

You can tease out a few more bits using the gain assuming you have a suitable offset DAC, but that is not too easy either,

[Kleinstein]

I currently have a 20 ms integration time and thus some 40.4 ms time for an auto zero cycle with 2 measurements. The theoretical / numerical resolution is at some 28-29 bits (depending on the gain used for the µC internal ADC). There is no real need for more resolution from the auxiliary ADC - I currently use some 8-9 out of 10 Bits.
The noise level is at some 850 nV_RMS with 50 K resistors (NOMCA) and some 450 nV with 20 K resistors (2xPTF56). This is close to  24 bit ENOB for 25 SPS, depending on the input range / front end. For comparison with SD ADCs one may have to look if the readings are independent. Some filters give kind of overlapping samples, like a running average filter.
 
I initially had a fast version that was at around 200 µs for the conversion (and still good resolution) - but the data transmission separate. So a speed up to some 5000 SPS should be possible. For the very fast conversions the integrated ADCs definitely have some advantage.

The SD ADCs can offer quite low noise, but the linearity is limited and they start with a reference of some 2.5 -5 V.  The high stability references tend to be around 7 V and it thus needs extra effort to generate the reference and also the input stage needs an extra divider.

For lower needs the SD adc chips are hard to beat. The really low noise noise ones (e.g. AD7177) are not that cheap and still need some support circuit (e.g. reference buffer, scaling).

[branadic]

Kleinstein, question:

Did you already test TOMC16032002AUF?

If 20k is a good value and noise is not to bad either, refering to the measurement by Nikolai Beev, they might be an economical solution and are available, other than TDP16032002 or multiple LT5400-1, which perform even better in terms of noise.
Though there are no public results of noise measurements on PTF56, other than many other resistors, that where tested in Resistor Current Noise Measurements.

-branadic-

[Kleinstein]

The 20 K resistance version is more like for INL testing to make some of the errors intentionally larger. A 8x20 K array may still be OK if used with 2 resistors in series. Because of the INL effects I would not like to go much below 40 K. Without excess noise from the resistors I would expect to reach some 500 nV noise level also with 40-50K resistors.

My current plan for a next board is to used DFNA type resistor arrays. They are also in the measurement of resistor arrays, only slightly higher noise than the TOMC type.

The PTF56 also seem to have some excess noise. The TC matching in an array can also be better - though the resistors I have show good matching (a little over 1 ppm/K for the gain drift, that depends on 2 sets resistors). The self heating effect on INL depends on the individual TC with separate resistors, but the relative TC with a coupled array. So an array is the way to go. I still have PTF65/PTF56 planed in the input stage.
I have planed a noise test of some  PTF56 resistors - using the ADC to read the amplified noise.  The circuit is also a test for the planed input stage.

[ali_asadzadeh]

Thanks Kleinstein for the points,

I initially had a fast version that was at around 200 µs for the conversion (and still good resolution) - but the data transmission separate. So a speed up to some 5000 SPS should be possible. For the very fast conversions the integrated ADCs definitely have some advantage.

Do you have the design? Also would you please share the eagle files too?

I know the basics of dual slope ADC ,IS there any post detailing how your Converter works?

[Kleinstein]

There are a few minor changes from the initial board/ circuit, that are described later. The main changes from the initial circuit are with the input buffer, the supply decoupling/filtering at the µC and 4053 and using a canned oscillator instead of just the crystal at the µC.
For a simple / low cost version a single OP is OK for the input buffer. The 2  OP version is there to be reasonable confident to not have INL effects from the buffer.
There is a circuit diagram at around post 241, redrawn from User Rerouter, that is rather close to my actual circuit. There should be also some eagle / Kicad files around. My last changes are more bodged on and thus no board for this.

There is some description on the workings in the initial few posts of this thread.
The fast case used the same hardware, just a minimal run-up phase with only integrate for a fixed time, so a  dual slope like run-up and multi-slope type rundown. It was used as initial test version for development. It is still there as dead code in the ASM file. A shorter run-up with only a few run-up cycles would also work, possibly even faster -  this also needs a higher baud rate. I have not tested beyond some 100 kbaud.

[ali_asadzadeh]

Thanks Kleinstein for the hints, I have some Ideas to paly with your circuit with more modern parts, Like the 1GHz MCU i.MX RT1170 from NXP or the STM32H parts, they are 480MHz or 550MHz and have 16bit internal ADC,

https://www.eevblog.com/forum/microcontrollers/the-1ghz-mcu-i-mx-rt1170-is-available!/

Since it can count the time with 1GHz, it should give us about 100 times the speed, also they have way better ADC's, so the first part of it is to understand fully how your circuit is working, I think I should keep reading for some time.

[Kleinstein]

It may make sense to use a slightly faster µC. However the faster µCs also make things more complicated, as they have things like internal caches and may also cause more EMI problems. The  old 8 bit AVR µC has the advantage that it does not use caches and gives 100% predictable execution speed. With a more modern ARM CPU one would more like need to rely on the µC internal event system to do the really time critical parts. Alternatively one may use extra timer input capture to at least measure the actual times. The worst case delays may not be that much better than with the old 8 Bit µC.  A µC internal PLL can also add jitter and complicate things.

The way the ADC is made, it does not really need a faster µC or higher resolution for the auxiliary ADC.  The points at the wishlist are more like a hardware buffered UART and a slightly faster (e.g. 100 kSPS instead of some 10 kSPS) ADC and maybe a low grade DAC.
The difference would be a slightly higher maximum speed, not lower noise.

I envisioned an STM32F334 version using the event system. While C code is easier than ASM, it makes heavy use of the timers and event system and is this way quite tricky, if it works at all. Somehow not the best project to start with a new µC.

The critical point is no more the noise (the main part is very likely from the resistors) and not at all the quantization limit. Different resistors are on the list as a possible improvement, e.g. for a new board, but low priority.

The weakness is more with INL, which is quite a bit more difficult part. One has to looks for all those small things one normally ignores and data-sheets usually don't tell.  Here it looks like the nasty part is from some EMI or odd high frequency interactions via the supply. 

There was a red herring with loading the OPA172 at the integrator: there is an effect of the load current visible on the scope, but it very much looks like the overall effect on the ADC result is minimal. It effects both transitions and it looks like those 2 effects near perfectly compensate. Of cause the OP data-sheets don't give curves for open loop output impedance as a function of output current and I don't expect the spice models to be accurate at such a detail.

Currently my prime suspect it the canned oscillator - there may be an effect on the clock frequency from the load to the clock signal or via supply ripple.

[Castorp]

In case you're interested, here are some more (preliminary) numbers for Noise Index of the arrays:

NOMCA: 1 kOhm -33.7 dB; 2 kOhm -29.1 dB; 5kOhm -24.9 dB; 10 kOhm -29.5 dB; 20 kOhm -27.2 dB 50 kOhm -34.9 dB
TOMC: 100 ohms -60.9 dB; 1 kOhm -60.8 dB; 10kOhm -52.1 dB;  20 kOhm -60.1 dB
DFN: 1 kOhm -51.5 dB; 10 kOhm -43.3 dB; 100 kOhm -48.5 dB
ORN: 1 kOhm -75.6 dB; 10 kOhm -72.5 dB; 50 kOhm -67 dB; 100kOhm -64.8 dB

The numbers for ORN are pretty much at the measurement limit, so in reality they are even quieter. In fact they seem to be the least noisy thin-film arrays I've tested so far, together with MORN (different package).
AORN are similar to NOMCA but slightly better, hovering somewhere in the -35 dB ballpark regardless of the value.

[Kleinstein]

Thanks for the data.

From the data sheets I found the MORN and ORN arrays show different specs - so it looks a little more difference than just the case.
They could still be very similar and only different are data-sheets with more available data for the newer version.

Anyway the ORN or MORN arrays really look promising.  I think I would want something like >10 dB better than the current NOMCA (50 K). So most of the other arrays seem to be good enough, just not NOMCA or AORN.

The ORN type would even allow for an upfront test on the existing board with a minor (link 2 pins ) bodge.

[ali_asadzadeh]

I currently have a 20 ms integration time and thus some 40.4 ms time for an auto zero cycle with 2 measurements. The theoretical / numerical resolution is at some 28-29 bits (depending on the gain used for the µC internal ADC). There is no real need for more resolution from the auxiliary ADC - I currently use some 8-9 out of 10 Bits.
The noise level is at some 850 nV_RMS with 50 K resistors (NOMCA) and some 450 nV with 20 K resistors (2xPTF56). This is close to  24 bit ENOB for 25 SPS, depending on the input range / front end. For comparison with SD ADCs one may have to look if the readings are independent. Some filters give kind of overlapping samples, like a running average filter.

Kleinstein you told that your integration time is around 20ms, and I know that ATMEGA48 can be clocked at most 20MHz, so in 20ms the timer can count to the maximum of 400000, so how you get 28-29 bits resolution, since 400K is around 19 bit so what am I missing something in here?

[Rerouter]

Count the number of positive / negative slope cycles (Positive slope voltage * positive count - Negative slope voltage * negative count), This derives most of the resolution of the converter, the rundown phase then drags out a little more, and finally the ADC reading of what is left drags out a tiny amount of resolution,

The resolution derived by the slope cycles is a tradeoff between switching cycles, charge injection, drift and a few more fun factors, the time it takes to complete these cycles do not actually contribute to the resolution, but can be used to increase confidence in the reading technically if you had enough compute left over,

The rundown to my understanding is just fixed length pulses until the comparator changes state, while you can go with a timer method to capture the nanosecond it reaches the threshold, that is trading resolution between the ADC that samples the residue and the timers precision, so you don't actually gain much,

I drew up the math for it some time ago, though the exact pattern or method may have changed slightly since then, https://docs.google.com/spreadsheets/d/124oaWnT20oyATqJzljLi7ERs9dDA7BqPNQoNRmwFV4k/edit?usp=sharing

[kleiner Rainer]

Kleinstein,

did you have a look at Silicon Labs 8051 derivatives? At work we use them in large quantities, and the tooling is free (Keil C-Compiler and assembler). Support is excellent and getting samples and demo boards is hassle-free, even for our interns and their projects.

Maybe this one could be interesting:

https://www.silabs.com/documents/public/data-sheets/C8051F35x.pdf

24-bit A/D, 2 current-mode 8 bit D/A, operation up to 50MHz, several PWM and Timers, FLASH-based and a buffered UART.

IIRC, there should be a demo board in my stash of samples, if you are interested:

https://www.silabs.com/documents/public/user-guides/C8051F35x-DK.pdf

Tooling:

https://www.silabs.com/developers/8-bit-8051-microcontroller-software-studio

Greetings,

Rainer

[Andreas]

Since it can count the time with 1GHz, it should give us about 100 times the speed, also they have way better ADC's, so the first part of it is to understand fully how your circuit is working, I think I should keep reading for some time.

Hello,

increasing the time resolution does only help if the clock stability is maintained.
Usually those parts have PLLs which are much less stable than a XTAL clock or Oscillator.

As I have seen with my 10V LM399 experiments the clock stability
has a large influence on stability of the analog part.

with best regards

Andreas