DIY high resolution multi-slope converter

[Kleinstein]

A short update:

I think I got the software for the STM32 µC so far ready to give useful results for the ADC.
The code part to measure the ratio of the positive and negative reference or better the ration of the difference divided by the sum of the references finally seems to work. The expected result is 43 and the measured ratio was 42.85 - so well in the range of the resistor tolerances. IT looks good enough to not get much DNL error from there.

The hardware is still using only 1 OP in the integrator (the 2nd OP is intentionally not yet populated, to do the test with only 1 OP at the integrator).
As far as I can tell the noise is still a bit higher than with the AVR version, but not much, and the reference filtering is still missing, and no shielding. So there is still a bit improvement expected.  The curve in the attachment shows the difference between the results when using the ADC with 2 slightly different run-up variations (longer and shorter pulse length). The range from -0.4V to -0.3V is the critical range, where the high low ratio is near 50% for the run-up and thus relative large variations in the integrator voltage. The curve shows some variation (some +-8 µV) on top of noise in the 6 µV_pp range. Compared to the AVR based ADC, there is more short range variations, but not much longer range effect.  So far the modulation is relatively slow and the AVR version also has a chance to get lower INL with slower modulation. At least no large INL error so far.

Much of the shorter range effect is similar to the error expected when using only 1 OP at the integrator: The voltage at the input of the integrator is exactly zero bu varies a bit. The integrator has an input impedance of about  1/ (C * GBW* 2*pi) or some 7 Ohms for the 10 MHz OP. This causes less effect of the references in the run-up phase than in the run-down phase, when there is not extra resistor to a fixed signal at the input. The difference is about in the calculated oder of magnitude.  So chances are the 2 nd OP could suppress much of the shorter range errors.
One may be able to compensate numerical too.

From the circuit on the picture I had to remove 1 inverter chip: Murphy got me with exactly the wrong phase of the clock when the IOs at the µC change and I got nasty errors from violating the setup time for the FF. Looks like the STM32L051 changes it's ouputs at the rising slope of an external clock. 

[ali_asadzadeh]

That's great, when do we expect to see a github repo with the STM32 schematics and code?

[Kleinstein]

I first want to do a few more tests on the INL for the STM32 version.  The code also needs a bit more polish - switching programming languages can be a bit confusing. Currently the output is ASCII text send to a terminal program, with a few cryptic 1 key commands.

The circuit is still very close to the AVR version, mainly a different µC and a flipflop for external resync (I had tried that dead bug with the AVR too) and level shifting (the LV4053 is not perfectly happy with only 3.3 V signals). Level shifting is a bit unconventional with a chip with intermediate supply voltage in between.  Kind of 3.3 V  -> 4 V -> 4.7 V steps for the supply.

So I repeated the test with the 2 nd OP installed. In addition I have a filter cap for the reference voltage. The filter cap give a significant reduction in noise: from some 5-6 µV_pp to some 3 µV_pp with the filter cap. I did remember that the filter cap did help with the AVR version, but I did not remeber that it was so much. So filtering the reference can be worth the effort, as it is relatively easy. Even near zero signal some of the higher frequency (e.g. 50 kHz range) noise of the reference gets through and gets visible. I think some of the commercial DMMs miss on this as it is not that obvious.
 
There are a few small waves still visible in the curve, but the level looks OK for me, at least for now  .

[MiDi]

A couple of month ago I decided it would be interesting and educational to build one myself.
It is based on the PCB from Rerouter with some minor modifications and uses parts from mouser (see partslist).
Eventually I had some spare time to build it, which was straight forward but took quite some time.
Had to modify the FW for 16MHz and different input mux configuration, but then it worked with great help from Kleinstein 



At least kind of - there are two major problems, the noise is way too high (~10x - ~10µV StD) and the offset is too high for input short & ref (>10µV).

Did some investigation and it seems the input mux DG408 shows weird behaviour, it overshoots by a decent amount and takes really long to decay, that would explain the offset in the readings.
Filtering with 100nF at the input of the buffer did not change anything significant and isolating the output (NC) of the input mux did not change anything either.
It cannot be charge injection - that would decay quite fast through the low resistance of the mux switches into low impedance GNDS and ref at the mux input.

Regarding the noise I have no idea where to start
At least the reference/Ref+/- shows no visible noise/oscillation on the oscilloscope and no significant differences with external or onboard Ref nor connecting the ops outputs directly to Ref+/-.

With AZ mode there is a problem with the program, the results are just crap & the screen values and recordings are totally different.

Attached some pics, measurements and all data logs (4x 3R, 2x 2R, DA test, Slope K1 K2)

[MiDi]

Attached the details of input MUX DG408 output overshoot

[Kleinstein]

The MUX itself should not create much overshoot. It is possible that the buffer creates some obershoot / slow settling. An amplifier with bootstrapped supply is always a bit tricky with the stability / settling. I would expect the overshoot more from the buffer than the mux.  Anyway for looking at the noise offset drift of the ADC only, one could use the case where the input signal is not connected to the ADC, so the 4053 channel allways off (modus T).

The integrator waveform looks as expected. 

To get low noise, the values for the slow slope (sum) and aux ADC should be reasonable correct.
The slow slope part looks reasonable, though the result of the k1 measurement shown is 20.88 while the other files use 20.90. This is not far off, and should not cause that much different in noise.  The part with K2 seems to be not working. So there seems to be something wrong with the residual charge measurement. The reading of the µC internal ADC look suspiciously constant at 506. So there may be a problem with the last amplification step (MCP6002 ?). So far this is kind of only the classicl MS ADC without a working res. charge measurement for the last bit of resolution.

Most of the mubers in the file are still raw ADC units and not yet scaled to mV.

I don't have much time now, so just a short note.

[Kleinstein]

It looks a bit, like the ADC channel that is supposed to read the residual ADC reads something different, like the scaled down input voltage or maybe the average integrator voltage.  So there may be a small difference in the plan, like using different ADC channels / pins at the µC.
Which is the schematics for the PCB used ?

An interesting signal to look at is the ouput of the slope amplifier (NE5534). This signal should be about -700mV to 1400 mV near square wave in the runup, and somewhere in the 0 - 400 mV range after the rundown part and slightly, variable ( ~50 mV) between conversions. The trimmer will effect the level where the signal be approximately.

The DA test part seems to be net yet correct/fully implemented in the new Pascal program. I think I never used it with the new program. This part is more like an extra if everything else works.  It can be used to check the cap qualtiy and see leakage currents at the integrator.

[MiDi]

The MUX itself should not create much overshoot. It is possible that the buffer creates some obershoot / slow settling. An amplifier with bootstrapped supply is always a bit tricky with the stability / settling. I would expect the overshoot more from the buffer than the mux.  Anyway for looking at the noise offset drift of the ADC only, one could use the case where the input signal is not connected to the ADC, so the 4053 channel allways off (modus T).

Changed MUX DG408 already 2x with no difference.
I have set scale = 6951.95, what do you get as offsets for short and ref?
Someone an idea how to measure those overshoots with µV resolution and sufficient bandwidth?

The integrator waveform looks as expected. 

To get low noise, the values for the slow slope (sum) and aux ADC should be reasonable correct.
The slow slope part looks reasonable, though the result of the k1 measurement shown is 20.88 while the other files use 20.90. This is not far off, and should not cause that much different in noise.  The part with K2 seems to be not working. So there seems to be something wrong with the residual charge measurement. The reading of the µC internal ADC look suspiciously constant at 506. So there may be a problem with the last amplification step (MCP6002 ?). So far this is kind of only the classicl MS ADC without a working res. charge measurement for the last bit of resolution.

It looks a bit, like the ADC channel that is supposed to read the residual ADC reads something different, like the scaled down input voltage or maybe the average integrator voltage.  So there may be a small difference in the plan, like using different ADC channels / pins at the µC.
Which is the schematics for the PCB used ?

An interesting signal to look at is the ouput of the slope amplifier (NE5534). This signal should be about -700mV to 1400 mV near square wave in the runup, and somewhere in the 0 - 400 mV range after the rundown part and slightly, variable ( ~50 mV) between conversions. The trimmer will effect the level where the signal be approximately.

Plot with Slope output & ADC0 @PC0/PIN23:



Both residuals change a bit from cycle to cycle and when adjusting trimmer for null setpoint - runnning program L (Slope K1 K2) K2 changes significantly and in extreme gives out of range.
Schematics are same for ADC0 Edit: difference between old and new schematics from Kleinstein ADC0 -> ADC1, ADC1 unused (U20 not populated).

Rerouter:




Kleinstein:
EDIT: updated to latest version

The DA test part seems to be net yet correct/fully implemented in the new Pascal program. I think I never used it with the new program. This part is more like an extra if everything else works.  It can be used to check the cap qualtiy and see leakage currents at the integrator.

You could not, I added that part to the code to get the numbers - in hope somebody could decrypt it :

Code: [Select]

241: {DA-Test 26 chars}
begin
write('DA result: 0x');
das := '0x';
for n := 0 to 25 do
begin
da[n] := ord(Readcom);
write(IntToHex(da[n]),' ');
das := concat(das, IntToHex(da[n]));
end;
writeln('');
writeln(f, das);
}
end;

[iMo]

FYI - there is a third schematics by Kleinstein:

[iMo]

Could you bypass that input buffer?

[Kleinstein]

I get an offset of some 0.5 to 3 µV, for some reason dependent on the channel of the 408 and the speed of the modulation (choose runup with keys P,Q,R,V,W).
I think the higher offset is still from the ADC function not fully working and having the limited resolution in the current configuration. 

I looked at the schematics, and it looks like the AD0 and AD1 signals are swapped: I have the residual charge signal at AD1, rerouter has the resudual charge signal at AD0. So this would need a slight modification to the software.

As far as I have found there are only 3 accesses to the chanel choice of the µC internal ADC (register ADMUX) in the program. So ideally define a 2nd constant for the ADC setting and than use this instead of    "ADMUXval-1" .

Having U20 not yet polulated is good: the program does not yet suport it. In addition the DG419L in the BOM list is wrong - it should be the non L version. The extra switch would be an option to reduce the DA related error - I  kind of doubt this would be very relevant anyway.
Anyway get it running without first.

Measuring the fine settling of the ADC buffer amplifier to the µV range is tricky. I remember seeing artifacts from the scope, when coming out of saturation. The scope may need some time to recover after overload. One may have to measure the settling to the mV range and than assume some exponential decay for the rest.  Chances are it would need some extra clamping with fast diodes (not low leakage as likely in the scope) or anouther switch and than a scope with a good input amplifier and plenty of averaging. There are app- noted on how to measure OP settling. This may use similar techniques. A simulation could give clue on what to about expect.

Alterntively one can try a few different delays with the ADC ciccuit to see how much waiting is actually needed from switching the DG408 to starting the conversion. Usually one does not ned full settling to µV (ppm of the signal) - the missing part to full settling is only a small part of the integration time and thus a little more initial error is allowed.

For the buffer amplifier behind the DG408 a first point to check is of the OPA145 actually gets enough supply voltage (e.g. > 4.8 V). I had a problem with this in my STM32 version - the zener diodes may have quite some tolerance and leakage, so not all the 5.6 V zeners are equal, but normally it should be OK (I had a 5.1 V one that did not work).

p.s. :
the waveforms for the slope amplifier out and MCP6002 out look good - so likely just the ADC channels swapped.

[MiDi]

I looked at the schematics, and it looks like the AD0 and AD1 signals are swapped: I have the residual charge signal at AD1, rerouter has the resudual charge signal at AD0. So this would need a slight modification to the software.

As far as I have found there are only 3 accesses to the chanel choice of the µC internal ADC (register ADMUX) in the program. So ideally define a 2nd constant for the ADC setting and than use this instead of    "ADMUXval-1" .

p.s. :
the waveforms for the slope amplifier out and MCP6002 out look good - so likely just the ADC channels swapped.

First I thought I have a "Knick in der Pupille", but your schematics differ between versions in this point.
Freely adapted from Bob Pease: My favorite programming language is solder  :



Attached the results 

CU@MM

[Rerouter]

Both adc signals went throught a 4.7K resistor. Would recommend you flip them there

[Kleinstein]

I would have simply changed the software. The is not really that much to change: just the 3 cases the ADMUX register accessed.

I see the resistors R99 and R36 populated. So the SW should also change to use that refrence. It is nearly the same place where to change the ADC channels, at the  ".equ  ADMUXval " part relatively close to the top
In my program / PCB the ADC still uses the supply as the reference. The extrernal ref should be lower noise - so this time really better change the SW.


Anyway the quick hardware change also has its good side: there are now 2 consecutive readings of essentially the same signal (column 9 and 10 in the file with 3 readings).
These 2 should normally be rather close, with relatively little noise. So there is something a bit noisy around the µC internal ADC.
With the old program the ADC reading of the filttered channel was quite stable. So it is not the µC internal ADC itself, more like some higher frequency noise from the amplifier, maybe not enough settling time for Q2 and Q8 (transistors are a bit slower than diodes)

I have something like 3-5 x the gain and still less noise for consecutive readings.  A small difference in the circuit that I spotted is 22 pf for C15 - I have 47 pF (AVR) / 39 pF (ARM version). Not sure if the this makes a lot of difference, likely not.

Another point may be C37 - I don't have it populated and it may contribute a bit to the noise, though I don't expect that much extra noise.

Still before removing C37, I would have a look at the integrator settling (the LSP6 test point in the plan), just to see how much C37 effects it.

[MiDi]

Bodge was just to get it done quick, changing FW would have taken much longer incl. burning.
Will take quite some time before the suggested fixes are made to FW, due to MM and other priorities.

[Kleinstein]

a short update:
Most of the input section seems to work, but there is still some odd EMI like effect.  With a short at the input, it makes a difference if there is addional parts connected. This can shift the signal some 10-20 µV. So a bit too much for a real INL test.

I first simple test shows some 5 µV difference when testing a 8 V battery in the 10 V (more conventional) range and the 20 V (kind of diffenrential, so the ADC would see +4 V and -4 V to convert). So this looks a bit like some INL problem (e.g. turn over error) of some kind.
The difference between 2 conversions modes so far looks good, but I have not yet ran a longer test.

With just a short, the input is quite stable and the noise can be really low. Some tweeks with the DCDC part did not help much with the EMI effect, but it did improve the noise. So the noise is now lower than with the AVR based version, rather close to the calculated noise. This may be in parts due to a relatively slow modulation (some 32 kHz).

Attached is a measurement in the change of the ADC gain (read the internal reference back) after turn on. The noise is a little higher than with a short, as the measured reference in not filtered and has a bit of noise that gets effective with the reference to the ADC filtered (some 2 Hz LP).
The numbers on the left are part of the raw data send to the terminal window.

[iMo]

Could you calc the stddev from 800secs up till the end, plz?

[Kleinstein]

Could you calc the stddev from 800secs up till the end, plz?

The std. dev (RMS noise) for the 800s to 1500s part is 0.045 ppm which is 315 nV for the voltage reading.

[iMo]

For reference - my running stddev of a 399 (10.5V output, 34401A 100PLC) during a peaceful period..
PS: horizontal axis is samples num.
The stddev for entire set of 1544 samples is 890nV.

[Kleinstein]

Measuring an external reference is a different test. This gives to a large part noise and drift of the external and internal reference.

The ADC gain measurement is reading the same reference used for the ADC. In the simple picture this would not include reference noise and as the noise is the same on the input and reference side of the ADC. There is also essentially no effect of reference drift.
However with filtering of the reference for the ADC (but not for the input) the noise that is filtered out on one side will now becomes visible. This would in this case be to a large part noise at around 25 Hz as part of the off/on modulation in the auto zero cycle. This 25 Hz range part is the reason why so much filtering is at the ADC ref. This especially helps when comparing 2 external signals, like 2 external reference measurements or 2 different RU modes of the same signal, which is used as a test for linearity.

The reference filtering can reduce the noise for normal measurements visibly (e.g. 2 x), though this is not just the 25 Hz part, but also some higher frequency part (e.g. 10-100 kHz). Attached is a curve that shows the effect of adding the filter cap (added while the measurement was running). For some reason I don't know the usual DMMs don't inlcude much reference filtering, though this is a relatively simple way to reduce the noise a little. Usually the effect is smaller than here, because not many combine a very low noise ADC with a relatively noisy reference (LM399).

[iMo]

..For some reason I don't know the usual DMMs don't inlcude much reference filtering, though this is a relatively simple way to reduce the noise a little. Usually the effect is smaller than here, because not many combine a very low noise ADC with a relatively noisy reference (LM399).

Something like this (34401A)? Not sure the resistor there would be a good idea - would need adjusting, imho..

[Kleinstein]

The position for possible filtering would be about the right positions. However the 34401 ADC has so much more noise, that one would not notice the difference. So for the 34401 I would not mind the missing fitler. It would be more a point with the Keithley 2000, maybe 2001 and even the 3458.

The ADC in the 34401 can be used to learn how to get low noise - by learning from mistakes. The cicuit has some good aspects (e.g. the switches), but noise wise it also has weak spots. There are 3 major noise sources in the 34401 ADC.
1) the current noise of the OP27 in the intgrator is a mayjor factor for longer integration, like 10 PLC.

2) the noise from the resistors at the integrator. With 100K from the input and 30 K from the references (and the additional 42 K to ground) there is quite some resistor noise. The 100 K give voltage noise and the other provide noise current - so lower resistors are on the bad side there. The resistor ratio also give noise gain (AFAIR 6.6 ) for the voltage noise of the OP27 - with low voltage noise to start with, this noise souces is still relative small. The noise gain may have been a reason why the started with the OP27.

3) Quantization noise: even with the small integration cap and thus fast modulation the resolution for the residual charge is limited. This limits the resolution at 1 PLC and even at 10 PLC is still can contribute a little.  This is kind of a limitation of the system with the reading on the fly.
The get at least acceptable resolution it needs the rather fast modulation.

My hardware is a bit similar (e.g. similar switches and integrator configuration) and addresses these 3 points:
The critical OP at the integrator is a OPA141 / OPA145 or OPA 1641 with essentially no noise current. Though slightly higher voltage noise. 
The resistor ratio at the integrator is 1:1 and thus a noise gain of 2 at the integrator.
With the extra rundown before the residual charge reading the quatization noise is much lower, and no need for very fast modulation in the FB that makes jitter more important.

[dietert1]

Your previous remark about strange design decisions of high resolution DMMs also applies to using resistor dividers in the reference section of the ADC. When i see the elaborate time division scheme of the ADC in our Advantest R6581T and then look at how they rely on lots of precision resistor networks, that are known to be bad below 1 ppm or so: "It can't be true". As far as i know other 8.5 designs are as bad in this respect.
I was wondering to what level of precision the internal calibration procedures of those meters can determine and later correct shifts of all those resistors in their resistor networks. I mean there are lots of unknowns and internal calibration will suffer from noise as well. I'd prefer a voltmeter without any precision resistor networks.

Regards, Dieter

[Kleinstein]

The resistors for the small slopes are not that critical, especially not for longer conversion as 10 PLC at a piece. The rundown part, especially from the first slow slope part on is only a relatively small part. So the relative error there can be relatively high before it causes trouble. AFAIR the 3458 only needs the resistor ratios to be accurate to some 1% or so (for 10 PLC mode) . The 1 PLC mode would need about 10 times better ressistors to get the same error level. The slower clock gives another factor. I use 1 PLC also for the highest resolution and aim for something like a 0.02 % stable ratio. However I don't need the resistors to be close to a nominal ratio, as I can measure the slope ratio and use the measured ratio and not a nominal ratio. So far the resistors are reasonable stable and no real need to repeat the measurement very often. A measurement together with normal ACAL may be an option, once a year is likely OK too.

AFAIK the R6581 also includes some measurements of the slope ratio. However I don't know if this is for a seft test only and would just give an error message when the error gets to large. In theory they could also use the measured value to use it as a kind off correction term. One does not absolutely need an integer ratio for the reference levels - it just looks funny and needs a little more math, but it still works with arbitrary ratios.

I was also confuse on how they could make sure that the negative reference is exactly opposite to the positive reference. This is critical with the dual slope ADCs like the ICL7135. The trick with the MS ADCs is that the run-up part is in such a way that the relevant reference is the difference between the positive and negative side. The sum of the two has only very little effect and than mainly as an offset. If one does the math right it does not matter if they are not exactly opposite or not. I have them some 5% off.

Many of the resistor ratios in the R6581 are not that critical and would only effect things like the offset or gain. These 2 are corrected with ACAL.
I don't expect the normal ACAL to correct the slope ratios in the ADC. It would only be the overall ADC gain and resistor ratios in the divider, gain stages and the shunts. The ADC gain in the R6581T is reasonable stable. So the resistors seem to be quite good, despite of the not so spectacular case.

With the measurend ADC slopes and ACAL, I don't need any of the resistor ratios to be long time stable. Some should stay within some 1% to get TC compensation, but that is not a very stringent requirement. They can all be measured and use the measured values. So the resistors (except one for current and ohms) are only relevant short time.

[dietert1]

What do you mean by long term stable? Let's assume one hour after the last ACAL temperature has changed by 1 °C. So the resistors changed, changing the positive and negative ADC gains. By how much depends, but i would assume 1 ppm as a typical gain change.
I mean you just presented the turn-on behavior with an initial drift of 0.6 ppm, if i read the diagram correctly. That's a fantastic result for your DIY meter but undesirable for a 8.5 multimeter, unless we can spend a good fraction of measurement time on ACAL runs, like we spend half the time for Autozero.
Will try and look at the internal calibration data of the R6581T. Maybe one can understand a little bit what they are doing.

Regards, Dieter