Author Topic: DIY high resolution multi-slope converter  (Read 125498 times)

0 Members and 2 Guests are viewing this topic.

Online KleinsteinTopic starter

  • Super Contributor
  • ***
  • Posts: 14071
  • Country: de
Re: DIY high resolution multi-slope converter
« Reply #450 on: October 03, 2021, 06:31:44 pm »
The noise data now look good. The relatively large difference between the mode P,Q and W shows that the switching is a quite important contribution to the noise. The main switching related noise contributions I know are
1) jitter (clock, 74HC74, LV4053)
2) charge injection variations (from my estimates this should not be very large)
3) maybe variations in the supply to the 4053 chip. Normally the 7805 regulator should be good enough for the supply, so I don't think this would be a major part.  This part should scale linear and not with the square root and would thus effect more fast case even more.
   
For the jitter the oscillator itself should be OK (e.g. < 1 ps) and the LV4053 is kind of fixed. For the flip-flop an AC74 or similar faster chip could improve things a little.

From the software side, there could still be a slight improvement, by using a 3 step run-up mode with 0 in between. This could reduce the effect of jitter a little without going to a lower modulation frequency, as the transitions are split in 2 parts and thus some averaging. Though only a small change from the 4 step version with 0, it's not so easy, as that part of the code is quite optimized and convoluted. As a downside the useful range is reduced a little, but with not too fast a modulation this should not be so bad (like 12.5 to 12.2 V max).

The offset part is still an effect I also don't fully understand. Using the 2 conversion AZ cycle the offset should be nearly gone. A large part of the offset seems to be some delayed effect from the reference reading: A reading of a large signal somehow effects the next conversion as well, like a carry over of some 1 ppm. One mechanism to cause such an effect is DA in the integration capacitor. However this part would get smaller with faster modulation. So the DA should be only a small part (maybe 10%) of the delayed effect. With DA I would also no expect the offset / delayed effect to get so much smaller with longer integration. So this looks more like a short time memory for less than 20ms.

A next part to check would be the linearity.

What software is used to generate the histogram plots ?
 

Offline MiDi

  • Frequent Contributor
  • **
  • Posts: 599
  • Country: ua
Re: DIY high resolution multi-slope converter
« Reply #451 on: October 03, 2021, 10:28:15 pm »
A next part to check would be the linearity.

What software is used to generate the histogram plots ?

How would you check linearity?
C||R charged to +-10V with Tau 1/2h?
Constant current source discharging C from +10V to -10V (and vice versa)?
For direct comparison 3458A parallel?
Which mode B or C?

All charts are made with Excel, there is histogram plot awailable and add-in "Analyse-Funktionen", the letter were used for this plots in conjunction with bargraph right manually sized to match both plots.

Attached plots reading own reference for different modes and plc with mode W.
Plc plots look strange with quite large jumps of the mean value.
ADC was warmed up for >2h and minor correction of K1&K2 was done before measurements.
« Last Edit: October 03, 2021, 10:49:06 pm by MiDi »
 

Online KleinsteinTopic starter

  • Super Contributor
  • ***
  • Posts: 14071
  • Country: de
Re: DIY high resolution multi-slope converter
« Reply #452 on: October 04, 2021, 05:37:38 am »
There are different methods to check linearity, that check different aspects.
One is direct comparison to 3458, or a good calibrator if available. This usually checks a moderate number of points, like some 50.

With a less capable external source one can do the classic turn over test and with a dual external source also a sum test - this are usually only few points, testing the soft INL (lower order polynom contributions). These test would use modes A and / or C.

The test with C||R  and mode B is a special for this ADC. It tests more the wiggly part of the INL (more hard INL) exculaing some sources. This test check a relatively large number of points and low noise.  Instead of the R parallel to the cap a current souce would be good (more even coverage of the points).

The test with mode B is relatively simple, the main range of interest is from about -4 V to -0.1 V. With C||R one can as well cover the -10 to -0.1 V as the higher voltage don't take much time. One can have the resistor to a different voltage (e.g. +-15) too, to get a slightly more even covering.

Full linearity testing would need more than 1 test.

The refrence readings show more noise, as there is additional reference noise, especially from the 2.5 to 10 Hz range. So it is normal to have more noise there and the ADC itself is only relatively small part.
 

Offline MiDi

  • Frequent Contributor
  • **
  • Posts: 599
  • Country: ua
Re: DIY high resolution multi-slope converter
« Reply #453 on: October 05, 2021, 06:55:26 am »
How to get the 2 readings in V from logged data in mode B?

Samples taken from preliminary test mode B runup W:
Code: [Select]
157945.754 153131.211 4814.537    -33 591 412 352 768 694 695 1221 524 340 867 723 690
 157945.759 153131.240 4814.533    -15 591 412 352 768 715 719 1221 524 340 867 725 710
 157945.762 153131.196 4814.544    -43 591 412 352 768 715 721 1221 524 340 867 753 710
 157945.738 153131.206 4814.538     85 591 412 352 768 758 749 1221 528 344 867 668 753
 157945.735 153131.191 4814.537    -46 591 412 352 768 676 665 1221 524 340 867 718 672
 157945.735 153131.179 4814.550     68 591 412 352 768 727 716 1221 528 344 867 655 723
 157945.713 153131.175 4814.536    -56 591 412 352 768 677 652 1221 524 340 867 728 672
 157945.727 153131.202 4814.539     83 591 412 352 768 740 724 1221 528 344 867 651 734
 157945.745 153131.158 4814.564    -67 591 412 352 768 652 647 1221 524 340 867 715 648
 157945.723 153131.160 4814.564     56 591 412 352 768 731 712 1221 528 344 867 671 727
 157945.710 153131.174 4814.543    -57 591 412 352 768 695 668 1221 524 340 867 747 690

Did you use interpolation for mode B to match readings in time for the different runup versions?
Otherwise the differences between two readings depend significant on slope of input voltage.
« Last Edit: October 05, 2021, 06:58:50 am by MiDi »
 

Online KleinsteinTopic starter

  • Super Contributor
  • ***
  • Posts: 14071
  • Country: de
Re: DIY high resolution multi-slope converter
« Reply #454 on: October 05, 2021, 08:25:03 am »
In the 2 readings loop there is averaging in time used for the 2nd reading. For the normal AZ readings (mode A) this means using the zero reading before and after the input and a slightly reduced noise. This suppresses the effect of the slope relatively good. Otherwise the rate of change is indeed a major problem. The data in the file are the first reading (selected run-up mode) and the 2nd reading (mode Q).
The 3rd column is the difference and thus the relevant result. The numbers are still in internal units, that are 1 clock cycle of the positive reference. So they still need to be scales with the scale factor (some 56 µV/unit for a 12 MHz clock).

The calculation only includes an approximate zero point, as for the normal modes there is always a difference and an offset does not matter. This leads to some offset to the difference of 2 run-up cases. So it is normal that the numbers are not so close to zero. Doing the full math to get the same zero point for both modes is tricky (needs more constants to describe the run-up versions). I use this with my ARM version and than use the difference of 2 run-up modes to get the slow slope ratio. It is not as exact and fast, but good enough.

The difference test works best with run-up modes that use the same modulation frequency (e.g. R,V,S,U). With a different modulation frequency there is some additional drift from changes in the charge injection (e.g if the 5 V supply drifts).
 

Offline MiDi

  • Frequent Contributor
  • **
  • Posts: 599
  • Country: ua
Re: DIY high resolution multi-slope converter
« Reply #455 on: October 05, 2021, 04:49:10 pm »
Result of INL test with mode B and runup V (vs Q).
Input1 with 33mF and 330k to -15V for discharge 6.5 .. -0.7V.

Scale of raw dU (3rd row in raw data):
Code: [Select]
dU = RAWdU * 56µV + 840504µV
« Last Edit: October 05, 2021, 05:15:47 pm by MiDi »
 

Online KleinsteinTopic starter

  • Super Contributor
  • ***
  • Posts: 14071
  • Country: de
Re: DIY high resolution multi-slope converter
« Reply #456 on: October 05, 2021, 05:18:40 pm »
The test resuslt looks quite good. The curve is quite linear, with most of the time less than 1 µV deviation from a straigth line. The slope kind of reprensts an effect from the no perfect settling in the short pulses. There is not much slope, especially for the integrator with the relatively slow OPA145.
There is a little "resonance" like structure near -0.7 V and 3 V. This are likely the regions close to stable simple run-up patterns.
So things look good and there is a good chance to get low INL. (e.g. 0.1 ppm FS range for the hard INL part).
The other polarity could complete the picture and allow a more meaningful line to subtract.

My AVR based version was not that good, especially not the original PCB.

With 2 resistors arrays in series the u³ part is expected to be good as well (should give about a factor 2.8 less thermal effect). There is still some randomness in how good the resistors are matched.

The u² part (measured from the turn over error) is to a large parte depending on the LV4053 on resistance - It should normally be OK.

I did a crude  test on the linearity of my ARM based version, including the front end: The amplifier gain and divider ratio measure for a postive and negative internal test voltage are reasonable close (some 0.6 ppm off).
 

Offline MiDi

  • Frequent Contributor
  • **
  • Posts: 599
  • Country: ua
Re: DIY high resolution multi-slope converter
« Reply #457 on: October 05, 2021, 10:19:20 pm »
The test resuslt looks quite good. The curve is quite linear, with most of the time less than 1 µV deviation from a straigth line. The slope kind of reprensts an effect from the no perfect settling in the short pulses. There is not much slope, especially for the integrator with the relatively slow OPA145.
There is a little "resonance" like structure near -0.7 V and 3 V. This are likely the regions close to stable simple run-up patterns.
So things look good and there is a good chance to get low INL. (e.g. 0.1 ppm FS range for the hard INL part).
The other polarity could complete the picture and allow a more meaningful line to subtract.

Resonance @-0.7V is of diode with lots of datapoints in there (~1/3), reduced them in the following plots.
Resonance @-0.5V is real and there in both slopes.

Result of INL test with mode B and runup V (vs Q).
Input1 with 33mF and 330k to +15V for discharge -9 .. +0.2V (blue) and to -15V for 6.5 .. -0.7V (orange).

Scale of raw dU (3rd row in raw data):
Code: [Select]
dU = RAWdU * 56µV + 840504µV

« Last Edit: October 05, 2021, 10:58:42 pm by MiDi »
 
The following users thanked this post: ch_scr

Online KleinsteinTopic starter

  • Super Contributor
  • ***
  • Posts: 14071
  • Country: de
Re: DIY high resolution multi-slope converter
« Reply #458 on: October 06, 2021, 08:08:33 am »
The center part looks good.

The part below -7 V however is unusual. I have not seen a large change in this range, in my measurements that range was OK and only some effect very close to the end of range (with ru-version P this can be a bit below 10 V as with faster modulation the useful range gets a little smaller).
I don't expect the integrator voltage to reach extra high values - the 2.2 nF integration cap should be well large enough and it also support the slower modulation. The more gradual bend at some -7 V is also a bit different from what I normally saw (jumps, "resonances" and more piecewise linear).

If the circuit is still with the "original" R10 = 6.8 K the settling of the integrator is still quite slow. The slower OPA145 would more like a smaller value for R10 (e.g. 4.7 K or 3.3 K) to speed up the settling. With warm up the speed of the OPA145 may change, and this can than effect the settling and indirectly the ADC gain a little, especially for the faster runup mode Q. So the bend may be a warm up effect - though ususally this should be smaller for 2 RU modes with the same frequency.  The settling has more effect on the modes with higher frequency and shorter pulses - so the later used case (e.g. V or W) are likely the better ones in the comparison. It is mainly the DA related error that gets worse with slower modulation.

One could test temperature effect with a measurement of the ADC gain during warm up or cool down. This is an interesting point anyway to see how stable the gain is. One can use the 3 reading cycle C and chose the temperature measurement diode as input source. So the readings are zero, internal ref and the temperature. One gets the ADC gain and temperature in a single file. Normally the main part of the change in ADC gain is from the resistor relative TC, but there can also be a little contribution from incomplete settling. The settling part would give a different temperature dependence for different RU mode (e.g. P and W), while the resistor part should be the same.
 

Offline MiDi

  • Frequent Contributor
  • **
  • Posts: 599
  • Country: ua
Re: DIY high resolution multi-slope converter
« Reply #459 on: October 07, 2021, 07:23:33 pm »
Measurements of INL with slope on input reversed from 0 ... +-10V.
Indeed the bend in the previous measurement is due to warm up (lid opened for short time), the slope is nearly linear.
The small downward tendence >10V keeps going, it was cropped due to range limit for one runup version.

If the circuit is still with the "original" R10 = 6.8 K the settling of the integrator is still quite slow. The slower OPA145 would more like a smaller value for R10 (e.g. 4.7 K or 3.3 K) to speed up the settling. With warm up the speed of the OPA145 may change, and this can than effect the settling and indirectly the ADC gain a little, especially for the faster runup mode Q. So the bend may be a warm up effect - though ususally this should be smaller for 2 RU modes with the same frequency.  The settling has more effect on the modes with higher frequency and shorter pulses - so the later used case (e.g. V or W) are likely the better ones in the comparison. It is mainly the DA related error that gets worse with slower modulation.


R10 is 6.8k, which op amp and value for R10 do you use in your circuits?
« Last Edit: October 07, 2021, 08:01:02 pm by MiDi »
 
The following users thanked this post: TiN, ch_scr

Online KleinsteinTopic starter

  • Super Contributor
  • ***
  • Posts: 14071
  • Country: de
Re: DIY high resolution multi-slope converter
« Reply #460 on: October 07, 2021, 08:12:48 pm »
With my ADC boards I have OPA1641 and OPA141. The resistors are 4.99 K and 6.8 K one the other board. The 4.99 K are a bit on the low side ( more ringing).
I had a OPA145 there before, but had to exchange it due to defect (some stupid error from my side - I don't remember the details).

The OPA145 is slower and could use something like 3.3 or 3.9 K.  So a 2nd 6.8 K ( or 10 K) in parallel (on top) would be an option. One could look at the testpoint at the OPA145 output to see the settling. There should be a kind of square wave like signal. In the current form likely more overdamped and a bit slow step. A smaller resistor should speed up the settling. Some ringing is OK, but it should not be very much. With a reduced resistor the OPA145 should be about as good as the OPA141, less divider can make up for the lower GBW.

The "resonance" near -0.6 V looks somewhat familiar. This should be the point of 50% H/L in the run-up and is one of the most difficult points. The excursion of +-1 µV is not ideal, but also not so bad.  I see 2 main suspects to cause such an error: one is DA, as the average integrator voltage changes quite a bit at that point. Another possible mechanism is some electric interference from the µC, HC74 or 4053 effecting the oscillator. At least with my AVR boards this was the likely main mechanism. Changing the decoupling at the oscillator had some effect, though this is not the only path.

One could try changing the modulation frequency (xdel parameter in the ASM program and pascal program). DA caused errors get larger with a lower frequency. Coupling type errors are expected to get smaller with a lower frequency.
 

Online KleinsteinTopic starter

  • Super Contributor
  • ***
  • Posts: 14071
  • Country: de
Re: DIY high resolution multi-slope converter
« Reply #461 on: October 09, 2021, 05:16:10 pm »
I did a little more INL testing on the ARM based ADC / DVM. The turn over and sum of 2 voltages test got a little automated. The DVM switches a sequence of 4 settings with 2 high side inputs and 2 low side inputs, to get all 4 combination in a sequence (16 x 16 PLC readings each). For most of the points I still looked at the data by hand, to find phases with low noise. The problem is especially popcorn noise from the references (external and in ternal LM399 based). There are low noise phases and higher noise phases. Brute force averaging needs quite some time to get to the level of quite phases. May have to teach the computer to see quite phases and do a smarter average.

For the more long range linearity (soft INL) I now have 3 tests:
1) the classic turn over test with the same external voltage read positive and negative. The sequence includes 2 additional zeros.
2) read the sum of 2 voltages that make up some 9.4 V from my reference. The 2 voltages are derived from a single LM399 with a amplifier, divider and buffer as used before.
3) use an external voltage source and read the same voltage in a classical AZ mode (0 and the voltage) and in my differential mode, where the ADC reads -1/2 U and + 1/2 U. The 2 voltages are not exactly opposite, but the difference should be accurate as only the ground shifts. So this is a little like the case 2, but with one voltage measured negative and fixed at half the voltage. For the DVM this is measuring the same voltage in the 10 V and 20 V range.

Attached are the results for the 3 tests.
The result of the turn over test is odd: it is more like linear, while the expected form is quadratic. I currently have no real idea what mechanism to give a slightly different gain for the positive and negative side. The main expected effect from the nonlinear on-resistance of the CMOS switch is square law.

The result for the sum of 2 voltages does not looks so bad, especially for the negative side. The positive side shows a little more error, but still not too bad with some 4.5 µV in the center. With the scattering it is a bit hard to tell if the curve follows the expected parabola form for the positive side - it at least looks a bit like it.
The test with the 10 and 20 V range gives some kind of v³ contribution, a bit like expected for the self heating of the resistors at the integrator input. The difference gets quite large - I had hoped for better performance. The difference is also larger than one would expect from the INL seen in the test with half the voltage (but with the same sign and with a different sequence).

The ACAL procedure also gives a slight hint on linearity, though this also includes the amplifier and possible nonlinear effects at the amplifier, especially the feedback resistors. The results for a positive and negative test voltage are reasonably close (-0.2 ppm , -1.8 ppm and -0.6 ppm for the positive side for gain 7, gain 100/ gain 7.4 and the divider), but still a tendency to have lower results for the positive side.
 

Online KleinsteinTopic starter

  • Super Contributor
  • ***
  • Posts: 14071
  • Country: de
Re: DIY high resolution multi-slope converter
« Reply #462 on: October 11, 2021, 04:23:54 pm »
A short addition to the last measurements:
The difference between the 10 V range and 20 V range is at least partially due to the amplifier / buffer settling, when switching between the positive and negative side.  With more delay (e.g. 300 µs instead of 70 µs) the diffenrence gets smaller (about half), though not all the way gone. More delay does not fix the problem however.

The DG408 multiplexer gives quite some current spike at the inputs, when switching between different voltages. Not sure of this is the amplifier or the CMOS switch, but it is strong enough to be visible on OP outputs used to drive the inputs.
 

Offline jbb

  • Super Contributor
  • ***
  • Posts: 1128
  • Country: nz
Re: DIY high resolution multi-slope converter
« Reply #463 on: October 12, 2021, 02:14:36 am »
The DG408 multiplexer gives quite some current spike at the inputs, when switching between different voltages. Not sure of this is the amplifier or the CMOS switch…

As a diagnostic, could you sneak a large-ish resistor in between the DG408 and the amplifier input? It might let you separate the two candidates (DG408 spike wouldn’t change much, opamp spike might be stretched or removed).
 

Online KleinsteinTopic starter

  • Super Contributor
  • ***
  • Posts: 14071
  • Country: de
Re: DIY high resolution multi-slope converter
« Reply #464 on: October 15, 2021, 05:25:12 pm »
I did try it with a larger resistor (47 K) at the input side with not much change. With a next HW change I will also try a little more resistance behind the MUX.

The more interesting point was a measurement of the turn over error with a battery 9 V instead of the mains powered reference. With a little faster (8 x 16 PLC) switching between the 4 steps and more averaging this also works with the slightly drifting battery. With the battery the turn over error looks different:  only some -6.5 µV (instead of some -11  µV) in the classic mode and  0+-1 µV for the differential mode. Essentially no turn over error is expected for the differential mode.  So chances are the INL tests with the external source were effected by some EMI (either direction) and are not really refecting the nonlinearity.
 

Online KleinsteinTopic starter

  • Super Contributor
  • ***
  • Posts: 14071
  • Country: de
Re: DIY high resolution multi-slope converter
« Reply #465 on: October 30, 2021, 08:53:51 am »
A small update:

The INL testing got slowed down by some likely EMI related problems. Especially if the debugger (ST-Link) is still connected there seems to be some EMI effect. This makes the INL test with my external reference (mains powered) somewhat unreliable. I tried some INL tests with just a chain of 1.5 V batteries. This looks a little better, but there is still a possible catch: the input switching in one case causes a current spike, that may effect the batteries. So the drift on the batteries is not necessary linear in time.
The turn over error curve with the batteries looks more like the expected square law curve and not as linear as the older measurements. However there is still the point at some 9.7 V (6 new alkaline cells). I have checked that point, the measurement is repeatable. At least the more normal turn over error is not really my concern, as the 20 V range suppresses this INL part quite well. There is very little turn over error in the 20 V range.

The sum test looks similar to the old results with some 4-5 µV of error.

For the difference test with 2 run-up modes shown earlier, the 2 cases to compare may have been a bit too similar and the result thus a bit too optimistic. With more different run-up modes the difference looks a little worse, but still not too bad. The plot in the attachment shows 2 cases with different modulation frequency ( 23.5 and 61.5 kHz). The run-up parts are a bit more different and especially with some offset relative to each other. The slower modulation curve looks a little better, but not much.
The idea of the comparison at different modulation frequencies is that errors due to DA get smaller with a faster modulation. Errors from switching related interference should get larger with faster modulation. The curves look different, but no clear pointing to one culprit. It looks more like a combination of both types of error: The more shorter range periodic like part (e.g. at abound -300 mV and -1.5 V) seem to be stronger with the slow modulation (this would point towards DA).

The white noise from the ADC is at some 350 nV for the 1 PLC conversions and thus some 80 nV_RMS for the data points that are the average over 20 conversions. The averaging is a balance between noise and loosing very local details of the curve. So some 500 nV_pp is the expected scattering from noise.
Different from the AVR version the noise does not change much with the modulation frequency. So clock jitter does not seem to be a problem. Less jitter also explains the lower noise.

The more step and piece-wise linear part is worse with the green curve and may be more due to switching effects (like coupling to the clock). Still not the hoped for clear result. There is no direct comparison at the some applied voltage, as with at different frequency the features also move to different voltages. The only fixed point is the center of the range with a symmetric modulation at some -310 mV.

I did a comparison with the same 2 run_up modes (61.5 kHz), but some added capacitance at 2 places: extra capacitance at the AC74 flip flop did not change much, still essentially the same curve.  An extra cap at the oscillator supply does improve things a little, though it does not effect the more periodeic part. So it looks similar to the  AVR version that the clock is somewhat part of the problem. Supply filtering at the oscillator really seems to matter.
 

Offline dietert1

  • Super Contributor
  • ***
  • Posts: 2018
  • Country: br
    • CADT Homepage
Re: DIY high resolution multi-slope converter
« Reply #466 on: October 30, 2021, 10:34:14 am »
Running the oscillator with a separate voltage regulator might improve isolation from other digital states. At low frequencies this is difficult to get with a filter.

Regards, Dieter
 

Online KleinsteinTopic starter

  • Super Contributor
  • ***
  • Posts: 14071
  • Country: de
Re: DIY high resolution multi-slope converter
« Reply #467 on: October 30, 2021, 01:19:30 pm »
An extra regulator is an option for a new PCB. With the current PCB additional filtering is simpler. I am not much worried about the really low frequencies, I am more worried about the harmonics of the clock.

I am also not so much convinced that the problem is directly with coupling via the supply. It could as well be coupling via the oscillator output and vaiations in the loading. Changes in the supply are than more a secondary effect.

I have currently running a new variation, with the extra cap still in place and a larger resistor (51 ohms instead of 14.7 ohms)  in the line between the osciallator and µC. So far the result is confusing: nearly back to the case without the capacitor.

 

Offline julian1

  • Frequent Contributor
  • **
  • Posts: 721
  • Country: au
Re: DIY high resolution multi-slope converter
« Reply #468 on: October 30, 2021, 09:33:51 pm »
Would it make sense to buffer the oscillator? I noticed the jitter specs on some canned cmos oscillators appear sensitive to the max capacitive loading (50pF). 

I think I calculated that the stray capacitance from traces and the 2 input cmos gates (mcu/fpga gpio and synchronization flip-flop) would be around that level.
For my simple prototype, I added an optional buffer/inverter after the oscillator, but then avoided it on the theory that introducing extra switch propagation would be more likely to upset timing.

Perhaps it would be possible to check the harmonic content (and possible interference) using an independent instrument - a spectrum analyzer/vna?


 

Online KleinsteinTopic starter

  • Super Contributor
  • ***
  • Posts: 14071
  • Country: de
Re: DIY high resolution multi-slope converter
« Reply #469 on: October 30, 2021, 10:25:23 pm »
Bufferig the osciallator is already there for the flip-flops. I have it planed for the µC too, but need to order a non inverting buffer. With 2 inverting buffers the phase relation is just wrong (violates setup and hold times and even seem to get random jumps, so really at the edge) with the ARM. The extra jitter to the flip-flops seems to be not an issue and jitter towards the µC would be no problem. There is currently not much trace : a 0603 size 14.7 Ohms resistor to both sides. U13 is currently replaced by a wire. Attached is the layout around the clock. U14 is the inverting buffer (NC7SZ14 , SOT 23-5 ). 

I don't have a spectrum analyser and my scope is very much on the slow side - just OK to see the approximate phase and realize that it needs 1 inverter and 1 non inverting buffer. Anyway even just the probe can make some difference and the parts are quite small. I don't see how a VNA would help, at least not a simple 1 channel version. A VNA may help with checking the supply filtering, but still a bit tricky.
 

Offline dietert1

  • Super Contributor
  • ***
  • Posts: 2018
  • Country: br
    • CADT Homepage
Re: DIY high resolution multi-slope converter
« Reply #470 on: October 31, 2021, 06:40:28 am »
As i have a R6581T open here: Instead of R25 it has two 47 uH inductors with a 10 uF electrolytic cap to Gnd in between and close to the oscillator there is another tantalum cap with a small MLCC cap in parallel. The circuit is arranged such that the caps are used in a "feedthrough" mode, while in your case the oscillator is on the trace to the filter cap. They use a metal can oscillator and the can is grounded, too.

Regards, Dieter
 

Online KleinsteinTopic starter

  • Super Contributor
  • ***
  • Posts: 14071
  • Country: de
Re: DIY high resolution multi-slope converter
« Reply #471 on: October 31, 2021, 07:17:05 am »
So far I had not that good experience with inductors / ferrites in the supplies. I tried with the AVR version and finally went back to low value resistors.
47 µH are quite a large inductor - maybe that helps. So maybe a large inductor is indeed an option.
The small boxed oscillator also has the case (at least the upper half) grounded.
The "feed-through" layout for the capacitor would indeed be better. 


For the buffer to the µC I just realized that using the inverter and typ of the signal from after the other inverter could be an option. So remove R29 and have a bodge wire to the inverted clock instead.
 

Offline Tazz

  • Contributor
  • Posts: 25
  • Country: fr
Re: DIY high resolution multi-slope converter
« Reply #472 on: October 31, 2021, 09:55:16 am »
Perharps overkill but why not a LTC6957 family buffer for the clock fan-out ?
 

Online KleinsteinTopic starter

  • Super Contributor
  • ***
  • Posts: 14071
  • Country: de
Re: DIY high resolution multi-slope converter
« Reply #473 on: October 31, 2021, 02:43:06 pm »
The LT part is indeed overkill. A lower end clock buffer like LMK1C1102 may be an option for a new board. Those fast buffers tend to be tiny cases, not very friendly for hand soldering.
Normally standard logic (like LVC family) buffers / inverters should be good enough.

I still hope to get some improvement for the existing board. After all the error seen is already relatively small, 1 µV is only 0.1 ppm of the 10 V range.

With very little change in the last few tries, I start to think that there may be some other mechnanism behind the features. It was mainly that 1 case that was different.
 

Online KleinsteinTopic starter

  • Super Contributor
  • ***
  • Posts: 14071
  • Country: de
Re: DIY high resolution multi-slope converter
« Reply #474 on: November 02, 2021, 04:08:21 pm »
After not getting much change from the clock part, I did 2 different test to see the effect of integrator speed and dielectric absorption (DA):

For the test of integrator speed the divider between the 2 OPs in the integrator was changed. From the original 10K/1K to some 8.3 K/1K by adding 47K parallel to the 10 K. This speeds up the integrator settling somewhat - still a relatively conservative ratio.  The result is quite some change to the overall slope, but no real change to the nonlinear details. This is not such a surprise, as the number of short pulses is about linear. As long as the effect of incomplete settling is the same for each pulse, one would get a small change in the gain and not much effect on the INL, as the INL part goes not sum up and the effect of single pulse is small. The measured curve makes it unlikely that the integrator settling is reason of the INL error.

With a 1 nF film cap with high DA in parallel to the 2.2 nF C0G cap of the integrator i get an intentionally worse DA. The attached curves shows the expected larger difference. This is especially true for the more shorter period part seen in the detail part.
The short range periodic part is thus confirmed to be from DA. The about constant steps are also not a surprise: the DA error for both measurements is expected to change about in a saw tooth like shape, with a relatively similar slope and frequency. for the difference the slope part than compensated and one mainly get the steps up or down depending on the phase.  With the intentionally poor cap the amplitude increased some 20 fold. This would correspond to DA in the 1 nF cap to be about 60 times higher than in the 2.2 nF cap, which is about the expected ratio for Mylar and a good C0G cap.
To my surprise the more longer range part is also getting larger. So some of the longer range error may also be due to DA. This is a bit surprising as this longer range part more like looks to go up with frequency and not down, as is expected for an DA effect.

To make the ADC work with the larger capacitor I had to do some changes to the program (fix a bug that effected some cases and somehow did not effect the original configuration). This may have also changed the general shape a little. The larger capacitance by itself could also make a small difference.
 
The following users thanked this post: SilverSolder, ch_scr


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf