Electronics > Metrology

DIY high resolution multi-slope converter

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Kleinstein:
Here in the forum I already showed some ideas and parts of an µC controlled multi-slope ADC.
https://www.eevblog.com/forum/projects/multislope-design/
So here I finally show my multi-slope ADC version as a "complete" project in a separate thread. The hardware side is essentially finished, with still a few resistor/capacitor values to tweak. The board is a little more than just the pure ADC. It also includes the reference (LM399 or LM329), a buffer amplifier and MUX for the input. So it is a limited (only 10 V range with little protection) voltmeter without the display part. Currently a PC is used for display and saving the data. Power is from a 2x18 V (2x15V is likely better) transformer. The 5 V part could use a lower voltage (currently just series resistors).

The software is currently supporting the basic functions including the MUX and a few debugging function. The ADC part sends out raw results via optically isolated UART and the ground referenced side (PC) is doing the conversion to the final result.

The hardware side is relatively simple, with an µC (Atmel Mega48) for control, xx4053 switches and 7 OPs. For the performance mainly 1 OP and 6(7) of the resistors are important. However even with simple parts (e.g. TL072 OPs for the integrator and 100 ppm/K resistors) the circuit works surprisingly well. The OPs given in the plan are the ones currently used.

The circuit shown is a slightly simplified version of the test board - leaving out alternative and optional parts and the ISP connector. I know the plan is not easy to read - sorry for that.

The optional extras on the board are other resistor / reference foot prints, alternative canned oscillator, a few more caps, a LM393 comparator to detect overflow, an input buffer before the MUX for 1 channel, a simple current source and an optional buffer for the ground return current at the ADC.

From the hardware side the ADC is a little similar to the HP 34401:
- switching via xx4053 at the integrator input. Here using 74LV4053 as a slight upgrade.
- a 2 OP integrator (essentially standard), but with more modern OPs.
- using a µC for the auxiliary ADC, though a more modern one with integrated memory.
- using continuous integration instead of a reset of the integrator. Instead of starting from zero the initial and final charge is read by the µC internal ADC.

Different from the 34401, there is no ASIC and the control is directly from the µC. The main difference is that my version also includes a more classical rundown phase and this way reaches a higher resolution and in part due to the more modern OPs a lower noise. So the ADC is in between the classical multi-slope ADC like used in the Keithley 2000 and the continuous integrating variation of the 34401.

The software side is a little tricky, as the program uses the program speed for timing and thus is written in ASM with careful check for the timing. However it is only the actual conversions that are so time critical. So the time critical parts are essentially ready.
Besides the actual ADC conversions, quite some code is there for 2 internal calibration measurements. One is to measure the ratio of the reference currents. The other is to measure the scale of the µC internal ADC relative to the reference currents. With measured ratios there is no need for special and accurate resistor ratios, except 3 reasonable (e.g. 1%) equal resistors for the integrator input.

The PC side program is currently written in Turbo Pascal. The software assumes a build in RS232. So for modern PCs it would need to be rewritten, e.g. to support an USB to UART bridge. The functions are not that complicated, and even a simple µC like the AVR should be able to do the job (though it would help to have a 2nd UART or USB interface).

Despite the simple hardware (about as simple as a good multi-slope ADC can be) the noise of the ADC itself is quite low. Currently I get a little below 1 µV RMS for 1 PLC auto zero readings, good enough for 7 digit resolution and often more limited by the reference.

Compared to a normal DMM the input MUX (DG408, optional DG508) has quite some leakage currents and there is not much protection. A practical voltmeter would need either a lower leakage mux, an amplifier instead of the buffer and more protection. An alternative extension is an additional amplifier (AZ) and protection stage in front of the board - this is more like the intended extension of the board. The ISP connector could also be used to control such a front end.

So far I have only done a partial linearity test. The result looks promising, with low local linearity errors. However the test does not include all INL sources (especially thermal effects) and is not sensitive to a more smooth background, e.g. a square or cubic contribution. A full INL test is still open.

So far I don't see a reason why linearity should be much worse than the 34401, except for the resistors currently used.
So the choice of resistors can be a topic if really good linearity and stable gain is wanted. The test data shown below are with not so good resistor matching, leading to a gain drift of some 12 ppm/K. I consider this bad luck for 15 ppm/K class resistors - it was better before, with simpler resistors.
 
The current board has a few bodges, but not that many.
While basically running there are still a few parts unfinished or open to improvements:
- better decoupling / ground routing (especially better EMI tolerance)
- optional parts on the board (e.g. comparator for overflow )
- speedup of the rundown from currently some 200 µs to maybe some 60 µs.
- use better resistors for low INL (U³ part) and gain drift
- faster conversion mode like 1 ms (needs fast UART interface, maybe shorter data format)
- accurate adjustment of integration time for better hum suppression
- control for external front-end
- PC software: change to C (with a µC) or Python (for the PC or Raspberry)

The attached files are:
1) Circuit diagram (simplified)
2) ASM code for the AVR + Pascal code for the PC (ziped)
3) Plot of data: relative size of reference reading versus diode voltage as a temperature sensor.
The data are dots with 20 ms integration each, during warm-up for some 15 minutes. 
4) Head of sample data file (with some added comments)

SilverSolder:

Awesome project.

How do you perform an INL test?

Kleinstein:
The INL test is a difficult part. For the final test I would have to send a unit to someone with suitable high end gear (calibrator and 8 digit DMM).

The tests I can do are in 2 steps. The first part is testing for possible fine wiggles in the INL curve: I have programmed the ADC to use 2 different versions of the run-up, by using a different modulation frequency. This shifts most of the short range INL errors to a different voltage level. Than a slowly changing voltage is measured with both modes. Ideally both versions should give the same result. Due to charge injection from the switches and similar effects, there is a small difference, that should be constant. So the different of the 2 modes is a good and quite sensitive test for those possible fine wiggles in the INL curve.  I did quite a few such test, especially with an older version that had a not so good run-up part and here the test did show some problems over a rather local range. The newer run-up version essentially solved that problem.
This test is a little unusual and requires the direct control of the ADC, but it is fast and low noise, so it can resolve even small errors (e.g. < 0.1 ppm range) without special gear. As both readings are with the same reference, it is not sensitive to reference noise and drift.  I still have to repeat this test on the new version with a little more resolution / averaging and over a larger range.
A crude first test of this type could also be done by just looking at the discharge curve of a large cap: while not always perfectly following an exponential, it should be reasonably smooth, and local INL errors or DNL errors would show up as deviations from a smooth curve. Attached is such a measurement: the horizontal axis is the voltage with some -400 mV offset and 42 µV steps (ADC internal units = clock cycles worth of the negative reference), the vertical scale is µV.  These are raw data in an non AZ mode. The voltage range  (around 1:1 PMW) is where the older run-up version showed errors in the 50 µV range. In this range also DA related errors would show up, as the average integrator voltage changes quite a bit. So DA is not a significant issue here. :-+

The second group of tests to do is still open. The main INL part to look for is the smooth long range part, like U² and U³ contributions. A first test is the so called turn over test, using an external isolated reference and measure this with both polarities. This kind of tests the even powers. For the odd powers one would need to add an offset, or use more test points and measure differences, checking that the sum of 2 voltages is measured right.  This test requires stable and low noise reference for both the ADC board and the external ones and also thermal EMF can cause quite some extra errors. So while only a few test points (e.g. 10) are needed, this test is not easy and fast. Here a high end calibrator would really help.

Before doing the INL test I have to fix the drift problem - so replace the resistor(s). It looks like one is bad (too high TC).

jbb:
I've been following the other thread, and I can see that a lot of work has gone into this.  It's very cool to think that we could build our own equipment to this level of performance, especially if we have a task which requires extreme precision but not the full gamut of a high performance multimeter.

Do you think you could make a brief comment about which parts of the circuit do what?

Kleinstein:
A few comments on the circuit parts:

The upper left corner part (OPs IC8,IC9) of the circuit is the reference part, with amplification to some 14 V and -13.3 V. The circuit has not much special. Different from many DMMs, there is a little filtering for the reference, as higher frequency noise (some 50 kHz) can contribute to the noise. It is a little unusual that the voltages are not symmetric - both references together are used as an effective 0.7 V level for a smaller slope rundown step.

The power supply part is just normal +-15 V and +5 V from linear regulators, for dual 15-18 V / 10 V AC (mains or maybe switched mode).


The OPs IC11 and IC2 form a 2 OP integrator, to get a really low voltage at the input.  The 2 OP integrator is pretty much standard.
Here IC11 (OPA1641 used, could be OPA145 later) is responsible for the low frequencies (up to some 1 MHz). This OP is the one that needs to be low noise, as the noise of this OP is about amplified by a factor of 2.
The OP IC2 is responsible for the higher frequencies and less critical, it just should be fast. C17 and R20 are there to help with settling of the integrator - the suitable values depend on the OPs used and maybe the parasitic capacitance. C37 is there in commercial circuits - I did not find it helpful, so not populated, but I kept it there just in case. It may be needed if IC11 is a BJT based OP. R10/R11 are effectively reducing the speed of IC11, the right value depends on the OPs used.

The supply for the integrator is isolated via R31/R32, so that at least the AC current flows back mainly through C6 and C14 and thus a controlled path. As an alternative to C6/C14 I have tested a ground buffer (a little like used in the Keithley 2002), that is also powered from the same supply island - but it did not give much difference. So c6 / c14 are just the simpler way. 

The 4053 switch, very much like in the 34401 switches the currents to the integrator. They go either to ground through R35 (ferrite bead) or the integrator. Different from the 34401 I have separate control for the 3 switches and make use of it. As the input current is send to ground or a virtual ground at the integrator, there is no problem to use a low voltage (5 V) CMOS switch even with +-14 V of input voltage and reference. The switches work essentially at zero level. The resistors R1,R2,R3 are the ones I had bad luck with (R1, which is the most critical one has to high TC). Self heating of R1 can be one of the major factors effecting the INL. So in the final version this would need to be a good one (e.g. wire wound or foil or resistor array with R2,R3).

An amplifier like IC4 (NE5534) is called slope amplifier and usually has only 2 diodes (no D10) in the feedback. It amplifies the integrator output voltage around zero and has the diodes for clamping the voltage. The output of IC4 is between some -0.6 V and + 1.2 V. D10 and R23 result in a relatively linear range from about 0 to + 500 mV.
The output of IC4  goes to the µC internal comparator with R40 and R34 for level shifting. This is the "zero-crossing" comparator used for run-up and run-down.
R15 sets the actual trigger level for the comparator.

The OP IC13B gives another amplification of about -20 and has an output limited to 0-5 V that goes to the µC internal ADC.
As the µC internal ADC is slow, it is used with the integrator in stop mode. So IC13B does not have to be very fast - the limited BW may even help.

IC12 with the transistors is an buffer amplifier with bootstrapped supply (currently the bootstrapping part is not yet used). The circuit should work this way, but it might be better to change the lower side of D9 a little. The bootstrapping helps to get very good linearity from a buffer, as the OP sees an essentially constant common mode voltage. The OPA145 was chosen here because it is low noise, reasonable fast and still low current consumption. The heat from the buffer amplifier is a possible source of INL.

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