DIY high resolution multi-slope converter

[Rerouter]

https://ez.analog.com/switches_multiplexers/f/q-a/77203/dg408-address-switching

Apparently the digital IO can also cause some coupling. It may be required to fit some inline resistors in the address lines near the avr to reduce the slew rate.

[Rerouter]

for D10, exactly how does its linearity effect the measurement, and could this be worked around by using a NPN transistor with Base and collector tied? (Routing out, but not so fond of possible injections into the signal path)

As the purpose of the slope amplifier is not making much sense to me? could the same not be accomplished with a gain limited comparator and an output divider?

Edit: could R23 not be put in parallel with D2?

[iMo]

As the purpose of the slope amplifier is not making much sense to me?

The value of the feedback resistor in your schematics is 5k - it should be 100k (or something like that).

The slope amp works for input voltages < +/-0.6V as an amplifier with gain=20, for larger as limiter (it is a "log" amp) thus the output voltage will be always < +/-0.6V. 
That works for 2 anti-parallel diodes in the feedback.

It simply amplifies the voltage transition around zero (at the integrator's output) such there is none "slowish" voltage at the input of the comparator, generating mess.

Enclosed you may find the "Multislope simulation" I did in past in the Multislope thread, you may play with the elements (it includes the composite integrator and the slope amplifier). Not exactly Kleinstein's version, however.

[Kleinstein]

for D10, exactly how does its linearity effect the measurement, and could this be worked around by using a NPN transistor with Base and collector tied? (Routing out, but not so fond of possible injections into the signal path)

As the purpose of the slope amplifier is not making much sense to me? could the same not be accomplished with a gain limited comparator and an output divider?

Edit: could R23 not be put in parallel with D2?

The normal purpose of the slope amplifier is to help the comparator, as a kind of first amplification before the comparator. This can help with the speed, especially if very small slopes are used. The NE5534 (a common choice for this) as defined low noise and reasonable good DC stability compared to the usual comparators (e.g. LM311 or similar).

In my circuit the slope amplifier also serves to limit the amplitude to some -0.7 V to +1.4 V. This helps as the following amplifier is powered from 5 V. As it is not only used for the comparator, but also send to the ADC, it should be linear at least over a range of some 400 mV or so. Due to residual current through the diodes even at low voltage the linearity is not fully guarantied and the parallel resistance of the diodes is temperature dependent. So the early 2 diode (and also with 3 diodes and too large a value for R23) version had a slightly temperature dependent gain and limited linearity.  An error in the gain or nonlinearity of the slope amplifier causes an error in the contribution from the residul charge ADC and thus some DNL errors (e.g. < 0.1 ppm of FS range) and noise (as the DNL error has a random component).
 
The extra diode D10 and R23 keep the voltage over D2 low for the first about 400 mV of output voltage. The initial current through D10 is send to ground through R23 and not yet working as feedback, as D2 does not conduct much at below 100 mV. This way the linear range for the amplifier should be larger by about 400-500 mV. The curve is than more like logarithmic - linear with a gain of about 20  (from about -200 mV to +700 mV at the output) and than approximately logarithmic (near twice the gain) again.

[SilverSolder]

Does the INL actually vary significantly over time?  Is it possible to store the parameters and remove the error mathematically in the CPU and expect that to keep working for a reasonable amount of time?

[Kleinstein]

Much of the INL is expected to not vary much over time, but nothing is for sure. Some errors may also be more like history dependent, not just a simple function of the reading.

Except for self heating of the resistor(s) at the integrator input I don't know a significant INL source.  I have a good idea of the INL effect expected due to DA of the integration cap. If my calculation is right and from the measurements so far it looks like DA related INL errors are at <10 ppb level and thus not a real issue.  It is really hard to tell how those still unknown INL sources would change with time etc.

It may be possibly to remove some errors numerical, if the error is actually known. At the current level it can be quite demanding to measure the INL to a high accuracy.  At least for the more short range wiggly part (e.g. due to combination of run-up and rundown) the self test shows that there is not very much of this shorter range INL to be expected (it still only cover some 90% of the sources). So the main INL part to look for is a more smooth background more like a lower order polynomial.

The self heating effect on the input resistor and thus ADC gain is actually corrected by the extra reference measurement. For the stability tests with the external reference one can see that the measured ADC gain before the correction is changing quite a bit,  much more than the stability after the correction. So this part works very well and is also expected to correct much of the self heating part to the INL. So a possible major INL source is  already corrected - not from pure math but with the extra measurement. This slows down the readings (3 PLC instead of 2) and adds a little (as the ADC noise is low) to the reference noise. At least with just an LM399 reference or not so good resistors it is worth it. It may be different with a lower noise reference (e.g. LTZ1000) together with much better resistors.

[Rerouter]

So to clarify, R23 must be outside the feedback network in order to not upset the linearity your trying to accomplish. equally a transistor could not act as a more ideal diode to replace it?

[SilverSolder]

We could create a profile of how much self heating there is...   current^2 * resistance * time, minus losses to the environment...   so depending on what you have been measuring recently, the CPU would make different adjustments to the numbers, with a time decay factor...   with a bit of care, and perhaps a heat sink on the resistor to better control its ambient temperature, we might achieve extremely good INL numbers out of the modest hardware...

There could be a calibration cycle built into the software that builds the profile by measuring the device's own reference.

It would not be simple software, necessarily, but it would be beautiful!  :-)

[Kleinstein]

I did some updates to the hardware. The main change is changing the critical resistors at the integrator input and for the  7 V to +-14 V amplification to NOMCA resistor arrays: 50 K for the integrator and 10 K (2 in parallel each) for the reference amplification.
This gives a big improvement in gain stability. In the initial version the gain drift was really poor (see first post) - the gain is now very stable, now in the 0.2 ppm/K range.  The other point that improved is the offset drift before auto zero mode. This is now at some 7 µV/K. This is not impressive compared to OPs, but the main part likely comes from resistor matiching. The 7 µV/K correspond to a relative TC of some 1 ppm/K.

Another point I found was that there seem to be some thermal EMF right at the DG408 MUX. Inputs on different sides of the chip show an offset (some 2 µV, but constant in my case). This may be relatively high because the chip is relatively close to the warm LM399 reference  .

The odd "after-effect" is still no fully understood  .  Testing with different frequencies of the modulation (26 kHz and 78 kHz) show very little difference. This pretty much excludes DA as the cause, as DA effects should change by a factor of 3 in this comparison. The effect depends on the resistance at the input - so it looks like a transient input current pulse. So my suspicion is now back the to buffer amplifier, maybe the MUX chip. With now less drift is should be easier to check.

Attached are 2 plots for a drift measurement. The temperature changes by a little over 2 K over the measurement. At the end, the cover / shield was removed, so not just a temperature effect.

The gain over time shows some noise, that looks a little like popcorn noise. With closer inspection also the offset part seems to have some step functions (not related to ADC internal coarse steps).  The step like noise can also explain that in the AZ mode there are some points off the normal distribution.

The step like changes in the gain (reference read back by the ADC) make me suspect that this effect could be resistor excess noise. The NOMCA arrays a specified as < -30dB  and that is about the order of magnitude noise I see.  So for lower noise it may need better resistors, though the NOMCA arrays are still not bad - noise wise comparable to the thin film resistors I had before. There drift just obfuscated the jumpy part.

[Kleinstein]

A small update:

I did some linearity test with an external reference, based on an LM399. The first and probably simplest test is the so called turn over test. An external reference is measured both as a positive and negative voltage. In my case the polarity change is done with a simple mechanical switch at the reference (choosing one end between the positive and negative side) and the MUX at the ADC, also switching between the positive and negative side.  For a turn over test, there are 4 voltage readings: the positive and negative voltage reading and 2 readings that should normally give zero, but do measure residual offsets (e.g. thermal EMF) at the switches. The resulting turn over error is the sum of the positive and negative reading minus the 2  "zero" readings.  The zero readings are relatively stable a about -1 µV in my case.

The graphics shows the measured turn over error for a few voltages:


The error of some 5-10 µV is larger than hoped for, but not so bad either. It is a little surprising that the error is larger for the smaller test voltages. The test at 1.5 v was done twice, at the beginning and at the end (lower error). Each of the tests showed relatively low drift,  more like suggesting an uncertainty in the +-1-2 µV range. So the difference between the 1 st and last test is more like a question of the warm up time, not noise.

[Kleinstein]

I think I found the reason behind the rather large turn over error:  Adding some small bias current to the output of the buffer amplifier improves things a lot (have to improve my external reference to see things different from zero)  for small voltages. So it seems the output cross over distortion of the OPA145 in the buffer was the weak point. Chances are a little more current would also improve things at higher voltage.

Using the supply bootstrapping essentially remove the errors from limited CMRR and limited gain, but it does not help with the effect of loading the output. The OPA145 is a low power OP and thus likely runs the output stage with low current and is thus relatively prone to cross over distortion. It looks like my OPA145 needs some extra 7 µV at the input when going from sinking a small current (e.g. 50 µA range) to delivering a similar current. Chances are the output impedance is highly nonlinear, with most of the voltage change at low currents.

The turn over error getting better at high voltage is probably a compensation of 2 effects: the rather constant part from the cross over distortion and a conventional square law part, e.g. from thermal effects at the resistors, that happens to be negative here. So with a fixed buffer I have to expect something like -5 µV turn over error at 10 V.

[Rerouter]

how did you implement the bias, just a resistor to the op amp bootstrap supply, or something different?

[Kleinstein]

The bias is just a resistor to the bootstrapped supply, so easy to implement.

[Kleinstein]

A small update:
I did a new measurement on the turn over error with a little high bias current (some 600 µA). The result was not as good as hoped for an at first looks odd. The turn over error is roughly proportional to the voltage used for the test.
If one uses a polynomial representation, the turn over test is sensitive to the even powers. So one would expect contributions proportional to the square , 4 th power and maybe 6 th power. So this would be an error more at higher voltage. However the polynomial form is only one possible form and other shapes are possible, e.g. with 2 nd, 4 th and  6th order parts compensating to large parts.

As seen in the plot there are different values for some voltages and there is some scattering due to drift and noise. At the low µV level the LM399 reference starts to show it's limits.

With the same reference circuit I also did a few INL tests with looking at 2 voltages in series and the sum.  Tests with some 4.6 V + 4.6 V , 3.8 V + 5.4 V and 3.1 V + 6.1 V showed rather little (some 1 +-3 µV) linearity error for positive voltages. The measurements are essentially limited by the drift and noise of the references. Also thermal EMF and EMI may cause a µV or so.

The main troublesome part is that for some still unknown reason the input voltage not only effects the current reading, but also the next few conversions a little. The effect did not change noticeable with the better resistors.  So it is likely no linked to heating in the resistors. The effect is also quite fast and large, so it likely is not a thermal effect on the buffer amplifier. Here it helps that the bootstrapped supply of the critical OP reduces the power consumption of that OP. So the main heat sources (transistors in TO92) are some 1 cm away.

[dietert1]

I know very little about your project and this may be a stupid idea, but your diagram looks to me like a "diode" acting above a threshold of 1 or 2 V. And the diode effect is about one ppm - difficult to discover.

Maybe also precision resistors need to be qualified separately for both current directions.

Regards, Dieter

[Kleinstein]

The resistor arrays are NOMCA type. AFAIK they are TaN on an alumina substrate. So I don't think they should have a problem with current direction.  This could be a problem with resistors on a silicon substrate (e.g. MORN or LT5400 series).

So far my suspicion is that short pulses of the reference could be part of the turn over-error. Ideally at 0 input, there are no short pulses. At positive input there is an linear increasing number of short negative pulses. With a negative input the pulses are negative. If for some reason the short (1 µs) pulses behave a little different from nominal, this could result in a small difference between the both polarities. For test I may just extend the min. pulse length to maybe 4 µs  (at the cost of a reduced input range).

Anyway the turn over error is not my main concern. Ideally the voltage reading could combine a positive and negative reading to remove this error. This may be the best way for a voltmeter anyway, as it would give a larger input range (e.g. +-20 V +some over range).
My main concern is the slow "settling" or delayed effect from the input. This may even effect my external reference.

[iMo]

The resistor arrays are NOMCA type. AFAIK they are TaN on an alumina substrate. So I don't think they should have a problem with current direction.  This could be a problem with resistors on a silicon substrate (e.g. MORN or LT5400 series).

Could you advice us how to wire the LT5400 as the feedback resistors in the the 7V->10V opamp booster (regarding the potential issue with the substrate influence), plz?

[Rerouter]

The thermal output of the input buffer is not static, it does vary with input voltage, which could in turn cause offsets that scale with input voltage, Its small, but may help account for what your seeing if its response changes at different ambient temperatures. It also changes which output transistor is heated on the op amp die, which could move the offset.

Equally does the offset remain the same if you perform the turn over a third time?

https://www.eevblog.com/forum/projects/multislope-design/msg2585700/#msg2585700

[Kleinstein]

There is a possibility for some thermal effects in the input buffer. With the bias current, the OPs output stage only uses essentially only one transistor - the other side should be off at some 500 µA. With only some 200 µA and only a 5.x V supply (some 4 V for the output stage), I would not expect that much thermal effect. The OPA145 is made to be low drift.
The buffer version from the link may need a slight adjustment (e.g. R27 smaller) to stay in the input common mode range of the OPA145.

The turn over tests are already done with multiple repeats. Usually some 2-4 times reading each polarity for something like 5 seconds. The difference usually stays the same and settling  is fast (not visible from the data). However there is some low frequency noise in the references, especially popcorn noise. So ideally one gets about the same reading after polarity change, but sometimes there is a considerable jump of some 2-5 µV, likely popcorn noise from the references or resistors. As expected these jumps are larger at higher voltage. It takes some tries to get data without much jumps in between to get good data for the higher voltages. The switch / mux related offsets are read less frequent, but these do not change much over time and are low noise.
Doing the test again later, there is same scattering. However it is not clear if this really the errors getting smaller or just noise or different EMI effect.

@IMO:
The 7 to 10 V step is a little off topic. This is just a static divider and any possible substrate leakage should not be so critical. I have not found specs for this for the LT5400, but I don't expect this to be a problem for the lower resistors and normal temperature. I may be an issue for the 1 M version at high temperature. The 7 to 10 step could be done with 2:1 resistors from 7 to 10.5 and as a separate less critical step  10.5 to 10 with some 1 K and 20 K. The exact ration also depends if one starts at 6.9 V or 7.1 V.

[iMo]

@KL: my question is not about how to do 7->10V, but "how to wire" the 2 or 3 LT5400 resistors in regard to the "current direction" because of the silicon substrate (as you mentioned above).
Imagine the 4 resistors inside the package and 10k+10k/10k divider (A=1.5). Now how to wire those three resistor to minimize the potential current direction issue.

[Kleinstein]

With 10 K resistors I would not worry so much about the substrate leakage.
For the resistor sequence I see 2 logical ways to chain 3 resistors. One is the simple sig-zag like form with short connections on both sides.
The second form is the same current direction and thus longer connections.

I expect both ways to be about same quality, as it is symmetric.  So I would prefer the simpler layout. 

[Kleinstein]

A small update on the choice of capacitors.

With slower modulation (some 27 kHz). Some DA effect gets visible - kind of intentionally. The final version would likely use faster modulation, which reduced the effect of DA about proportional, as less charge is stored in the cap.

So I did a few measurements on the DA for different capacitors. The same ADC HW is used, but with an extra SW part for the DA test. The test is one a different time scale from the normal data-sheet numbers, more closer to the time scale relevant for the ADC.
For the test the capacitor is charged (to around 5 V) than hold for some 32 ms and discharged by the normal rundown procedure. From than on the µC internal ADC is used to measure the reappearing charge due to DA at a few times. To get a larger range a 2nd rundown is used after some 20 ms. The total time to watch the recovery is some 42 ms. The same procedure is than repeated with opposite polarity. For noise reduction readings from some 100 cycles are averaged.   The start of the time scale is a little uncertain due to a variable length of the rundown.
The result is the difference between both polarities: this way a constant drift of the integrator and the zero point of rundown is removed. Even at the end (some 41.5 ms) the DA effect dominates of the drift rate of the integrator.

The absolute numbers are different from the standard values because of the different time scales. The standard test uses much longer times (1 hour charge, 10 second discharge and looking the the charge after 15 min).  My test is more like 30 ms charge some 100 µs discharge and looking at the recovery after that up to some 40 ms. So the standard DA vales would be the rise happening some 3-4 decades to the right.

The capacitors tested so far are:
1) 2.2 nF PP capacitor 400 V from Kermet
2) 2 x 1 nF NP0  THT MLCC capacitors with epoxy coating
3) 2.2 nF PS capacitor (old (1980s ?), used in most of the early tests)
a second PP cap (Wima MKP2  630 V)  was tested with an earlier SW and was similar to the other PP.

The NP0 cap is surprisingly similar to the PP cap in performance. The old PS cap turns out to be slightly better - though not very much.
The leveling off to long times is likely due to the limited charging time, not necessary a property of the capacitors.

[ogden]

You may want to check Polyphenylene-sulphide (PPS) film capacitors as well. Wima manufacture such, Panasonic as well. Those are used in high performance PLL/VCO (fast lock) applications that require as low DA as possible.

[Kleinstein]

From what I have read so far and the datasheets PPS caps are good (similar to good PP) at the long time scale, but more on the poor side at the short time scale (higher loss factor at 10 kHz already). So I may give it a test, but I don't have very much hope that they are really good.

I have more hope in high quality NP0 caps. There are quite different versions of NP0 caps - NP0 only specifies low TC ceramics not the material. I still have 2 different types there to test. The problem is that not all caps specify DA and often it is something like < 0.1%, so not really specific.

Also PP caps can vary between types and brands. Not all PP are the same.

PS:  I just got data from another NP0 cap:  about in between the PS and PP caps , but likely some out-layers. So I have to remeasure / check.

[SilverSolder]

Perhaps it is possible to improve performance with compensation in this application?  (attachment)