Electronics > Metrology

DIY high resolution multi-slope converter

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MiDi:
Recognized today that I screwed up and patched the wrong branch of the FW, which had long delay between readings :palm:
The results for different run-up versions W&P are not compareable to former results, have to repeat the measurements:


--- Quote from: MiDi on January 08, 2022, 04:42:29 pm ---To test for DA on the delayed/settling effect, the FW & control software was modified to run mode B in selected run-up version (formerly one of the two readings was done everytime in run-up Q):
Comparison of 3 run-up modes were done for P: fast, Q: normal, W: slow (P shows higher noise then Q, W lower)

--- End quote ---

MiDi:
Next try to test for DA on the delayed/settling effect, the FW & control software was modified to run mode B in selected run-up version (formerly one of the two readings was done everytime in run-up Q):

Diffs for completeness, they did not change since last time.

FW hack diff:

--- Code: ---@@ -1053,10 +1053,11 @@ mslopeB:                   ; run multi-slope, 2 Runup versions for tests
  ldi temp,255
     st  x+,temp            ; Data are send during next runup, one ADC is ready
 
+    rcall mslope1          ; 2 nd conversion
 
-    rcall runup_P3nF        ; nromal mode
+/*    rcall runup_P3nF       ; nromal mode
  rcall rundown
- rcall mslope2          ; data collecton 2nd conversion
+ rcall mslope2          ; data collecton 2nd conversion*/
     rcall control          ; Check UART
    rjmp mslopeB
--- End code ---

Control software hack diff:

--- Code: ---@@ -283,11 +283,11 @@ def read2 (n):              # 254, 251: 2 readings (modes A, B, E)
 
     if n == 254:
         u2 = readADC(k0[ruv])   # result of 2. conversion
         du = u1 - u2
     else:
-        u2 = readADC(k0[1])     # result of 2. conversion, mode B for INL test
+        u2 = readADC(k0[ruv])     # result of 2. conversion, mode B for INL test
         #du = u1-0.5*(u2+u2old)      # TODO should be only for mode B? Or better avg 0V reading even for mode A/E?
         du = (3*(u2old-u1)-u1old+u2)/4   # interpolate both values
 
     #f.write('{:11.3f}\t{:11.3f}\t{:13.4f}\t{:6.0f}'.format(u1, u2, du*sf, adcdiff))
     writeraw()
--- End code ---

New comparison of 3 run-up modes P: fast, Q: normal, W: slow (P shows higher noise, W lower than Q) were made.
Each measurement was repeated 3 times and best with lowest noise was chosen for comparison (only values with original FW were kept in table for reference).
This time only one out of 18 showed pronounced 1/f noise, no popcorn noise was spotted.

Both modes (A/B) do not show significant differences, in mode B there is a marginal difference between run-up versions (see attachments), this means no relevant effect from DA.
There is some gain error ~0.1ppmFS, therefore the trailing values were matched manually for better comparison and the results in the table should be handled with some grain of salt.


Comparison table mode A (AZ):
Input | dev to 0V in µV | -> in ppm (10V) | dev to +-7V in µV | -> in ppm (10V)7V orig FW19.71.97-27.7-2.77-7V orig FW-12.9-1.29-19.0-1.907V adc first RU Q0.40.04-7.4-0.74-7V adc first RU Q-0.5-0.05-3.6-0.367V adc first RU W0.40.04-7.1-0.71-7V adc first RU W-0.6-0.06-4.9-0.497V adc first RU P0.70.07-7.1-0.71-7V adc first RU P-0.6-0.06-3.6-0.36

Kleinstein:
Part of the slightly different gain for the 2 run-up modes is from settling (µs time scale) of the integrator.  A faster setting of the integrator can improve on this. The gain difference corresponds to the slope seen in mode B comparing 2 versions.

It is a bit strange to see that the settling / delayed effect is similar for cases P (fast) and W (slow), but a bit different from the intermediate case.
For a DA caused effect one would expect more delayed effect for the slow mode.
Anyway the effect is small (settling to 0.2 ppm within some 80 ms is quite good).
So much of the delayed effect that I also saw with the original FW is fixed with switching the input signal only after reading the µC internal ADC.

RikV:
Is there a Github repostory linked to this thread?

MiDi:

--- Quote from: RikV on February 24, 2022, 11:53:31 pm ---Is there a Github repostory linked to this thread?

--- End quote ---


--- Quote from: MiDi on January 02, 2022, 11:05:31 pm ---The project for the ATMEGA version is now on github: https://github.com/Multi-slope-ADC?tab=repositories
Separated into four parts:

* PCB from Rerouter - BOM & additional information under Releases
* Firmware
* ADC control program (Free pascal)
* ADC control program (Python)
--- End quote ---

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