DIY high resolution multi-slope converter

[MegaVolt]

Can take a capacitor that is used in 3458a?

[Kleinstein]

The modern DMMs usually use some kind of NP0 caps. The caps in the 3458 are quite small. I want to avoid a modulation that fast and thus need a larger capacitor, more like 1 - 2.2 nF. 

There are many different flavors of NP0 and it is hard to find a good type, as the relevant parameters are usually not given in the data-sheets. It is about isolation resistance that should be high, preferably > 100 G.  The other point is loss factor or DA for a time scale of some 20 µs to 100 ms - here one may find tan delta or Q for some 1 MHz and DA for times in the 1000 seconds range (the standard DA test), but data for the 10-1000 Hz range are rare. From what I have read so far some low loss NP0 types (usually specified for even higher frequencies)  could be a good bet. However they tend to come in small form factor (e.g. 0402). I prefer 0805 or 1206 to have a guard trace under the cap. At least some of these specify parallel resistance > 100 G.
I prefer NP0, as they have a low TC and thus less effect on the scale factor for the residual charge reading with the ADC.

For the film caps there seem to be quite some variations too. Compared to the classic article given, the PS and PP caps I have tested are about in the same ball park. In my case the PP caps with higher DA and the PS cap better than in the article. I don't think this is a problem with the measurement, more like having different brands and types. For the PP dielectric there are different purities of the material that can make a difference.  The other point can be the cleanness when making them (this could especially effect the slow end). The typical processes may have changed over the last decades.

[iMo]

People say the resistance of an FR4 (perfectly cleaned) for couple of mm distances is like ~10G.
You want >100G.
Would PTFE standoffs help?
Edit: ok, the guard ring under the cap (between the pads) helps?

[MegaVolt]

Here are my archives.
Comparison table of dielectrics.
And also a series of capacitors where the insulation resistance is prescribed. But unfortunately there is no 100 T Ohm. 1 ... 10 T Ohm

[MegaVolt]

I found one: file dsc03028.pdf and dsc03029.pdf

[SilverSolder]

[...] I prefer 0805 or 1206 to have a guard trace under the cap.  [...]

I read somewhere that the commonly used FR4 PCB material has very significant dielectric absorption...   it might be worth running some tests where the capacitor is in free air?  This could include considering the traces that lead to/from the capacitor...

Perhaps the teflon stand-off suggestion is worth a try, at least as an experiment?

[jaromir]

What particular problem of this ADC has solution in form of teflon standoffs?

[SilverSolder]

What particular problem of this ADC has solution in form of teflon standoffs?

Possibly none at all!   -  the standoffs are perhaps addressing the question,  "How to minimize DA"  (assuming the PCB is a significant contributor, which has not been shown)

[Kleinstein]

I know that FR4 has quite some loss, compared to low loss dielectrics. However the good thing is that there is not much field in parallel to the capacitor. The integrator input is a virtual ground and largely surrounded by guards. The other capacitor side is kind of avoiding close neighborhood .  I could check the effect of the board by testing with 2 caps in parallel - this should reduce the relative effect of the board or other parasitic capacitance.

I don't think I would need Teflon standoffs at the ADC. There should be reasonable low leakage, but in my version with reading the residual charge at a fixed time, leakage is only a 2 nd order problem. The switch chip is not really specified for low leakage anyway - in the current setup I still get an effective bias current to the integrator in the 5-10 pA range - so must be some luck there. As am still doing quite some changes I have not even cleaned the flux (no clean type).

I still have a few C0G types caps to test. From a quick look at the data-sheets something like Vishay  VJ0805D102KXAAJ  (1 nF) , a low loss 0805 cap is my current favorite.  They are specified for >100 GOhms and  < 0.05% dissipation at 1 MHz or 1 kHz (for 1.5 nF).

To avoid the small, hard to clean area under the chip, I consider mounting the cap upright standing with an extra bodge wire.

The Bob Pease article on DA  has a nice graph. My measurements contain data for some 30 ms of charge, some 2 ms effective discharge (use this time as zero point) and 20 ms recovery. So I can show the approximate data on the graph. The red circle is for the PP caps and THT NP0, the green is about the SMD NP0 (Vishay VJ1206A...) and yellow is the PS cap. The graph is a little confusing in using the discharge time for the scale.

[dietert1]

Interesting discussion!

The russian teflon capacitors really seem to be much better, please have a look here:
https://www.eevblog.com/forum/testgear/hp-3455a-last-digit-jitter-in-hi-res-auto-cal-mode/msg967855/#msg967855

Today i ordered some 3.9 nF parts fit for our HP3456A DVMs. Before using them i would try to reproduce the scope measurements linked above.

Regards, Dieter

[Kleinstein]

Needing 3.9 nF in the 3456 suggest a relative slow modulation and thus relatively high sensitivity to DA.
On the positive side a relatively long time spend for the rundown and especially the slow slopes acts a little like the time the cap is shorted in the DA test. Relevant is the charge reappearing after the last rundown step. So a slow run-down (e.g. with some waiting before the final slow step) could help reducing the effect of DA.
A good quality cap can definitely help.

So far I have no luck for me to find a really good one, my best one is still the old PS one, about as good as the cap in the scope test (regaining some 160 ppm from 5 ms to 100 ms)  In my test it is 160 ppm from 2 ms to 22 ms.

The scope test looks reasonably simple, and the result may be easier than checking INL of the DMM.

[iMo]

OT
I've read this pdf on Multilayer Organic capacitors with DA smaller than teflon in SMD.. 
https://www.mouser.com/pdfdocs/DielectricAbsorptionofMLOCapacitors.PDF
Why OT? The largest cap value I've found is 5.1pF 

[Kleinstein]

I added another NP0 SMD capacitor to the list of tested DA caps, with relatively poor performance. To get a really poor cap I tested a parallel combination of 2.2 nF NP0 and a 1 nF polyester cap. In the DA test it goes partially off scale for my setup. The DA effect is about 5 times worse than the PP capacitor. So for the polyester cap alone this would be some 15 time higher DA than the PP one.

The main purpose of the test is to increase the DA related errors so far that they are easily visible. Due to the low modulation frequency my linearity test already shows some errors with a relatively good cap. The same test with the intentionally bad cap shows an largely amplified error.
This test shows that DA can be a major error source - at least for the relatively slow modulation in run-up.  The curve with the bad cap reproduces most of the details of the other curve - so most of the error with the good cap is also due to DA. Looking at the individual data sets shows that the main effect is taking over charge from one conversion to the next. The main effect is thus from the relatively slow DA part.

To reduce the error there are mainly 3 ways: reduce the change in average integrator voltage (e.g. better feedback algorithm), increase the modulation frequency and get a better capacitor.

The intentional bad cap also amplifies the delayed effect seen before - so at least some of this is also due to an DA effect. It is still odd why faster modulation did not help here. It could be the slightly different time when the comparator is checked that makes the fast modulation not so much better.

[ogden]

Seems like you need to test "Teflon" (PTFE) capacitor as well.

[iMo]

https://exxelia.com/en/product/detail/362/ta-72-ptfe

Interestingly they rate PolyStyrene 0.001% DA, while Teflon 0.006%..

[Kleinstein]

I am considering PTFE caps. Some NOS (likely Russian milliary left over) are available at a reasonable price (some $15 for a set of 8 or 10). However they are quite bulky and thus possibly more parasitic coupling.
Looking for low loss caps, I found a hint in an Murata appl. note that type CH ceramic (slightly positive TC, low µ dielectric) may be a good choice.  I still have hope to get away with a better C0G maybe CH version and a faster (e.g. 5x, maybe 10 x) modulation in the run-up. The faster version could use a smaller cap, like 1 nF or even less.

So after testing a few more caps I have at hand, the next point would be faster run-up.

[Kleinstein]

No more need for a PTFE cap: I found a good ceramic one:  TDK C2012C0G1H222J
In the DA test it is much better than the other (about a factor 5 from the PS). With a slightly faster (e.g. x 2) run-up the DA error should than be really small (e.g. 0.1 ppm Level).

So there is quite some difference between the different type of NP0 caps.

[Rerouter]

I think the rule of thumb I found was higher voltage, larger package size NPO has less DA due to thicker sheets of material,

Still if you want a good read, this is probably the most detailed study into DA that exists for the public

https://nepp.nasa.gov/files/25847/2013-Taverovsky-paper-NEPPweb-MLCCsVabs-n264.pdf

[Alex Nikitin]

No more need for a PTFE cap: I found a good ceramic one:  TDK C2012C0G1H222J
In the DA test it is much better than the other (about a factor 5 from the PS). With a slightly faster (e.g. x 2) run-up the DA error should than be really small (e.g. 0.1 ppm Level).

Yes, the current generation of TDK NP0/C0G leaded capacitors is excellent, very low DA and femtoamps level leakage even for >10nF caps.

Cheers

Alex

[iMo]

We would need a quick test to know whether you have got the TDK ones or something else ..

[SilverSolder]

Yes, the current generation of TDK NP0/C0G leaded capacitors is excellent, very low DA and femtoamps level leakage even for >10nF caps.
[...]

Are modern leaded capacitors made by, essentially, putting leads on a SMD component?

[Kleinstein]

The good cap I tested is SMD  size 0805 with 0.85 mm hight. It was bought from Mouser - nothing special (some 70 cents for 10 pieces).
The corresponding point (at some 3 ms discharge) in the Graph from Bob Pease is at about the curve for the PTFE cap.

[Alex Nikitin]

The good cap I tested is SMD  size 0805 with 0.85 mm hight. It was bought from Mouser - nothing special (some 70 cents for 10 pieces).
The corresponding point (at some 3 ms discharge) in the Graph from Bob Pease is at about the curve for the PTFE cap.

Try something like FA28NP02E222JNU06 or FA28C0G2E222JNU00 if a leaded cap is more convenient.

Cheers

Alex

[wildhog]

The HEF4053B switch turns on in 65ns typ, 130ns max with a +-15V supply.  The difference between turn-on and turn-off is unspecified and is important for accuracy.  If this time skew is 1nsec, and the switching period during run-up is 100us, this is a 10ppm error.  This can be calibrated but not on a cycle-by-cycle basis as would be required to eliminate its drift with temperature/life. 

How is this dealt with?

Thanks,
Dave

[Kleinstein]

I have tested the slow HEF4053, but my favorite is the considerably faster 74LV4053. More stable delay and less jitter is a reason for preferring the faster switches. Another factor is low a relatively small internal gate capacitance and thus less supply noise. The switching speed (delays) can effect the result a little. However most of the effects would cause just an offset or change in gain factor. The 2 reference switches are also connected symmetric, so that many of the errors of those 2 switched would compensate.

The offset is corrected with normal auto zero, just switching between a signal and zero conversion. The effect on gain is normally not corrected. For the new setup with resistor arrays I did a quick check on the temperature drift of the overall gain factor and it turned out to be very stable ( < 1 ppm/K).  Most if this is due to the resistors and hardly any effect from heating the LV4053.

In the version before with less stable resistors I had a fast gain factor measurement. So the measurement cycle was signal , zero and 7 V reference. So the gain factor could be corrected on the cycle by cycle basis. This was needed as there was quite some drift in the gain factor.  Even with this extra measurement the overall noise was still acceptable: the noise of the reference conversion is less than the LM399 reference noise. The extra gain correction about doubles the ADC noise - but it is still good enough, as the ADC starts with very low noise.
This mode may still be attractive, as it can also correct some thermal INL effects, that where visible with the simple resistors.