Despite the simple hardware (about as simple as a good multi-slope ADC can be) the noise of the ADC itself is quite low. Currently I get a little below 1 µV RMS for 1 PLC auto zero readings, good enough for 7 digit resolution and often more limited by the reference.
The PC side program is currently written in Turbo Pascal. The software assumes a build in RS232. So for modern PCs it would need to be rewritten, e.g. to support an USB to UART bridge.You can read from serial port by opening a pseudo-file named "COM1"/"COM2"/... and reading like any other file. That ought to give you access to all serial ports supported by Windows, including USB.
I remembered an interesting part which could be useful for the input resistor: a SMT chip ceramic thermal jumper (https://www.electronicsweekly.com/news/products/passives/chip-component-gets-heat-tight-spots-without-leaking-electrons-2019-04/). Maybe sucking some of the heat away from the resistor into the ground plane would help. Or use them to thermally bond the three integrator input resistors together?I tried to google thermal jumper, doesnt look like its in production :-//. not on digikey too
I tried to google thermal jumper, doesnt look like its in production :-//. not on digikey tooThey are "on order":
It had been discussed in the Multislope topic some time back, but let me kindly ask whether the runup is still as follows:
You do 20ms long measurement, 800 phases, 25us each (==40kHz modulation)
Pseudocode:
pos_phase = 0; // positive REF counter
// do 800 loops, 25us each == 20ms
for (phase_num=0; phase_num<800; phase_num++) {
1. set REFP for 2.5us long;
2. based on comparator output set REFP or REFN, if REFP then ++pos_phase;
3. wait 10us;
4. set REFN for 2.5us long;
5. based on comparator output set REFN or REFP, if REFP then ++pos_phase;
6. wait 10us;
}
result_POS = pos_phase;
result_NEG = 800 - pos_phase;
The Comparator output synced with rising clock edge (ie clock = 2.5us period)
Is that somehow correct?
..
The runup is now a little simpler, with only 1 variable phase and shorter fixed phases:
1 µs fixed negative reference
25.125 µs positive or negative depending on a comparator reading
1 µs fixed positive reference
..
I changed the buffer amplifier supply from true bootstrapping form the output to a system with an extra OP buffer (OPA172) to drive the supply voltage center from the input signal.Interesting. Any schematics available?
One input was fitted with 1 nF (towards signal ground), but no difference visible.Where exactly did you place the 1nF? before or after the 22K (across the input protection diode).
There is some filtering for the reference at the ADC, though currently not much (only 1.5 K and 1 µF). There may be a chance to use more filtering (e.g. some 5 K and some 10 µF). Usually reference filtering is not considered that effective, but it may be worth it to have the same reference level for all 3 conversions that make up a reading.What would be max acceptable thermal noise of that resistor?
As the purpose of the slope amplifier is not making much sense to me?The value of the feedback resistor in your schematics is 5k - it should be 100k (or something like that).
for D10, exactly how does its linearity effect the measurement, and could this be worked around by using a NPN transistor with Base and collector tied? (Routing out, but not so fond of possible injections into the signal path)
As the purpose of the slope amplifier is not making much sense to me? could the same not be accomplished with a gain limited comparator and an output divider?
Edit: could R23 not be put in parallel with D2?
The resistor arrays are NOMCA type. AFAIK they are TaN on an alumina substrate. So I don't think they should have a problem with current direction. This could be a problem with resistors on a silicon substrate (e.g. MORN or LT5400 series).Could you advice us how to wire the LT5400 as the feedback resistors in the the 7V->10V opamp booster (regarding the potential issue with the substrate influence), plz?
[...] I prefer 0805 or 1206 to have a guard trace under the cap. [...]
What particular problem of this ADC has solution in form of teflon standoffs?
No more need for a PTFE cap: I found a good ceramic one: TDK C2012C0G1H222J
In the DA test it is much better than the other (about a factor 5 from the PS). With a slightly faster (e.g. x 2) run-up the DA error should than be really small (e.g. 0.1 ppm Level).
Yes, the current generation of TDK NP0/C0G leaded capacitors is excellent, very low DA and femtoamps level leakage even for >10nF caps.
[...]
The good cap I tested is SMD size 0805 with 0.85 mm hight. It was bought from Mouser - nothing special (some 70 cents for 10 pieces).
The corresponding point (at some 3 ms discharge) in the Graph from Bob Pease is at about the curve for the PTFE cap.
I remembered an interesting part which could be useful for the input resistor: a SMT chip ceramic thermal jumper (https://www.electronicsweekly.com/news/products/passives/chip-component-gets-heat-tight-spots-without-leaking-electrons-2019-04/).
I don’t know if it’s a problem to worry about, but you can probably avoid reception of UART characters during the critical parts of the ADC operation by using a GPIO to as an old -fashioned Clear To Send (CTS) line and configure your ‘master’ (PC serial port?) into 4 wire mode (with RTS and CTS). The ADC uC can then simply say ‘not now, I’m busy,’ and the master can handle that in the UART hardware.
Given that you’re now considering additional logic resources, I wonder if a CPLD might be helpful.
On second thought, CPLDs don’t have ADCs and comparators. Maybe a PSoC, then? They have some special configurable logic built in which could be quite helpful
..So I tried the synchronization of the control signals with flip flops (currently 74HC74 as a dead bug bodge). The positive thing is that the clock phase of the external AVR clock is about right to use just xx74 flip flops. .Could you indicate the 7474 wiring, please (just indicate the two signals you synced, 74's clock is the external 16MHz)?
so far I am quite confident the INL is < 1 ppmFS and likely better, in the 0.2 ppm range, but I have no way to measure.
A pity the effort with the pcb bite the dust, I think $50 7digits +/-12V input AD converter would be an interesting playground for experimenters (and I bet a lot of them have got 3458A to provide some measurements).The PCB has some bodges, but except for the extra HC74 this is not too bad. One of the NOMCA arrays is already includes in the PCB layout (though not very good - a 20 K version and using 2 of the resistors in series is probably better (less excess noise)).
I was at that point of high confidence too, before testing the PCB version to find out that the version on the breadboard was better performance :-//. I now have quite some tests with the limited possibility at hand, and the results for the "final" versions looked good:so far I am quite confident the INL is < 1 ppmFS and likely better, in the 0.2 ppm range, but I have no way to measure.
Not trying to be snarky, but I still remember how confident I was about my first multislope ADC design, up to the moment I started real measurements ;)
so far I am quite confident the INL is < 1 ppmFS and likely better, in the 0.2 ppm range, but I have no way to measure.
.What is the function of third opamp in the buffer?
The turn over test revealed some problems with the buffer, that the extra bias mainly solved (though an extra 3rd OP may be better).
The PCB has some bodges, but except for the extra HC74 this is not too bad. One of the NOMCA arrays is already includes in the PCB layout (though not very good - a 20 K version and using 2 of the resistors in series is probably better (less excess noise)).
It would likely still need an update to the PCB to have 2 (maybe 3) x NOMCA resistors, an updated buffer, a few more SMD parts, include the bodges and a connector for an optional external reference.
The third OP in the bootstrapped buffer would just buffer the bootstrapped OP, inside the FB loop and with the normal +-15 V supply. This same configuration is used by CERN in there buffer for a high end ADC. This 3 rd OP would keep the load to the bootstrapped supply constant and suppress the output stage cross over distortion a had seen in my first try without the bias. It should be even a little better than just the bias..What is the function of third opamp in the buffer?
The turn over test revealed some problems with the buffer, that the extra bias mainly solved (though an extra 3rd OP may be better).
The third OP in the bootstrapped buffer would just buffer the bootstrapped OP, inside the FB loop and with the normal +-15 V supply. This same configuration is used by CERN in there buffer for a high end ADC.Oh, that makes sense, thanks.
I thinks I saw this for the Cern ADC too, but could not find it. I found another reference however:The third OP in the bootstrapped buffer would just buffer the bootstrapped OP, inside the FB loop and with the normal +-15 V supply. This same configuration is used by CERN in there buffer for a high end ADC.Oh, that makes sense, thanks.
I read a few documents about DS22 and DS24 CERN ADC designs, but I don't remember bootstrapped buffer. Could you, please, share or point me to appropriate document?
2 x 100 K in parallel would be an option too - with the advantage of possibly populating only one. As low cost alternative to the LT5400 (compatible footprint) there are MORN arrays - however with possibly quite some excess noise.Or 2x LT5400/100k with 3x 100k_A||100k_B..
[...] One thing that surprised me: The absorbed charge shows up slowly like a small current. Only after some 30 to 50 msec that current will slowly diminish when charge approaches its asymptotic total. [...]
"Short pulse effect" - short pulse means here the time in the modulation scheme where you a) set refP for Xus, b) you set refN for Xus, right?Yes, it is about the short pulse that occur in the modulation scheme during run-up. depending in the signal sign there are short pulses of either the positive or negative reference. The lenght is set by the scheme to some 0.5 µs to 1 µs and for testing I measure the difference in the results with 0.5 and 1 µs pulses. This is kind testing how fast the modulation can be and how much error to expect if the shorter pulses are used (assuming the longer pulses are OK).
The pseudo-differential input trick is interesting but makes me a little nervous. To a first approximation, you get 2 readings, so double voltage and sqrt(2) noise... seems too good to be true.The pseudo differential way does not even add much to the noise: the alternative classical method is alternating between the input and a zero reading. So the noise level would be about the same.
[...]
For the input buffer I am more like thinking about switching to an OPA189 chopper stabilized OP.
[...]
[...]
For the input buffer I am more like thinking about switching to an OPA189 chopper stabilized OP.
[...]
When in neanderthal mode, I have successfully used this amp as an ad-hoc buffer with literally no supporting components at all... it is an extremely stable and generally likeable component. It seems an excellent choice.
[...]
For the input buffer I am more like thinking about switching to an OPA189 chopper stabilized OP.
[...]
When in neanderthal mode, I have successfully used this amp as an ad-hoc buffer with literally no supporting components at all... it is an extremely stable and generally likeable component. It seems an excellent choice.
Not sure about that:
https://www.eevblog.com/forum/metrology/emi-measurements-of-a-volt-nut/msg2819014/#msg2819014 (https://www.eevblog.com/forum/metrology/emi-measurements-of-a-volt-nut/msg2819014/#msg2819014)
and following posts...
The "too good to be true" part makes me worry a little, but there is still the fall back option switching the inverter to a ground buffer.
Why a ground buffer and not just ground?The ground buffer comes out easy when the inverter is switched "off" at the input side. The buffer for most cases it not inside a critical path, so errors of that buffer should not be that bad. I hope I would need to switch back to ground buffer mode only for some kind of ACAL measurements to measure the amplifier gain and maybe if later added for 4 wire resistance measurements. It would add a little noise, but not much. Offset and output impedance should have little effect. I could use switching at the output, but this would need lower resistance switches and leave the ground return current from the gain setting.
The Keithley 2002 has a +-20 V high Z input range, but only uses a +-11 V ADC. So I had some hope to find a similar concept and some ideas there. There is no schematics available and the service manual only gives a crude block diagram. However the description of the self test steps gives more details. Combining the information gives a more detailed, though still incomplete diagram: The circuit seems to use a more basic concept, with an additional divider after the initial buffer for the 20 V range - relatively similar to the 2001 . So not much to learn from it :(.
Another part that is not that sure / clear and a little odd is the part with R313, R314 going via U242 to the input of U253. To me that part does not make much sense. The current sources for the references in the ADC circuit are a kind of elegant way to allow for a (small) difference between the input ground (ADGND) and the reference low side. However the ADC circuit still needs ADGND to be close (e.g. < +-1 V) to ground, so the signal at U253 can not be much different from ground.
The main part still left over is U236 (= OP27). It may be part of the buffer with U217+U257.
U256 also does not appear in the descriptions - these 2 OPs are likely used with the input protection (e.g. bootstrapping the protection) and maybe part of the input buffer (e.g. part of the floating supply or current source).
Syncing an MCU's ADC with such external events is difficult.With some MCUs its difficult, but with some its trivial.
Just stumbled on "precision" mux http://www.ti.com/product/TMUX6104 (http://www.ti.com/product/TMUX6104) with special charge-injection cancellation circuitry (-0.41 pC in the full signal range). TI article about charge injection (https://e2e.ti.com/blogs_/b/analogwire/archive/2018/10/18/is-charge-injection-causing-output-voltage-errors-in-your-industrial-control-system). For those who already know - sorry. Others may find something new, perhaps.
A 20x improvement from 1 change, Now that is something very nice to see,The improvement was relative to a bad starting point. So the unusual point was that the the crystal at the µC was unusually sensitive to external effects. The 2nd board is now about to the same level (maybe a little better) I have with the 1 st. I also started with just a crystal on the first board, but there was a relatively small effect changing to the canned oscillator - because of this (and because it took some time to find one) I was so slow in changing to the canned oscillator.
For the canned oscillator graph, how does that look if scaled by PPM of input instead of delta voltage?
1) slight changes in the input buffer (adding a resistor to provide a biasing current to keep the output stage in class A.I assume something like 100K to the -15V rail, or did you do something else?)
2) A canned oscillator and for one of the 2 boards also 74HC74 flip-flops for syncronizationAny description of how the 74HC74 is used, I presume inline with the PD2/PD3/PD4 lines? and maybe the PC3/PC4/PC5 lines?
3) An additional capacitor at the integrator: a direct feedback for the "slow" OPwould that be between U2 + and the intergrator input node, and assuming something low like 1nf?
4) A low pass filter and buffer for the average integrator voltage - currently used for debugging, as a test-point.already have an integrator output test pad, so if you have a rough circuit, I will just add it. always been a chunk missing from that area I've not been sure how to fill.
5) For a test : add a current mirror at the positive supply, controlled by a resistor from the buffer output + one to ground. The current goes to the integrator output. As a result the waveform at the integrator looks better (no change with input), but there is essentially no change in the INL error visible.
There are a few planed changes, not yet in HW:1. Had already started working towards 2 in series based on earlier comments, for 2 in parrellel that gets more interesting to lay out without cheating and mirroring on the other side of the board (you wanted the heat shared, which means to me all signals through both resistors)
1) use different resistors at the integrator: either LT5400-100K (1 or maybe 2 in parallel) or NOMCA as 2x20K in series each
this would be for a new board
2) test a buffer for the ground to the 4053 switch to make it easier to use an external reference I can test this with the current board.
3) For the integrator I would like to test another option to use extra FB from the average integrator voltage during run-up. This could help to reduce errors from DA and related. This part would be mainly an optional DG419 switch and a few resistors.
4) Changes to the buffer: 3 OP version with maybe different OPs or maybe just 1 AZ OP (e.g. OPA189).
5) Input amplifier and switching to make is a real voltmeter with different ranges, possibly later also a DMM with current and resistance ranges. This part would be more like a separate board.
Due to the position in the signal chain, most of the noise of the entire circuit is dominated by those input resistors, (was about 2700nV / root Hz when I was calculating using a 25K array), so using any tricks you can to reduce the noise of those resistors gets a very significant improvement in the entire circuit.
For 2 x LM399 one would use 2 separate resistors to the filtering and separate resistors to provide the current. The heaters would be directly in parallel.What physical mechanism(s) would you attribute to causing INL ? Is it simply self heating of the resistor or other factors?
For the integrator resistance I don't know exactly where the sweep spot is. More resistance adds a little to the noise (like twice the resistance at the input) and too low can increase the INL. I have tested 20 K to 105 K so far with no big problem. The last INL data are with 20 K. With 10 K resistors it did not work so well (too much drift), but this could be from the resistors used (power type wire wound). Maybe I have to repeat the test with different resistors, to see if there is significant more INL.
30 K would not be that much different from 20 K anyway.
I am new to this project and would like to understand how it works. I was not able to find: the kicad files, the software and a theory op operation. I suspect the letter one does not exist but where could I find the other two?(on github?)
I am new to this project and would like to understand how it works. I was not able to find: the kicad files, the software and a theory op operation. I suspect the letter one does not exist but where could I find the other two?(on github?)
https://www.eevblog.com/forum/projects/multislope-design/msg1376978/#msg1376978 (https://www.eevblog.com/forum/projects/multislope-design/msg1376978/#msg1376978)
The eagle file was the binary format as best I can tell. The xml one i can import into kicad.
Thank you very much for that,Those two points were misplaced dots from moved parts. In my program versions they are still connected.
R48 is a floating connection
IC13's (pin 7) output is floating
on your schematic klein.
The JFET at the reference heater is there to limit the current on start up. It may be enough to have a resistor there.
It’s the Agilent / Keysight 34972A DAQ. You can download the service manual from the Keysight website, and the schematics are near the back.I could not find the circuit :( Tell me where can I see the circuit?
I recommend the DC230A-C board with ±15V on the secondary side. Already have that demoboard on my desk and it works a treat by now. Still need to add the LDOs.125$ :scared:
Yes, an isolated supply would require some care. I guess the following would be relevant:
- Reduce capacitive coupling by using a large toroid core and a snap on plastic cover to make an air gap between primary and secondary
- Consider electrostatic shielding between primary and secondary windings (some designs have been spotted using coax cable for this)
- Reduce dV/dt with slew rate limited transformer driver and snubbers (on both primary and secondary) or maybe use a resonant converter
- Reduce stray magnetic field by using toroid core and careful winding terminations (no partial turns!)
- Reduce stray magnetic fields by careful layout of rectifiers and filter capacitors
- Investigate system sensitivity to various frequency ranges (eg frequency mixing in multiplex schemes, autozero / chopper amplifiers and ADC sample rates. Synchronisation of DCDC converter and ADC clock may be required
Edit: as you can see, that’s quite a few things to consider. PPM level equipment is hard.
US-Patent US9478351 seems to be a good read on this topology.Its a nice way of doing low-noise, low L/C txfmr. A little surprised they got a patent, pretty sure i've seen similar txfmr concepts as gate drive transformers though.
Another day, another few more steps into madness [...]
| Datasheet | Manufacturer PN | Manufacturer | Price | On resistance max | Channel Matching | Single Supply | Split Supply | On Time, Off Time | Charge Injection | Channel Capacitance CS,CD | Leakage |
| MAX4053ACSE+ | Maxim Integrated | 3.75 | 100Ohm | 6Ohm (Max) | 2V ~ 16V | ±2.7V ~ 8V | 175ns, 150ns | 2pC | 2pF, 2pF | 100pA | |
| https://datasheets.maximintegrated.com/en/ds/MAX4051-MAX4053A.pdf (https://datasheets.maximintegrated.com/en/ds/MAX4051-MAX4053A.pdf) | MAX4053CSE+ | Maxim Integrated | 3.58 | 100Ohm | 12Ohm (Max) | 2V ~ 16V | ±2.7V ~ 8V | 175ns, 150ns | 2pC | 2pF, 2pF | 1nA |
| https://datasheets.maximintegrated.com/en/ds/MAX4617-MAX4619.pdf (https://datasheets.maximintegrated.com/en/ds/MAX4617-MAX4619.pdf) | MAX4619CSE+ | Maxim Integrated | 2.24 | 10Ohm | 200mOhm | 2V ~ 5.5V | - | 15ns, 10ns | 3pC | 5pF, 8.5pF | 1nA |
| https://datasheets.maximintegrated.com/en/ds/MAX4558-MAX4560.pdf (https://datasheets.maximintegrated.com/en/ds/MAX4558-MAX4560.pdf) | MAX4560ESE+ | Maxim Integrated | 5.18 | 160Ohm | 2Ohm | 2V ~ 12V | ±2V ~ 6V | 150ns, 120ns | 2.4pC | 2pF, 4pF | 1nA |
| https://datasheets.maximintegrated.com/en/ds/MAX4581-MAX4583.pdf (https://datasheets.maximintegrated.com/en/ds/MAX4581-MAX4583.pdf) | MAX4583CSE+ | Maxim Integrated | 1.97 | 80Ohm | 1Ohm | 2V ~ 12V | ±2V ~ 6V | 200ns, 100ns | 0.5pC | 4pF, 6pF | 1nA |
| https://datasheets.maximintegrated.com/en/ds/MAX4581L-MAX4583L.pdf (https://datasheets.maximintegrated.com/en/ds/MAX4581L-MAX4583L.pdf) | MAX4583LESE+ | Maxim Integrated | 2.57 | 80Ohm | 1Ohm | 2V ~ 12V | - | 200ns, 100ns | 0.5pC | 4pF, 6pF | 2nA |
| https://assets.nexperia.com/documents/data-sheet/74LV4053.pdf (https://assets.nexperia.com/documents/data-sheet/74LV4053.pdf) | 74LV4053D,118 | Nexperia USA Inc. | 0.62 | 105Ohm | 2Ohm | 1V ~ 6V | - | 31ns, 24ns | - | 3.5pF | 2µA |
| https://assets.nexperia.com/documents/data-sheet/74HC_HCT4053.pdf (https://assets.nexperia.com/documents/data-sheet/74HC_HCT4053.pdf) | 74HC4053D,652 | Nexperia USA Inc. | 0.44 | 120Ohm | 6Ohm | 2V ~ 10V | ±1.5V ~ 5V | 31ns, 29ns | - | 3.5pF | 100nA |
| 74HC4053D-Q100,118 | Nexperia USA Inc. | 0.44 | 120Ohm | 6Ohm | 2V ~ 10V | ±1.5V ~ 5V | 31ns, 29ns | - | 3.5pF | 100nA | |
| 74HCT4053D,112 | Nexperia USA Inc. | 0.48 | 120Ohm | 6Ohm | 4.5V ~ 5.5V | ±1V ~ 5V | 34ns, 31ns | - | 3.5pF | 100nA | |
| HEF4053BT,652 | Nexperia USA Inc. | 0.44 | 155Ohm | 5Ohm | 3V ~ 15V | - | - | - | 7.5pF | 200nA | |
| http://www.onsemi.com/pub/Collateral/MC74HC4051A-D.PDF (http://www.onsemi.com/pub/Collateral/MC74HC4051A-D.PDF) | MC74HC4053ADG | ON Semiconductor | 0.5 | 100Ohm | 10Ohm | 2V ~ 6V | ±2V ~ 6V | - | - | 50pF | 100nA |
| http://www.onsemi.com/pub/Collateral/MC74VHC4051-D.PDF (http://www.onsemi.com/pub/Collateral/MC74VHC4051-D.PDF) | MC74VHC4053DR2G | ON Semiconductor | 0.6 | 100Ohm | 10Ohm | 2V ~ 6V | ±2V ~ 6V | - | - | 50pF | 100nA |
| http://www.onsemi.com/pub/Collateral/NLAS4053-D.PDF (http://www.onsemi.com/pub/Collateral/NLAS4053-D.PDF) | NLAS4053DR2G | ON Semiconductor | 0.71 | 26Ohm | 10Ohm | 3V ~ 5V | ±3V | 23ns, 23ns | 12pC | 10pF, 10pF | 100nA |
| http://www.onsemi.com/pub/Collateral/MC14051B-D.PDF (http://www.onsemi.com/pub/Collateral/MC14051B-D.PDF) | MC14053BDR2G | ON Semiconductor | 0.43 | 280Ohm | 10Ohm | 3V ~ 18V | - | - | - | 7.5pF | 100nA |
| https://www.renesas.com/en-us/www/doc/datasheet/isl84051-52-53.pdf (https://www.renesas.com/en-us/www/doc/datasheet/isl84051-52-53.pdf) | ISL84053IBZ | Renesas Electronics America Inc | 1.98 | 100Ohm | 6Ohm (Max) | 2V ~ 12V | ±2V ~ 6V | 50ns, 40ns | 2pC | 3pF, 9pF | 2pA (Typ) |
| http://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=http%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fcd74hc4051 (http://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=http%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fcd74hc4051) | CD74HC4053M | Texas Instruments | 0.55 | 130Ohm | 5Ohm | 2V ~ 6V | ±1V ~ 5V | - | - | 8pF | 100nA |
| http://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=http%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fcd74hct4051 (http://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=http%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fcd74hct4051) | CD74HCT4053M | Texas Instruments | 0.55 | 130Ohm | 5Ohm | 4.5V ~ 5.5V | ±1V ~ 5V | - | - | 5pF, 8pF | 100nA |
| http://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=http%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fcd4051b (http://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=http%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fcd4051b) | CD4053BM | Texas Instruments | 0.5 | 240Ohm | 5Ohm | 3V ~ 20V | ±2.5V ~ 9V | - | - | 0.2pF, 9pF | 100nA |
| http://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=http%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fcd4051b (http://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=http%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fcd4051b) | CD4053BNSR | Texas Instruments | 0.46 | 240Ohm | 5Ohm | 3V ~ 20V | ±2.5V ~ 9V | - | - | 0.2pF, 9pF | 100nA |
| http://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=http%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fcd4053b-q1 (http://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=http%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fcd4053b-q1) | CD4053BQM96G4Q1 | Texas Instruments | 0.53 | 240Ohm | 5Ohm | 3V ~ 20V | ±2.5V ~ 9V | - | - | 0.2pF, 9pF | 100nA |
| http://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=http%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fsn74lv4053a (http://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=http%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fsn74lv4053a) | SN74LV4053AD | Texas Instruments | 0.59 | 75Ohm | 1.3Ohm | 2V ~ 5.5V | - | 14ns, 14ns | - | 0.5pF, 8.2pF | 100nA |
| https://toshiba.semicon-storage.com/info/docget.jsp?did=54976&prodName=74HC4053D (https://toshiba.semicon-storage.com/info/docget.jsp?did=54976&prodName=74HC4053D) | 74HC4053D(BJ) | Toshiba Semiconductor and Storage | 0.4 | 100Ohm | 5Ohm (Typ) | 2V ~ 6V | - | 38ns, 38ns | - | 5pF | 100nA |
| https://toshiba.semicon-storage.com/info/docget.jsp?did=54977&prodName=74HCT4053D (https://toshiba.semicon-storage.com/info/docget.jsp?did=54977&prodName=74HCT4053D) | 74HCT4053D(BJ) | Toshiba Semiconductor and Storage | 0.4 | 110Ohm | 5Ohm (Typ) | 4.5V ~ 5.5V | - | 45ns, 59ns | - | 5pF | 100nA |
| http://www.vishay.com/docs/69685/dg4051e.pdf (http://www.vishay.com/docs/69685/dg4051e.pdf) | DG4053EEY-T1-GE3 | Vishay Siliconix | 1.49 | 78Ohm | 910mOhm | 3V ~ 16V | ±3V ~ 8V | 75ns, 88ns | 0.3pC | 2pF, 3.1pF | 1nA |
RUNUP:
SWITCH SWITCH_VIN //2 clock cycles
//----------------- We are counting clocks from here down
// Clock cycle accurate delay
DELAY (INTEGRATE_TP/2)-4 // compensate for the next switch
RUNUP_LOOP:
SWITCH_TOGGLE SWITCH_TOGGLE_CURRENT, SWITCH_TOGGLE_MASK, SWITCH_VIN //4 clock cycles
//-------------------- From here we are integrating VIN + VRP as start
// the next loop we are integrating VIN+VRN and toggle on a subsequent loop
DELAY us_to_cycles(1)-5 // 3 for jmp and 2 for switch
// If integrator is positive go to the needed slope
LOOP_IF_POSITIVE 1f //3 clock cycles
// The integrator is negative, we integrate VREFN to go positive
SWITCH SWITCH_VREF_N | SWITCH_VIN //2 clock cycles
//---------- From here we are integrating VREFN+VIN
DELAY us_to_cycles(20)-12
INCR SLOPE_COUNT_VRN //2 clock cycles
JUMP_IF IS_ONE(TIFR1, OCF1A), PRERUNDOWN //4 clock cycles
rjmp RUNUP_LOOP //2 clock cycles
// The integrator is positive, we integrate VREFP to go negative
1: SWITCH SWITCH_VREF_P | SWITCH_VIN //2 clock cycles
//---------- From here we are integrating VREFP+VIN
DELAY us_to_cycles(20)-12
INCR SLOPE_COUNT_VRP //2 clock cycles
JUMP_IF IS_ONE(TIFR1, OCF1A), PRERUNDOWN //4 clock cycles
rjmp RUNUP_LOOP //2 clock cycles
PRERUNDOWN:
// When we exit the runup loop we exit with 6 missing clock cycles from a full integration slope period
// 2 for rjmp and 4 for the new switch toggle, compensate for that in the switch and extra delay
DELAY 4
// Make sure we are above 0
// Integrate -VREF So we go in a positive direction until we go above zero
SWITCH SWITCH_VREF_N //2 clock cyclesWow, that's sounds great. I believe we have enough room to put everything in place on one or even two levels if needed: e.g. ADC + MCU + Power on base PCB and DMM stuff as piggyback.
Wow, that's sounds great. I believe we have enough room to put everything in place on one or even two levels if needed: e.g. ADC + MCU + Power on base PCB and DMM stuff as piggyback.
Would this still allow building a stand-alone unit in a minimal enclosure?
Wow, that's sounds great. I believe we have enough room to put everything in place on one or even two levels if needed: e.g. ADC + MCU + Power on base PCB and DMM stuff as piggyback.
Would this still allow building a stand-alone unit in a minimal enclosure?
Re Kleinsteins latest graph, a while back I spotted that the pattern you where using had certain ambiguous spots and seems to be roughly in the same spot I suspected, Perhaps alter the pattern slightly and see if it moves?
https://www.eevblog.com/forum/projects/multislope-design/msg2608230/#msg2608230 (https://www.eevblog.com/forum/projects/multislope-design/msg2608230/#msg2608230)
The noise is already very good and I now know the NOMCA resistors are a large part of it
So no need to have the winding as primary - secondary - primary.They do not have that either. All they have is a secondary, sitting between two (not shorted) layers of copper tape (grounded) serving as electrostatic shield.
The efficiency may not be great, but probably still better than the loss from linear created sine driveThey also point out that trapezoidal drive works the same. They say that pretty much anything without discontinuities should work.
With the aim of little capacitance to ground, there is only a limited effect of a common mode choke.
A 50 Hz power supply i made recentlyWell, duh! :)
I initially had a fast version that was at around 200 µs for the conversion (and still good resolution) - but the data transmission separate. So a speed up to some 5000 SPS should be possible. For the very fast conversions the integrated ADCs definitely have some advantage.Do you have the design? Also would you please share the eagle files too?
I currently have a 20 ms integration time and thus some 40.4 ms time for an auto zero cycle with 2 measurements. The theoretical / numerical resolution is at some 28-29 bits (depending on the gain used for the µC internal ADC). There is no real need for more resolution from the auxiliary ADC - I currently use some 8-9 out of 10 Bits.Kleinstein you told that your integration time is around 20ms, and I know that ATMEGA48 can be clocked at most 20MHz, so in 20ms the timer can count to the maximum of 400000, so how you get 28-29 bits resolution, since 400K is around 19 bit so what am I missing something in here?
The noise level is at some 850 nV_RMS with 50 K resistors (NOMCA) and some 450 nV with 20 K resistors (2xPTF56). This is close to 24 bit ENOB for 25 SPS, depending on the input range / front end. For comparison with SD ADCs one may have to look if the readings are independent. Some filters give kind of overlapping samples, like a running average filter.
Since it can count the time with 1GHz, it should give us about 100 times the speed, also they have way better ADC's, so the first part of it is to understand fully how your circuit is working, I think I should keep reading for some time. >:D
increasing the time resolution does only help if the clock stability is maintained.
Usually those parts have PLLs which are much less stable than a XTAL clock or Oscillator.
As I have seen with my 10V LM399 experiments the clock stability
has a large influence on stability of the analog part.
To work in assembler with timing by cycle counting may be some thrill, but not very productive.If you are inspecting code in great detail to ensure it will unconditionally meet a deadline, allowing for all the caching, and collision resolutions, you may well be doing something productive. If you are trying to get the code to unconditionally make an event happen on an exact machine cycle, you really should look at getting the peripherals to do that timing instead.
Our MSP430s work like this. For example the hardware will sample waveforms on various ADC inputs and save them to RAM without CPU action.
I think a typical STM32 datasheet is ten times the size of a MSP430 datasheet.
That's why i wanted to mention MSP430 - still a nice product.
Can't understand your comments in this context.
Using MSP430 may be a path for Kleinstein, who is currently stuck with AVR, while using Arm technology may be unrealistic for him. Of course it's up to him.
Can't understand your comments in this context.
I do not understand what you do not understand. You think all ARM MCU's have complex peripherals as stm32 of your choice? - You are mistaken. There's MSP432 - ARM MCU with peripherals of msp430 and documentation of comparable size/weigth.QuoteUsing MSP430 may be a path for Kleinstein, who is currently stuck with AVR, while using Arm technology may be unrealistic for him. Of course it's up to him.
Exactly. You will not be one deciding which MCU is too complex for Kleinstein and which is not.
I am not really stuck with the AVR - it is working. I doubt the INL comes from the µC type - more like a layout question and maybe the clock.
I want to learn about the STM32 anyway - I even already have a cheap Nucleo board there. The question is a little wether to test the ADC first, or get a board ready before the Chinese new year. with a slight chance that the SW will not work as planed.
I am not really stuck with the AVR - it is working. I doubt the INL comes from the µC type - more like a layout question and maybe the clock.
INL could come from software-induced jitter. I am not familiar with what and how you are doing things on AVR, but to say obvious - running timing-critical stuff in software is challenging. I would suggest to add some GPIO "logical debug trace" outputs to look at the timing of ADC code using multichannel scope, see if there is any unwanted jitter.
The problem is more subtile
The problem is more subtile
Just a (silly) idea: perhaps you should introduce "symmetrically" switching on the port pins.
So when one pin does a rising edge another compensates this by creating a falling edge (on the same port of the controller).
with best regards
Andreas
The jitter type error is way smaller than a clock cycle. 1 cycle wrong would result in some 50-100 µV error. That would be very visible.
Now comes the question: how to improve one the clock circuit. I have a old style DIP14 size) canned oscillator with a local 100 nF cap and 39 ohms + a ferrite bead isolation from the 5 V supply. Adding an extra electrolytic cap to the oscillator supply did not change anything. The clock goes to the µC with short (~10 mm trace) and some 30 mm bodge wire to 2 74HC74 Flipflops. Does one need an extra buffer or added load capacitance ?
For the next PCB version the oscillator would likely be 3.3 V and smaller and closer to the flipflops and maybe a little longer to the µC.
Probably not it, but I wonder if there might be problems with setup/hold times on the flip flops. If the uC output toggles too close to the clock edge the flip-flop may do odd stuff
PS: fyi - atmegas have got 2FF synchronizers at their I/O pins, so there could be a random delay, when you are messing with input edges..
PS: fyi - atmegas have got 2FF synchronizers at their I/O pins, so there could be a random delay, when you are messing with input edges..
Very good point actually. Many MCU's latch input signals with peripheral clock meaning worst case jitter equals 1/Fclk.
The weak point seems to be more like coupling troung the supply or ground, so that something effects the oscillator itself.It could be, could be not. I would test - disconnect existing oscillator, build external osc powered from AA batteries + cap, no LDO. Connect it through coax + decoupling cap, look for difference if any.
[...] nearly looks like one may need a VNA to do DC precision design.
[...]
The funny part was that the initial version of the ADC was working surprisingly good, with the analog part on a bread-board.
Take a look at this chart of 100 samples. Left and right part of the chart run at constant integrator average voltage, arrows represent 3 events where it flips back and forth. If the input voltage happens to fall in the right spot, the described effect can swamp other noise sources. At the moment this is the most significant noise source in my ADC project when measuring around 0V. Stable chart regions are around 450nV RMS (without AZ), frequent flipping can increase noise to ~800nV RMS. Estimated DA recharge of my capacitor is 150ppm for 20ms charge time.
This may be the point of worst DNL error.I agree. I did some preliminary tests with a slowly slewing input voltages as well as theoretical runup simulations and this seems to be the worst region.
Even if one has no switching at the input yet, one can use the difference of adjacent samples (the first point of the Allan deviation curve) as an approximation of what the AZ mode would look like.The noise in simulated AZ mode is around 600-650nV rms, perfectly fine. I refrained from implementing AZ until I resolve the runup issue - the discontinuity happens to be right in the spot where AZ measurement is being done at 1PLC. The result is a noise increase up to ~0.9-1.5uV no matter what the input is. The chart above is a measurement of a small voltage at the input. I can keep applying bandaids and shift the problematic region a bit but I don't think it's the correct approach.
150 ppm DA for the capacitor already looks reasonable good. The number depends on both the charging and discharging part, so one usually has at least 2 times involved - so the comparison of just the number is difficult without knowing the exact conditions. I think I got lower DA with a C0G cap from TDK - they are not even expensive.Thanks for the recommendation - I am using that TDK cap I believe, at least the same series. I can recall the DA testing chart you published - what was the discharge time in your test, same as the charge time? My estimation came from observing runup patterns and their effects, I'm yet to perform standalone DA testing. Selecting a better cap alone might not be enough to mitigate DNL/INL errors related to the average integrator voltage as this DA performance is already close to what the best C0G/teflon caps achieve. It would be a good idea to reduce known and controllable error sources as much as practical.
I would not be so sure the error at the critical point is only from DA. There are other parasitic effects that change at the same point and can contribute to the error.Which effects do you have in mind? Offsetting the comparator threshold voltage by 2V or more doesn't seem to reduce the error, so it might not be related to the sign of the integrator average. On the spot I can't think of any other sources that would be equally significant.
:) JFET-Frontend based on a existing known design like 34420A i expect? Or is it something of your own cooking?
I think it makes good sense to develop 2 different designs and to learn from differences.Having 2 "designs" and look at the differences is a nice way to look at INL effects. Already just slightly different modulation is enough to move nonlinear effects to a different voltage and thus create a visible difference from 2 reading with essentially the same HW, but lightly different control. It is a nice and simple (no need for an expensive super linear calibrator) test for my MS design. Chances are this could also work with a DS design, if there is room in the FPGA. Compared to classic INL tests this can be fast and quite sensitive, though not catching all.
Just today I found that I missed the introduction of the switch TMUX1133 of Texas Instr. (2019). Assuming that I understand the datasheet correctly, this SPDT would be excellent for DS-ADCs - with the exception of the reference voltage limitation to +/-2.5V. This part seems to include a much faster unipolar-->bipolar digital level translation than with 74HC4053. I'm afraid that I have to redesign of my PCB layout to paste this new IC into the ADC circuit hoping that it is worth for the additional work. Unfortunately, the tight dynamic demands exclude alternative switches in the layout (there are no packages common to 74LV4053 and TMUX1133).
.. Both the LV4053 and TMUX1133 are limitd to low voltage. So they are OK for switches at the intgrator input, but would limit the ref. voltage to some +-2.5 V. With a low ref voltage settling and the integrator noise get more important. The S/N ratio for the resistor contribution scales with the power - so one would also need a higher current to get the same noise level. A higher voltage really makes it easier on the amplifiers: less sensitive to noise, less current and less critical settling level. The downside of switching at the intgrator side is that there is additional kt/c noise from the gate charge. This can be a problem with very fast modulation. So switching on the voltage side gets more attractive with very fast modulation.
I found the LV4053 sufficient low resistance for the 280 µA current level I use, so no real need for even lower R_on. It may be requited if a 2.5 V ref is set and a higher current (e.g. 1 mA) is used.
My latest version has 3 different run-up versions to choose. The basic one (AFAIK also used similar by Jaromir and in the 34401) is really simple, but still good:As far as i understand this is the description of a PWM DAC running at 100 KHz and with only two pulse widths (10% and 90 %). It is made into an ADC by a sigma-delta type control loop that lets it follow the input signal.
each period of the run-up has 3 phases:
1) a phase with the positive reference (e.g. 1 µs)
2) a phase with a ref. Setting that depends on a single comparator reading (e.g. some 8 µs)
3) a phase with the negative reference (e.g. 1 µs)
So there are only 2 cases. ...
if (ru_count)
{ // normal ru-up step
if ((COMP2->CSR & COMP_CSR_COMP2VALUE)) // test comparator
{
TIM2->CCR1 = ru_high; // PWM registers for the references: positive is active at the end, negative is active at start
TIM2->CCR2 = ru_high; // switch late -> more negative ref. , uses preload: effective only for next period
}
else
{
TIM2->CCR1 = ru_low; // switch early on both, more positive phase
TIM2->CCR2 = ru_low;
ru_sum++; // count number of positive phases
}
ru_count--;
}
else
..... // run-down part
.. The board shown on the photo has the ADC and a voltmeter input stage.The board is nice but already more complex (number of parts) than my 34401, it seems.. :D
The MUX itself should not create much overshoot. It is possible that the buffer creates some obershoot / slow settling. An amplifier with bootstrapped supply is always a bit tricky with the stability / settling. I would expect the overshoot more from the buffer than the mux. Anyway for looking at the noise offset drift of the ADC only, one could use the case where the input signal is not connected to the ADC, so the 4053 channel allways off (modus T).
The integrator waveform looks as expected.
To get low noise, the values for the slow slope (sum) and aux ADC should be reasonable correct.
The slow slope part looks reasonable, though the result of the k1 measurement shown is 20.88 while the other files use 20.90. This is not far off, and should not cause that much different in noise. The part with K2 seems to be not working. So there seems to be something wrong with the residual charge measurement. The reading of the µC internal ADC look suspiciously constant at 506. So there may be a problem with the last amplification step (MCP6002 ?). So far this is kind of only the classicl MS ADC without a working res. charge measurement for the last bit of resolution.
It looks a bit, like the ADC channel that is supposed to read the residual ADC reads something different, like the scaled down input voltage or maybe the average integrator voltage. So there may be a small difference in the plan, like using different ADC channels / pins at the µC.
Which is the schematics for the PCB used ?
An interesting signal to look at is the ouput of the slope amplifier (NE5534). This signal should be about -700mV to 1400 mV near square wave in the runup, and somewhere in the 0 - 400 mV range after the rundown part and slightly, variable ( ~50 mV) between conversions. The trimmer will effect the level where the signal be approximately.
The DA test part seems to be net yet correct/fully implemented in the new Pascal program. I think I never used it with the new program. This part is more like an extra if everything else works. It can be used to check the cap qualtiy and see leakage currents at the integrator.
241: {DA-Test 26 chars}
begin
write('DA result: 0x');
das := '0x';
for n := 0 to 25 do
begin
da[n] := ord(Readcom);
write(IntToHex(da[n]),' ');
das := concat(das, IntToHex(da[n]));
end;
writeln('');
writeln(f, das);
}
end;
I looked at the schematics, and it looks like the AD0 and AD1 signals are swapped: I have the residual charge signal at AD1, rerouter has the resudual charge signal at AD0. So this would need a slight modification to the software.
As far as I have found there are only 3 accesses to the chanel choice of the µC internal ADC (register ADMUX) in the program. So ideally define a 2nd constant for the ADC setting and than use this instead of "ADMUXval-1" .
p.s. :
the waveforms for the slope amplifier out and MCP6002 out look good - so likely just the ADC channels swapped.
Could you calc the stddev from 800secs up till the end, plz?The std. dev (RMS noise) for the 800s to 1500s part is 0.045 ppm which is 315 nV for the voltage reading.
..For some reason I don't know the usual DMMs don't inlcude much reference filtering, though this is a relatively simple way to reduce the noise a little. Usually the effect is smaller than here, because not many combine a very low noise ADC with a relatively noisy reference (LM399).Something like this (34401A)? Not sure the resistor there would be a good idea - would need adjusting, imho..
Changed mux7 from Nr. 5 (S6 buffered 7V) to Nr. 6 (S7 unbuffered 7V) - there is no buffered 7V awailable
Refined comments on mux0/1/Temp
--------------------------- Multislope ADC/main.asm ---------------------------
index 5df8705..f61ee93 100644
@@ -91,10 +91,10 @@
#define portMUX portc ; MUX port , rest is input, e.g. ADC inputs
; mux setting, including fixed part (currently 0)
-#define mux0 8*7 ; Mux channel for 0 V = Nr. 7
-#define mux7 8*5 ; mux channel for 7 V ref = Nr. 5 = buffered 7 V
-#define mux1 8*2 ; mux channel 2
-#define muxTemp 8*4 ; mux channel for diode (Temp) = Nr. 4
+#define mux0 8*7 ; Mux channel for 0 V = Nr. 7 (S8 = GNDS)
+#define mux7 8*6 ; Mux channel for 7 V ref = Nr. 6 (S7 = unbuffered 7V)
+#define mux1 8*2 ; Mux channel for Input3 = Nr. 2 (S3 = J2 Pin 3)
+#define muxTemp 8*4 ; Mux channel for diode = Nr. 4 (S5 = Temp)
.equ ADcontr = (1 << aden) + (1<< ADSC) + (1<<ADIF) + 6 ; ADC enable + start + Flag (to clear) + clock / 64 (6 -> 125 kHz bei 8 MHz)
Use external Ref for ATMEGA ADC
--------------------------- Multislope ADC/main.asm ---------------------------
index f61ee93..9e33073 100644
@@ -101,7 +101,7 @@
; include Interrupt flag to clear flag on start
.equ ADcontrStop = 7 ; Disable ADC, set ADC divider to different values
-.equ ADMUXval = 1 + 64 ;ADC channel (1) + Ref. (64=VCC , 192 = internal , 0 = external)
+.equ ADMUXval = 1 + 0 ; ADC channel (1) + Ref. (64=VCC , 192 = internal , 0 = external)
Swap ADC0 and ADC1 (change in rev of Kleinstein)
--------------------------- Multislope ADC/main.asm ---------------------------
index 9e33073..3c51ea1 100644
@@ -96,13 +96,15 @@
#define mux1 8*2 ; Mux channel for Input3 = Nr. 2 (S3 = J2 Pin 3)
#define muxTemp 8*4 ; Mux channel for diode = Nr. 4 (S5 = Temp)
+; ATMEGA ADC setting ADMUX – ADC Multiplexer Selection Register
+#define REFS 0 ; Reference Selection Bits (0 = external, 64=VCC , 192 = internal)
+#define ADMUXICh 0 + REFS ; ATMEGA ADC input channel for integrator charge level - output of U13B (ADC0 = 0 ... ADC7 = 7)
+#define ADMUXSlp 1 + REFS ; ATMEGA ADC input channel for slope output level - output of U13A (ADC0 = 0 ... ADC7 = 7)
.equ ADcontr = (1 << aden) + (1<< ADSC) + (1<<ADIF) + 6 ; ADC enable + start + Flag (to clear) + clock / 64 (6 -> 125 kHz bei 8 MHz)
; include Interrupt flag to clear flag on start
.equ ADcontrStop = 7 ; Disable ADC, set ADC divider to different values
-.equ ADMUXval = 1 + 0 ; ADC channel (1) + Ref. (64=VCC , 192 = internal , 0 = external)
-
start:
@@ -120,7 +122,7 @@ start:
; ADC initializing
ldi temp, ADcontr ; ADC config mit start
sts ADCSRA,temp
- ldi temp, ADMUXval ; ADC channal + speed + Ref. . for AVCC ref. (no link needed)
+ ldi temp, ADMUXICh ; ADC channal + speed + Ref. . for AVCC ref. (no link needed)
sts ADMUX,temp
ldi temp, 1+2 ; Disable digital input for ADC inputs 0 and 1
@@ -955,7 +957,7 @@ mslope2: ; call point for just data collection of rundown
st x+,coutBL
rcall readAD_wait ; ADC right after rundown;
- ldi temp, ADMUXval -1 ; MUX to auxiliary (for next conversion)
+ ldi temp, ADMUXSlp ; MUX to auxiliary (for next conversion)
sts ADMUX,temp
lds temp,par_syncdel ; extra delay to check delayed effect (some gets hidden by wait for ADC)
@@ -963,7 +965,7 @@ mslope2: ; call point for just data collection of rundown
rcall fullADC ; 2nd reading for simpler data format , make drift visible (e.g. DA)
- ldi temp, ADMUXval ; MUX to res charge
+ ldi temp, ADMUXICh ; MUX to res charge
sts ADMUX,temp
Local uncommitted changes, not checked in to index
--------------------------- Multislope ADC/main.asm ---------------------------
index 3c51ea1..34272bc 100644
@@ -54,7 +54,7 @@
#define par_syncdel 0x105 ; delay in ADC sync (for testing)
#define par_runup_ver 0x106 ; runup version
-#define F_CPU 12000000
+#define F_CPU 16000000 ; Clock frequency of µC - change accordingly
#define BAUD 9600 ; should be more than about 8000 Baud to transmit data during 20 ms conversion
#define UBRR_BAUD ((F_CPU/(16*BAUD))-1)
Slow down ATMEGA ADC conversion by 2
--------------------------- Multislope ADC/main.asm ---------------------------
index 3c51ea1..4ca82e4 100644
@@ -101,7 +101,7 @@
#define ADMUXICh 0 + REFS ; ATMEGA ADC input channel for integrator charge level - output of U13B (ADC0 = 0 ... ADC7 = 7)
#define ADMUXSlp 1 + REFS ; ATMEGA ADC input channel for slope output level - output of U13A (ADC0 = 0 ... ADC7 = 7)
-.equ ADcontr = (1 << aden) + (1<< ADSC) + (1<<ADIF) + 6 ; ADC enable + start + Flag (to clear) + clock / 64 (6 -> 125 kHz bei 8 MHz)
+.equ ADcontr = (1 << ADEN) + (1<< ADSC) + (1<<ADIF) + 7 ; ADC enable + start + Flag (to clear) + ADC Prescaler clock (6 = /64 -> 125 kHz bei 8 MHz, 7 = /128)
; include Interrupt flag to clear flag on start
.equ ADcontrStop = 7 ; Disable ADC, set ADC divider to different values
xd = 1000*3; // extra delay 3x xdel in ASM codeThe Q2 and Q8 part at the Ne5534 is a bit odd. I had not so great experience with transistors as diode and for the ARM version use 3 diodes that work quite well. The BAS21 seems to be a good compromise between leakage and recovery time for the 1 critical diode. The other 2 can be simple fast ones (e.g. 1N4148 / BAV99). With just 3x 1N4148 the weak point is dirft of the gain (likely temperature dependent leakage). With a transisistor instead of 1 diode the problem with relatively large drift of the DC level / trimmer position, likely from slow recovery. With a relatively low gain for the final amplifier the drift of the DC level may be still acceptable.
Concerning the jitter of the µC: Awoid or check the internal PLL.... usually a cheapo BangBang ..... have seen nice sawtooths in the f_cpuclock/timer over time ..Hello,
Meanwile the board got different XO (cheap Reichelt (https://www.reichelt.de/quarzoszillator-16-00-mhz-oszi-16-000000-p13686.html?&nbc=1)) and noise got a lot worse - around x2 (4µVacrms vs. 2µVacrms prior XO).
Seems the XO has quite high influence on noise - @Kleinstein, which one do you use?
The FW always had delay 12, but missed to change it in Pascal program :palm:
Did comparison of delay 12 & 0 in program with cheap XO and as proposed the noise with delay 0 is around 2x (4µVacrms vs. 8.1µVacrms) - this applies to the diff to the expected value as well (5.3µV vs. 10.3µV for short).
One thing I want to try is to have more delay after DG408 input mux switching, but have no idea where what to change.The Q2 and Q8 part at the Ne5534 is a bit odd. I had not so great experience with transistors as diode and for the ARM version use 3 diodes that work quite well. The BAS21 seems to be a good compromise between leakage and recovery time for the 1 critical diode. The other 2 can be simple fast ones (e.g. 1N4148 / BAV99). With just 3x 1N4148 the weak point is dirft of the gain (likely temperature dependent leakage). With a transisistor instead of 1 diode the problem with relatively large drift of the DC level / trimmer position, likely from slow recovery. With a relatively low gain for the final amplifier the drift of the DC level may be still acceptable.
BAS21 diodes are in the pipe (with some other components) to try out.
#define rundown_wait 200 ; Length für rundown (256 cyles = 16 µs units) standard = 6I took one datafile (3R short P-Q-R-V-W Runup.txt) and did a correction of the k2 factor from the raw data. This way kind of cheating - fitting K2 to give the least correlation of the resuadual ADC readings with the result and thus about the lowest noise.
Looking at just the columns 10 or 11 also support the wrong K2 values assumption: the difference from the min to max value is a bit over 120 and no way reaching 150.
The noise goes down to to 0.78 µV rms over the data, excluding the start with mode "P", that shows more noise
This is a reasonable good noise value. Chances are just taking the slow modulation case (mode W) would give lower noise.
adcclock = 12000000; // clock on ADC board
scale = 6951.95; // Ref voltage in mV 7106.8384
xd = 12*3; // extra delay 3x xdel in ASM code !!! has to match FW !!!
k1 = 1.0 / 20.96333; // measured ref ratios from adjustment - was formerly 20.9638
k2 = 4.0/ 121.74; // fine step / adc LSB - was formerly 148.5A next part to check would be the linearity.
What software is used to generate the histogram plots ?
157945.754 153131.211 4814.537 -33 591 412 352 768 694 695 1221 524 340 867 723 690
157945.759 153131.240 4814.533 -15 591 412 352 768 715 719 1221 524 340 867 725 710
157945.762 153131.196 4814.544 -43 591 412 352 768 715 721 1221 524 340 867 753 710
157945.738 153131.206 4814.538 85 591 412 352 768 758 749 1221 528 344 867 668 753
157945.735 153131.191 4814.537 -46 591 412 352 768 676 665 1221 524 340 867 718 672
157945.735 153131.179 4814.550 68 591 412 352 768 727 716 1221 528 344 867 655 723
157945.713 153131.175 4814.536 -56 591 412 352 768 677 652 1221 524 340 867 728 672
157945.727 153131.202 4814.539 83 591 412 352 768 740 724 1221 528 344 867 651 734
157945.745 153131.158 4814.564 -67 591 412 352 768 652 647 1221 524 340 867 715 648
157945.723 153131.160 4814.564 56 591 412 352 768 731 712 1221 528 344 867 671 727
157945.710 153131.174 4814.543 -57 591 412 352 768 695 668 1221 524 340 867 747 690
dU = RAWdU * 56µV + 840504µVThe test resuslt looks quite good. The curve is quite linear, with most of the time less than 1 µV deviation from a straigth line. The slope kind of reprensts an effect from the no perfect settling in the short pulses. There is not much slope, especially for the integrator with the relatively slow OPA145.
There is a little "resonance" like structure near -0.7 V and 3 V. This are likely the regions close to stable simple run-up patterns.
So things look good and there is a good chance to get low INL. (e.g. 0.1 ppm FS range for the hard INL part).
The other polarity could complete the picture and allow a more meaningful line to subtract.
dU = RAWdU * 56µV + 840504µVIf the circuit is still with the "original" R10 = 6.8 K the settling of the integrator is still quite slow. The slower OPA145 would more like a smaller value for R10 (e.g. 4.7 K or 3.3 K) to speed up the settling. With warm up the speed of the OPA145 may change, and this can than effect the settling and indirectly the ADC gain a little, especially for the faster runup mode Q. So the bend may be a warm up effect - though ususally this should be smaller for 2 RU modes with the same frequency. The settling has more effect on the modes with higher frequency and shorter pulses - so the later used case (e.g. V or W) are likely the better ones in the comparison. It is mainly the DA related error that gets worse with slower modulation.
The DG408 multiplexer gives quite some current spike at the inputs, when switching between different voltages. Not sure of this is the amplifier or the CMOS switch…
For the difference test with 2 run-up modes shown earlier, the 2 cases to compare may have been a bit too similar and the result thus a bit too optimistic. With more different run-up modes the difference looks a little worse, but still not too bad. The plot in the attachment shows 2 cases with different modulation frequency ( 23.5 and 61.5 kHz). The run-up parts are a bit more different and especially with some offset relative to each other. The slower modulation curve looks a little better, but not much.
The idea of the comparison at different modulation frequencies is that errors due to DA get smaller with a faster modulation. Errors from switching related interference should get larger with faster modulation. The curves look different, but no clear pointing to one culprit. It looks more like a combination of both types of error: The more shorter range periodic like part (e.g. at abound -300 mV and -1.5 V) seem to be stronger with the slow modulation (this would point towards DA).
(https://www.eevblog.com/forum/metrology/diy-high-resolution-multi-slope-converter/?action=dlattach;attach=1311014)
I got a first higher resolution test for the difference of 2 variations of the run-up. So the same, slowly changing voltage (capacitor charge and discharge) is measured with 2 different versions of the run-up. Ideally the 2 versions would get the same result, but the details can vary, e.g. due to errors from DA in the integration capacitor and also coupling effects at the clock. One can see the curve (deviations from a stright line) as indication for the more wiggly parts to the INL. INL from the amplifier, ADC input buffer and thermal effects (e.g. in the resistors) are not included. The main effects included are DA, integrator input settling and unwanted electrical coupling / supply variations.
Compared to a classic INL measurement this test is easy (not much extra instruments needed) and relatively fast (some 3 h for the curve), but still quite sensitive (low noise).
The curve is still not perfect, but allready quite good and better than in the AVR based version. The improvment is not from the different µC, but more with a better layout / better decoupling. Using a slower modulation may also be part of it: so decoupling gets less important but DA gets more important.
The points are the average over 192 conversions or 2x20 ms each.
(https://www.eevblog.com/forum/metrology/diy-high-resolution-multi-slope-converter/?action=dlattach;attach=1276333)
The curve is still not perfect, but allready quite goodis a bit understatement, with linear regression by eye the wiggly part would be in the order of +-0.3µV = +-0.03ppm - what is your goal?
Are the measurements still with R10 = 6.8 K ? This would be with a relatively slow settling integrator. With the OPA145 a smaller value (like 3 K to 5 K) for R10 would be more appropriate. This would especially make a difference for the mode P with rather short time for settling. Overall the shape is similar what I have seen.
A real INL test to a 3458 would be interesting. With the relatively noisy LM399 ref. this may still take some time for averaging. So for the voltage source there is no need to have a much lower noise one, especially if the readings are at the same time. The tricky point are the jumps from popcorn noise of the LM399. To suppress this low frequency noise one would ideally run through the sequence of test voltages several times and not just every voltage once.
For the start the interesting points would be a general overview (e.g. 1 V steps) and than maybe the readings around 0.6 V, where the DIY ADC is likely weakest.
For the start the Python program to read the data could get away with only the normal measurements. The small slope part is not needed very often and one of the more complicated parts.
Discovered an unexpected effect regarding the 0V offset in 3 readings mode (AZ+AS).Just looked at schematics for first time - signal 'Res_adc' must to be decoupled with at least 10nF as close as possible to uC pin. Please follow the STM AN.
If the input is set to the same 0V used for AZ (S8), expectation is to read ~0µV avg, but it is ~6µV avg (run-up W).
The input mux switching (In 0V 7V) occurs after the run-down is finished and before the µC ADC reads the residual charge.
Switching the input mux after reading residual charge the result is ~0.4µV avg.
With 7V (S7) it changes from ~-7µV to ~+7µV relative to expected value.
Discovered an unexpected effect regarding the 0V offset in 3 readings mode (AZ+AS).
If the input is set to the same 0V used for AZ (S8), expectation is to read ~0µV avg, but it is ~6µV avg (run-up W).
The input mux switching (In 0V 7V) occurs after the run-down is finished and before the µC ADC reads the residual charge.
Switching the input mux after reading residual charge the result is ~0.4µV avg.
With 7V (S7) it changes from ~-7µV to ~+7µV relative to expected value.
@@ -873,7 +873,7 @@ rundown:
out portSW,t2 ; start of Rundown: start with larger Ref.; Input off
; may need extra delay here (min length for phase)
ldi t2,control_neg
- out portMUX, nextmux ; change MUX for next conversion : DG408 is slower than 4053, so likely no extra delay needed
+ /*out portMUX, nextmux ; change MUX for next conversion : DG408 is slower than 4053, so likely no extra delay needed */
LDI temp,1 ; timer1 start (already 0 and OC1A flag cleared in runup prepare)
STS TCCR1B,temp
@@ -959,6 +959,8 @@ mslope2: ; call point for just data collection of rundown
rcall readAD_wait ; ADC right after rundown;
ldi temp, ADMUXSlp ; MUX to auxiliary (for next conversion)
sts ADMUX,temp
+ ; Debug change input mux after ADC readout
+ out portMUX, nextmux ; change MUX for next conversion : DG408 is slower than 4053, so likely no extra delay needed
lds temp,par_syncdel ; extra delay to check delayed effect (some gets hidden by wait for ADC)
rcall longdelay ; schon viel delay ! (startwert ist 26 -> 1.6 ms)| Input | | dev to 0V in µV | | -> in ppm (10V) | | dev to +-7V in µV | | -> in ppm (10V) |
| 7V orig FW | 19.7 | 1.97 | -27.7 | -2.77 |
| -7V orig FW | -12.9 | -1.29 | -19.0 | -1.90 |
| 7V adc first | 0.6 | 0.06 | -9.4 | -0.94 |
| -7V adc first | 0.3 | 0.03 | -5.5 | -0.55 |
Part of the settling one still sees after the step in the input voltage can be from DA.
In the non AZ mode this is stronger than in the more normal AZ mode, as effects from longer time scales are included. To a large part the effect from DA is linear and thus would in the AZ mode only lead to a slight (e.g. 0.5 ppm range) change in the gain.
| Input | | dev to 0V in µV | | -> in ppm (10V) | | dev to +-7V in µV | | -> in ppm (10V) |
| 7V orig FW | 19.7 | 1.97 | -27.7 | -2.77 |
| -7V orig FW | -12.9 | -1.29 | -19.0 | -1.90 |
| 7V adc first | 0.6 | 0.06 | -9.4 | -0.94 |
| -7V adc first | 0.3 | 0.03 | -5.5 | -0.55 |
| 7V adc first R/2 | 0.3 | 0.03 | -7.9 | -0.79 |
| -7V adc first R/2 | 0.2 | 0.02 | -5.3 | -0.53 |
The observed settling is a bit different for the +7 and -7 V case and thus nonlinear. For the small difference seen for the zero reading, there are a few poible nonlinear effects, like self heating in the resistor array at the integrator input. The heat can not only change the gain, but also cause an offset of the ratio of the 2 reference channels changes. A similar effect would also effect the +-7 V test cases. The observed difference between the + and - sign case is still quite a bit larger than at zero. So there is still a bit unclear about the mechanism behind this. There is some possible asymmetry with thermal effects from the buffer amplifier, but this should be rather slow. Settling after the charge injection spike at the input of the MUX may a factor - though this shuold be quite fast. Hard to tell how much is still there for the 2nd sample after the jump.
@@ -1053,10 +1053,11 @@ mslopeB: ; run multi-slope, 2 Runup versions for tests
ldi temp,255
st x+,temp ; Data are send during next runup, one ADC is ready
+ rcall mslope1 ; 2 nd conversion
- rcall runup_P3nF ; nromal mode
+/* rcall runup_P3nF ; nromal mode
rcall rundown
- rcall mslope2 ; data collecton 2nd conversion
+ rcall mslope2 ; data collecton 2nd conversion*/
rcall control ; Check UART
rjmp mslopeB@@ -283,11 +283,11 @@ def read2 (n): # 254, 251: 2 readings (modes A, B, E)
if n == 254:
u2 = readADC(k0[ruv]) # result of 2. conversion
du = u1 - u2
else:
- u2 = readADC(k0[1]) # result of 2. conversion, mode B for INL test
+ u2 = readADC(k0[ruv]) # result of 2. conversion, mode B for INL test
#du = u1-0.5*(u2+u2old) # TODO should be only for mode B? Or better avg 0V reading even for mode A/E?
du = (3*(u2old-u1)-u1old+u2)/4 # interpolate both values
#f.write('{:11.3f}\t{:11.3f}\t{:13.4f}\t{:6.0f}'.format(u1, u2, du*sf, adcdiff))
writeraw()| Input | | dev to 0V in µV | | -> in ppm (10V) | | dev to +-7V in µV | | -> in ppm (10V) |
| 7V orig FW | 19.7 | 1.97 | -27.7 | -2.77 |
| -7V orig FW | -12.9 | -1.29 | -19.0 | -1.90 |
| 7V adc first | 0.6 | 0.06 | -9.4 | -0.94 |
| -7V adc first | 0.3 | 0.03 | -5.5 | -0.55 |
| 7V adc first R/2 | 0.3 | 0.03 | -7.9 | -0.79 |
| -7V adc first R/2 | 0.2 | 0.02 | -5.3 | -0.53 |
The interpolation for AZ mode for case B is not so much for lower noise (as a kind of digital filtering, but mainly for the difference test, so that both versions get the value for the same time. So with 3 conversions V1,V2,V3 the first and last (using the same input / conversion mode) are averaged to get a values for the same time. This is needed for the linearity test to avoid an effect of the rate of change. For a normal reading in AZ mode, it would be possible to average 2 zero readings without an extended step response. So though actually using 2 PLC for the zero the response would be the same as 1 PLC, just with slightly lower noise and little extra latency compared to the zero and signal case.
# TODO should be only for mode B?was due to the fact that the pascal program interpolates in all modes A, B, E (see last line).
if n == 254:
u2 = readADC(k0[ruv]) # result of 2. conversion
du = u1 - u2
else:
u2 = readADC(k0[1]) # result of 2. conversion, mode B for INL test
#du = u1-0.5*(u2+u2old) # TODO should be only for mode B? Or better avg 0V reading even for mode A/E?
du = (3*(u2old-u1)-u1old+u2)/4 # interpolate both values
#f.write('{:11.3f}\t{:11.3f}\t{:13.4f}\t{:6.0f}'.format(u1, u2, du*sf, adcdiff))
writeraw() 254, 251 : // 2 readings (modes A, B, E)
begin
u1 := readADC(k0[ruv]); { result of 1 st conversion }
if n=254 then
u2 := readADC(k0[ruv]) { result of 2. conversion }
else
u2 := readADC(k0[1]); { result of 2. conversion, mode B for INL test }
du:=u1-0.5*(u2+u2old);Or better avg 0V reading even for mode A/E?It is not implemented and just an idea.
Apropos popcorn noise: In the above schematic C210 = 100 nF isn't ideal, as the LM399 zener pin is in fact an operational amplifier input and output at the same time. Better use a 50 Ohm resistor in series with the capacitor. Otherwise the circuit may exhibit RF instability, that may appear as popcorn noise.
A series resistor for a capacitor in parallel to the ref is definitely a good idea. Not sure if 50 Ohms is best - from the impedance curve with some 30 ohms at 100 kHZ my guess would be a little lower (e.g. 22 ohms), though not much.
To test for DA on the delayed/settling effect, the FW & control software was modified to run mode B in selected run-up version (formerly one of the two readings was done everytime in run-up Q):
Comparison of 3 run-up modes were done for P: fast, Q: normal, W: slow (P shows higher noise then Q, W lower)
@@ -1053,10 +1053,11 @@ mslopeB: ; run multi-slope, 2 Runup versions for tests
ldi temp,255
st x+,temp ; Data are send during next runup, one ADC is ready
+ rcall mslope1 ; 2 nd conversion
- rcall runup_P3nF ; nromal mode
+/* rcall runup_P3nF ; nromal mode
rcall rundown
- rcall mslope2 ; data collecton 2nd conversion
+ rcall mslope2 ; data collecton 2nd conversion*/
rcall control ; Check UART
rjmp mslopeB@@ -283,11 +283,11 @@ def read2 (n): # 254, 251: 2 readings (modes A, B, E)
if n == 254:
u2 = readADC(k0[ruv]) # result of 2. conversion
du = u1 - u2
else:
- u2 = readADC(k0[1]) # result of 2. conversion, mode B for INL test
+ u2 = readADC(k0[ruv]) # result of 2. conversion, mode B for INL test
#du = u1-0.5*(u2+u2old) # TODO should be only for mode B? Or better avg 0V reading even for mode A/E?
du = (3*(u2old-u1)-u1old+u2)/4 # interpolate both values
#f.write('{:11.3f}\t{:11.3f}\t{:13.4f}\t{:6.0f}'.format(u1, u2, du*sf, adcdiff))
writeraw()| Input | | dev to 0V in µV | | -> in ppm (10V) | | dev to +-7V in µV | | -> in ppm (10V) |
| 7V orig FW | 19.7 | 1.97 | -27.7 | -2.77 |
| -7V orig FW | -12.9 | -1.29 | -19.0 | -1.90 |
| 7V adc first RU Q | 0.4 | 0.04 | -7.4 | -0.74 |
| -7V adc first RU Q | -0.5 | -0.05 | -3.6 | -0.36 |
| 7V adc first RU W | 0.4 | 0.04 | -7.1 | -0.71 |
| -7V adc first RU W | -0.6 | -0.06 | -4.9 | -0.49 |
| 7V adc first RU P | 0.7 | 0.07 | -7.1 | -0.71 |
| -7V adc first RU P | -0.6 | -0.06 | -3.6 | -0.36 |
Is there a Github repostory linked to this thread?
The project for the ATMEGA version is now on github: https://github.com/Multi-slope-ADC?tab=repositories
Separated into four parts:
- PCB from Rerouter - BOM & additional information under Releases (https://github.com/Multi-slope-ADC/PCB/releases)
- Firmware
- ADC control program (Free pascal)
- ADC control program (Python)
The non AZ mode adds extra low frequency noise, but it also samples the input all the time and this redues the noise bandwidth. Longer sampling also helps with noise from 236 signal source and getting better correlation with the 3458 DMM. The noise of the DIY ADC is only one part of the total noise and the extra 1/f noise seems to quite low. With the 236 in the 1.1 V range the noise is already quite a bit lower and there the extra 1/f noise from the non Az mode than gets important.
The RMS noise calculated from the mutiple reading to average is more of the higher frequency noise and does not include the extra 1/f noise that effects the non AZ readings. So for the +-1 V range the non AZ mode reading get a lower RMS noise, but still shows the more jagged (noisy) INL curve. For the full range the difference may not be so relevant as there is more noise from the 3458 and the K236 source.
The 1/f noise would be visible in the difference between runs.
The choice of AZ and non AZ mode should also effect the INL error due to the slow part of the DA in the integration capacitor: In the Az mode there is a charge carry over between the signal and zero reading and thus from positive to a negative effect. This increases the INL effect for the intermediate time scales (e.g. around 20 ms). With the non AZ mode the carry over is between one conversion and the next, nearly negating the effect of slow DA, especially the intermediate time scales.
The very similar INL error for the AZ and non AZ mode thus suggests that the slow DA is not the dominant contribution to the INL.
At least in my SW version the modes V and Q use the same modulation frequency for the feedback, and the difference is only in the length of the shortest pulses. Here the mode V has longer min pulses (comes with the downside of a slightly reduced full scale range) and is less sensitive to integrator settling.
Even for the test in the +-1 V range some of the fine structure around -300 mV may be missed. With faster modulation the excursions in the INL are expected to also get more local ( e.g. half the horizontal scale for modes P and V compared to W). So it may be interesting to also have a more detailed curve (e.g. -360 to -260 mV) for the faster modulation to do the comparisons to the mode W (there is already a detail curve).
In principle one could add some dithering to the ADC, at least for the slower results (more than 1 PLC). For the initial phase one could add some offset (e.g. half a run-up step), like shifting the curve some 5 or 10 mV horizontally and than average. This could smoothen the INL curve and reduce the error from local effects quite a bit.
Sir, may I ask you compared with off shell commercial adc, why would us diy adc like hp do in 3458a? And have a conclusion of your project, compared with adc in 3458a, how this diy adc perform? I want to diy and share an open source dmm, and if I implement your adc design, how far it will go, 6.5 digit? Thank you very much sir.
I have an question
How the INL test performed?
- startup time / stabilization etc.
- steps sequence
- measurement equipment settings
- PC post processing.
- timing
- logging information - temperature , at which point to sense temeprature, humidity, atmospheric pressure
To many questions. Isn't it? :-) :)
PRESET FAST
DCV {int(range)} #10V or 1V, depending on range of source (constant over one run)
AZERO ON
TARM HOLD
TRIG SYN # only capture data on read
NPLC {int(nplc)}
FIXEDZ OFF
ARANGE OFF
NRDGS 1,SYN
MEM OFF
END ALWAYS
DELAY 0
TARM SYN # only capture data on read
F0,0XB{float(Source.start_value)/1000:7f},{Source.range_set},0X # Function: F0,0 = source V, B: Range setting 0 = Auto, 1 = 1V/nA, 2 = 10V/nA, 3 = 100V/nA, delay = 0 in ms
H0X # only with immediate trigger it sets the output
N1X # N1 = operate
O0P0Z0S3W0L10E-3,8X # other settings O0 = local, O1= remote sense, P5 = Filter 5 = 32 readings, Z0 = suppression disabled, S3 = 50Hz 20ms integration time, W0 = disable default delay, L compliance 0=auto range
[init()] #reset, initialise & gain corrections (k factors)
A # mode: A=AZ
[run-up] # run-up version W, Q, ...
[input_ch] # input channel of mux (0..7)
src_set_values = collections.deque() # list of values for voltage source (K236/7/8), each value for one ADC cycle
# +-11V
range_set = int(2) # range of K236/7/8 - 1: 1V, 2: 10V, 3: 100V, 4: 1000V
factor = int(10**(int(2-range_set))) # multiply start/stop value for stepping in range: 1: *10, 2: *1, 3: *0.1 = *10^(2-[range])
stop_value = int(12500) # gives ~11V on ADC input due to 4th order LPF (4x2x1kΩ, 4x220µF)
stop_value_range = int(stop_value*factor) # max value in range-steps of K236/7/8, for 10V range: factor = 1 (see factor)
#Staircase +-11V
for _ in range(5000): # 5000 * ADC cycletime initial value (~220s +11V)
src_set_values.append(stop_value_range/(1000*factor))
step = int(500)
repeats = 2
for _ in range(4): # generate staircase with steps of 500mV with 2x500 values for each step (440s) going from +11V .. -11V .. +11V repeated 4 times
for i in range(stop_value_range - step, - (stop_value_range + 1), -step):
for _ in range(repeats*step): src_set_values.append(i/(1000*factor))
for i in range(-(stop_value_range - step), stop_value_range + 1, step):
for _ in range(repeats*step): src_set_values.append(i/(1000*factor))
src_set_values.append(0) # set source to 0V
Any updates?Currently no real news:
-branadic-
He discussed his multislope design here (https://www.eevblog.com/forum/projects/(yet-another)-diy-multislope-adc/) and was also looking for help/support at MM2022. There are even some videos on youtube by him about his design.Ok, my bad.. I even made a post there.. :palm:
-branadic-
Hello all,
interesting discussion here. I have rough looked from the start to the end.
Q:
Is there somewhere a simplified scheme with a description of the of the individual sections and the timings - would be very helpfully to understand what's going on.
May be I've missed it?
Guido
Hello! Apologies for not being very active here, somehow I find myself more active on Discord and just got around to reading some of the threads here and randomly found a mention ;DA pity the hacker "NNNI" is not discussing his design here (even he mentions the eevblog directly and indirectly there), perhaps the experts here could help him with the noise and none-linearity of his multislope design..
In my ADC I use the LV4053 with 5 V supply and a measured on resistance of some 20 Ohm. With 10 K resistors (and 10 V at the input) the INL contribution is quite significant already. So even the TMUX1134 may want a little more than 10 K - maybe 20 K as a resonable lower limit. Besides the R_on a higher supply voltage also help in reducing the voltage dependence.
The 50 K resistors already allow quite low a noise and noise wise there is little need to go much lower with a 10 V or similar input range.