DIY high resolution multi-slope converter

[Kleinstein]

I tried a small variation of the ADC: the current from the 4053 switches to ground (when the "signals" are turned off) is not send directly to ground, but to an OP buffer. This is the optional OP IC1 in the plan, that replaces C6 and R47.
The idea behind this is to have a rather similar path for the current: either to the integrator or to the buffer. The supplies of the 2 OPs are closely coupled, so that the extra OP is expected to reduce supply ripple and ground currents. This extra buffer corresponds U808 in the ADC of the Keithley 2002.

For testing the difference of 2 run-up versions is recorded, while the voltage is slowly changing.
The 2 run-up version here are 3 phase with 1000 ns respectively 666 ns fixed phase. Total run-up period is 8.5 µs.
This is with the 2nd board and 10 kOhms at the integrator - so more like the test version to make the errors more visible (the 50 K version shows less difference).
Ideally one would have a flat curve or as the next approximation a slight slope. Deviations from a straight line represent different INL errors for the 2 modes of operation.

The green curve is before the change, with a direct ground connection. The blue curve is with the extra buffer.
The blue curve has slightly lower noise because this is the average over 50 conversions as opposed to 20 conversions.
There is a slight change in slope and some zig-zag part from -2500 mV to 1800 mV. So some visible errors at the +-1 V points that would be used to measure 1:10 gain steps.
The extra buffer seems to help with the overall slope (change in overall gain), but not much with the INL.
So far the extra buffer is not worth the effort.

[Crossphased]

Hope this topic isnt dead,
I find it incredibly interesting and I'm definitely going to build one!

Is it possible to switch to a more compact microcontroller? Kleinstein I think I read a comment by you that code coupled with this microcontroller provides the correct timing. I'm wondering if a smaller, faster micro would be acceptable as well?

Also, I took a look at the great board that Rerouter put together. I opened it in Kicad, but Rerouter must have a newer development version of Kicad, the board wouldnt open for me. After going through the text of the .kicad_pcb file, and removing code specific to the newer version of Kicad, I was able to modify to a file that can be opened with the current stable release of Kicad. See attached file if you're having trouble opening Rerouters Github version. Change the .txt extension to .kicad_pcb to open.
Cheers

[Rerouter]

smaller micros are possible, but to use his original code it should be the same series, pretty sure the chip has a QFN option, I was using a dev version from memory as at the time clearance around curves was a little broken,

[Kleinstein]

The Mega48 µC is also available in a SMD version (QFN or similar) - for me this was too tiny to solder by hand. There is no real need for a faster µC. I would even consider reducing the clock speed to some 8-12 MHz to reduce the power consumption. My current board is intentionally not very small to have some room for bodges. Some of the room was needed, e.g for the modified buffer.
DIP parts with socket also allow changing chips (e.g. 74HC4053 or LV4053 or max4053) and if needed to change a chip if leakage is excessive.

With a much different µC one would need to rewrite the code. Some of the code is relatively tricky ASM code to ensure a defined run time, even with doing UART write from the buffer in the "background". Things could become rather tricky if the µC uses some kind of cache or similar, as this makes the run-time less predictable.

My current code uses about half the flash of the mega48, and includes some debugging test code. For a final DMM I am not so sure the fash is sufficient, so it may need the 8 kB version if more functions are integrated.

I have done some slow progress on an analog input board for DMM functions. Basically still the same idea as described earlier in the thread. Integration of 4 Wire ohms and current measurement caused some minor changes.
 
The other open point is the output / digital side. This currently is still a Turbo pascal program for a PC. I also have a crude limited version in C for another AVR µC. However here the AVR is a little on the small side using double numbers makes the code grow quite fast. One may have to go for some ARM based solution here (e.g. Blue pill or maybe a Raspberry).

[prasimix]

Hm, such great ADC + DMM functionality would be a neat new module for EEZ BB3 

[Rerouter]

Glad to see you join the party Prasimix, This was actually the ADC front end I was hoping to adapt into a module for the BB3 after refining it for 100x100mm, I think my kicad files actually still have your pcb template laid out to the right of the page.

[prasimix]

Wow, that's sounds great. I believe we have enough room to put everything in place on one or even two levels if needed: e.g. ADC + MCU + Power on base PCB and DMM stuff as piggyback.

[Rerouter]

Re Kleinsteins latest graph, a while back I spotted that the pattern you where using had certain ambiguous spots and seems to be roughly in the same spot I suspected, Perhaps alter the pattern slightly and see if it moves?

https://www.eevblog.com/forum/projects/multislope-design/msg2608230/#msg2608230

[SilverSolder]

Wow, that's sounds great. I believe we have enough room to put everything in place on one or even two levels if needed: e.g. ADC + MCU + Power on base PCB and DMM stuff as piggyback.

Would this still allow building a stand-alone unit in a minimal enclosure?

[Rerouter]

The blocks are easy to shift around, once implemented for one, it can be shuffled around for another. I've already done it like 40 times for this project 

[prasimix]

Wow, that's sounds great. I believe we have enough room to put everything in place on one or even two levels if needed: e.g. ADC + MCU + Power on base PCB and DMM stuff as piggyback.

Would this still allow building a stand-alone unit in a minimal enclosure?

Yes, why not if we take that requirement into account while designing the PCB.

[Kleinstein]

Wow, that's sounds great. I believe we have enough room to put everything in place on one or even two levels if needed: e.g. ADC + MCU + Power on base PCB and DMM stuff as piggyback.

Would this still allow building a stand-alone unit in a minimal enclosure?

This would still allow a stand alone version with a minimal enclosure. The added part (otherwise provided by the EEZ box) would be the ground referenced part (e.g.  ARM based µC  + LDC module + some PC interface (USB ?)) and a crude power supply to give some 12 V (some 1- 1.5 W) - possibly from an external wall wart.
A point that may prove tricky is that in the EEZ box the boards are vertically mounted - not sure how happy the LM399 is with this.

From what I have found the space in the EEZ box es about 75 mm x 180 mm (maybe 200 mm). At least with my current density this would need 2 stacked boards. Likely split like:
A) ADC + reference(LM399) + ohms current source + some reference level generation
B) input protection, switching, main amplifier, current shunts and current switching.
Especially the relays (currently 5 x)  may take up some space.
For the DC/DC converter and voltage regulation it is not sure which board would have space.

My current plan is to include some kind of internal calibration of the gain and shunt steps to get a artifact calibration like the 3458. For a DIY project it can be handy not to need many calibration points. This kind of needs  current ranges down to µA  and 1:10 steps. So there is no easy simplification with fewer shunts or only small current sources for Ohms. If at all one could simplify at the low current / high ohms (e.g. > 10 M) end. Also limiting the current to some 1-2 A can allow for more compact relays.

[Kleinstein]

Re Kleinsteins latest graph, a while back I spotted that the pattern you where using had certain ambiguous spots and seems to be roughly in the same spot I suspected, Perhaps alter the pattern slightly and see if it moves?

https://www.eevblog.com/forum/projects/multislope-design/msg2608230/#msg2608230

There are a few more tricky values, e.g. at some -350 mV where the modulation is like +-+-+- or to a smaller extend at other special patterns. The points move with a modified run-up. Quite a few of the graphs / linearity tests are with the difference between different feedback (run-up) versions. This is currently the most sensitive way I have to detect small deviation from ideal behavior.

[prasimix]

Thanks Kleinstein for valuable input. The EEZ DIB module PCB dimensions are as in the picture below (height 95 mm x width 90-185 mm, source files are here). We also have enough room to stack two PCBs (distance between modules is 35 mm).



The module may or may not be ground referenced. A small isolated DC-DC converter like Traco could be used (e.g. like in case of MIO168 module).

Hm, if LM399 don't like vertical mounting that could be a show stopper. Perhaps something else could be used (not in that class but still worth the trouble)?

[Kleinstein]

The LM399 shows a slight change in voltage when tilted, but if this is constant it would not really matter. It is most likely OK. The main effect would be a slightly different thermal environment for the reference.  The LM399 with long leads is relatively high - so this may need to go to the inside with space left out in the other board. With the populated side to the inside one would just need to avoid a high part in this area - just no relay of large cap there.

One would likely need some insulation and maybe a shield to neighboring modules so some of the 35 mm spacing is lost there. So it would likely be something like 20 mm board spacing with the large parts on the inside.

The DCDC converter on the bus board would probably not be good enough. They usually have too much common mode ripple signal to be really useful for a good DMM. At least the ones I know are made for small size and not low coupling capacitance.  For the DCDC converter it would help to know the real power need (likely < 1 W, but could be more (e.g. 1.5 W) with a high ohms source current).
So far I plan with some +-20-22 V and some 7 V (to get 5 V from an LDO) so this would be non standard voltages anyway.

[prasimix]

Judging by the look of similar modules for VXI / PXI chassis, I think shielding will be mandatory for the whole module or at least for the sensitive sections.

Regarding DC-DC isolation, what's about SN6505B push-pull converter in combination with ultra-low noise LDOs? That should provides 2-3 W.

[Kleinstein]

I think shielding and extra isolation would be needed, as the circuit ground / shield could be at a relatively high voltage (e.g. 200 V, maybe 500 V) relative to the rest of the circuit. At least for the 1st version I would limit the maximum voltage, so that more normal relays can be used and less need for cut-outs or extra spacing.

The SN6505 looks good, though I would prefer the lower frequency A version. My current DIY DC/DC runs even slower (AFAIR 25 kHz and long BBM time) as it uses a relatively large core (some 30 mm OD  ring core) to get more distance for low coupling. I don't think it takes special low noise LDO's - normal ones should be OK. It would be more about the higher frequency ripple. If at all it would be the +5 V for the 4053 switches at the ADC that is a little critical. This may be derived from the main reference (like in the 34401) if really needed - it may be a good idea if the 5 V regulator is not directly at the ADC.

[cape zoloh]

Kleinstein,

Thank you for this thread, it is pure gold.
I've gone through roughly half of the thread now, and your posts are invaluable. Your tone is always positive and very informative. Thank you for sharing. Do you still put time into this?

[Kleinstein]

I am currently working on the input part to make it a full DMM (DC only). For the actual ADC part I have currently no need for changes: The INL part is still not as good as I ideally hoped for, but kind of good enough. The DMM input part would make INL testing simpler - so for the time being I consider the ADC good enough. The noise is already very good and I now know the NOMCA resistors are a large part of it, so it could get even better. The INL could always be better, but it's starts to get tricky with testing for the 50 K version - the last tests with larger errors were with lower resistors (20 K and 10 K) to make the errors more visible and thus simplify testing.

The last change in the HW (using a ground buffer - already planed on the PCB and finally tested) looks small, but it makes the difference between needing the reference closely linked to the ADC and the option to have an external reference.  There is an effect on the INL too - though not large. This supports that part of the INL has to do with the layout / ground routing.  A lower noise reference may be needed for more stringent INL tests.

Another point was looking at the option to change to an STM32 µC  (e.g. STM32F334 or STM32L151) - wanted to start with these µC anyway. It looks like the event system can do essentially all the time critical things in hardware. So there would be no more need for ASM code and C code could work. By itself the other µC with a 12 bit ADC would not improve the resolution or noise - it may make things slightly faster, but not much. It can however allow a different run-up version, that may have better INL  So I am not sure if I do the next ADC PCB version for an AVR or STM32.  I have a slight problem with the communication from the GND based part towards the AVR, as the AVR is not checking the input side very often.

Anyway the front end would probably be first, but should work with both µCs.

[openloop]

Kleinstein,

The noise is already very good and I now know the NOMCA resistors are a large part of it

What's wrong with those? Not-temperature-related ratio drift?
How did you find out?

K2002 ADC uses that kind array (asymmetrically) in slopes current setting.

[Kleinstein]

I see more than initially expected 1/f noise, even after changing the main relevant OP. So there seems to be an additional source of 1/f noise.  The noise also went down with different resistors:  with NOMCA (50K) the noise level is at some 850 nV, with 20 K PTF56 (2x10K in series) the noise goes down to 500 nV. The change is not only in the white noise part, but also with the 1/f part.

There is also a measurement of the NOMCA resistor noise directly:
https://www.eevblog.com/forum/metrology/statistical-arrays/msg3137942/#msg3137942
The noise measured there is about the order of magnitude I see as extra 1/f noise.
So my current favorites are DNFA resistors as there is no 50 K version of LT5400.

The K2002 DMM is relatively noisy (some 2000 nV for 1 PLC AFAIR, but conflicting reports). Excess noise from the resistors could be part of the problem, but there seem to be other points (the front end may contribute a factor of 2) that also add to the noise. The resistors are likely not the main point. The resistors look similar to NOMCA, but they may be different internally.

[openloop]

Kleinstein,
Thanks!

In regards to your INL testing:

How do you measure it?
I'm asking because when messing with my guinea pig K2001, I found that it is very important to keep ADC busy.
Namely, interspersing payload with acal readings of various voltages keeps components warm and their thermal mass (inertia?) reduces influence of the value measured on the result.

[Kleinstein]

For the INL testing I have 3 different tests:
1) the classical turn over test with a few voltages (1.5 to 9.3 V in steps of some 0.7 V). Switching the polarity is manually, but the program runs through. The results are averaged over some 5 repeats.
2) A simple addition of 2 voltages test, with the sum at some 9.3 V or -9.3 V. Here again switching at one end is manually the other end is with the DG408 mux at the ADC board.
3) compare 2 ADC variants with different run-up versions (e.g. different delays, FB frequency). So one reading version A, one reading version B and than back to A. The difference between the 2 versions captures those INL errors that are different for the 2 versions. So not a full test, but on the upside very sensitive to also small  errors down to the 0.01 ppm range and relatively fast and automatic (let the program run for some 2-5 hours to get a whole lot of data, e.g. covering some +10 to -8 V with maybe 5000 points after averaging to some 50 to 100 PLC.

The first 2 tests include the reference noise and are thus more noisy. The difference test uses an external test voltage, but the difference is over a short time and the filtering of the ADC reference helps here quite a bit. So reference noise does not enter very much. The first 2 tests get the long range (e.g. U² and U³ contributions), while the 3rd test gets the shorter range more wiggly part with more local effects. The more short range effects are expected to be effected by a different run-up. The slow changing part may not change with a different run-up.

[branadic]

With respect to the noise measurements by Castorp you could test Susumu (NI -60dB) RM3216I-503 / RM3225I-503 / RM6432I-503 (4x 50k resistor) to see, if you are limited by the noise of NOMCA (NI -40dB) resistors.

-branadic-

[Kleinstein]

The Susumu resistor arrays with 50 K and 3 or 4 resistors  seem to be not so easy to get - I don't see them in Stock or even listed at Mouser or Digi-key.

The DFNA arrays are in stock at mouser. They are not as low noise, but still supposed to be some 10 dB  (7 dB compared to 2 resistors in series) better than NOMCA. As last resort it could be 4 x 10 K in series, which also has a chance to improve on the relative TC and self heating.

The relevant frequency for me is at some 17 or 25 Hz. So there may be a little excess noise visible, maybe comparable with the normal Johnson noise.  The excess noise would also cause some fluctuations in the overall gain, effectively adding noise to the reference.  This is not much and the NOMCA resistors should still be better than the LM399 ref, though likely more noisy than a LTZ1000 ref.

Another series available is the PRA100 series: not as cheap (some 10 EUR), but still OK.

So maybe a should get some for testing (e.g. dead bug style on the existing PCB)  before designing the next ADC PCB. The 50 K resistors may behave slightly different from 10 K. Also the noise specs (if there at all) could depend on the value or may reflect the limits of the test system. Measuring below -40 dB noise index is tricky.
I am quite sure that quite some of the noise is due to the resistor excess noise - so the tests are more about finding / confirm a better solution.