DIY high resolution multi-slope converter

[Kleinstein]

I have not measured the TC of the ADC gain for the new ADC. For the 2 AVR based version the gain changes by something like 0.3 to 1 ppm/K, depending on the resistors used and temperature range.
I would consider the warm up after turn on to be some 1-3 K. The circuit is relatively low power (some 1.3 W - most in the half with the ADC) and relatively open, so not very much temperature rise. The matching of the ORN resistors is typical quite good and the other resistor is only used for some 5%. The very first part of the turn on is missing - it just took some time to set up the data recording. So it is 0.6 ppm from 1 min to final, which is still surprisingly good.

With long time stable I mean more than the time between ACAL , maybe more than weeks or so.

To really get 8 digit stability and 7 digit accuracy it needs a relatively stable temperature that is the same with other high end meters too.
The 0.5 to 1 ppm/ K range is what I get from the resistors and for me this is good enough - espeically with still only a LM399 ref.

Some keithley meters spend actually quite some of the time in a kind of ACAL to measure the ADC gain as part of the AZ cycle. The Keithley 19x supposedly do that for every cylce. They may do some averaging over mutiple cycles to reduce noise. I tried this cycle too with the AVR based version and for poor quality resistors at the ADC (e.g. thick film, or low grade thin film) it is really worth it, as the gain changes not only from temperature but also with some random component from resistor excess noise.  AFAIR even with the cheap resistors the gain TC was low (in the < 2 ppm/K range), but there were still variations in the gain, more than expected from the TC.  If really needed, spending half the time in ACAL is a real option. However it may not be a good idea to directly interleave it with the AZ cycle like with the old Keithley meters. At least in the AVR version there was some delayed effect, that could than lead to an INL error.

[Kleinstein]

I got a first higher resolution test for the difference of 2 variations of the run-up.  So the same, slowly changing voltage (capacitor charge and discharge) is measured with 2 different versions of the run-up.  Ideally the 2 versions would get the same result, but the details can vary, e.g. due to errors from DA in the integration capacitor and also coupling effects at the clock. One can see the curve (deviations from a stright line) as indication for the more wiggly parts to the INL.  INL from the amplifier, ADC input buffer and thermal effects (e.g. in the resistors) are not included. The main effects included are DA, integrator input settling and unwanted electrical coupling / supply variations.

Compared to a classic INL measurement this test is easy (not much extra instruments needed) and relatively fast (some 3 h for the curve), but still quite sensitive (low noise).

The curve is still not perfect, but allready quite good and better than in the AVR based version. The improvment is not from the different µC, but more with a better layout / better decoupling. Using a slower modulation may also be part of it: so decoupling gets less important but DA gets more important.
The points are the average over 192 conversions or 2x20 ms each.

[MiDi]

Put together the major issues with PCB of Rerouter, see the github issue.

[Kleinstein]

I had a quite look at the plan from Rerouter / Midi:

There is no problem to use 4.7 K resistors where 5 K is in the schematics.
The capacitors C28 and C26 should be OK with only 47 nF and likely even 10 nF, which are better available.

The capacitor C31 is quite large, a smaller value, more like 1 nF or maybe even 1 pF may be more suitable as the settling of the butter could be faster, though the difference would be hard to see, but it could be the last missing fraction of a ppm.

When using an OPA145 for U11 the resistor R10 should be smaller, more like 2.2 to 3.3 K. This resistor set the compensation / settling speed of the intgrator. The 6.8 K values is about right it U11 us as fast as U2 (e.g. OPA141 or OPA1641 for U11).

The capacitor C37 is more like optional and not sure if it helps or is more like a problem. I don't have it populated.

The capacitor C15 is quite small at 22 pF. I have 47 pf (AVR version) resp. 39 pF (ARM version) to give a slightly lower BW and betterst stability for the NE5534. I am nor sure this makes a big difference.

For the µC  the mega88 would be OK too (may need to change the include in the ASM file, but that should be about it).

The part around Q5 and Q6 is optional. I had this for tests and it does improve the settling of the integrator seen on the scope (e.g. at LSP6): the settling is no longer depending on the input level. However the overall effect on the INL is no measurable. I now also understand why:
The slow op in the integrator (U11) makes fixed steps following reference switching. For each step it needs a fxied pulse area at the input. The loading of U2 changes the shape of the pulse for the integrator input, but it hardly changes the area. The relavant part for the linearity is the area only and not much the shape of the pulse.  The change in settling with loading of U2 was one of the candidate mechanism for INL, but it looks like it is not a significant one.

[MiDi]

Remarks/suggestions for Rerouters version rev 2 from 22 Mar 2020:
Enable (2) DG408 U7: should have e.g. 1k resistor to 5V for protection Edit: or a diode from 5V to 15V as suggested by Kleinstein
Mark components/areas as optional (e.g. U1 GND buffer, U202 DAC heater, U20 slope switch, C37, Q2 [add JP], U10, R84 JP) -> see former post from Kleinstein
RN201/2/3: footprint hard to solder by hand (0.65mm) -> option for e.g. ORN (1.27mm)
Differential frontend (LTC2057 & OP07) needs some investigation, it happily oscillated (removed it for now)
Ref+/- buffer needs some investigation, measured high ripple on output of OP07 U8/9

Ideas/questions:
C13 4.7µF foil @ LM399 that large useful? (I must admint, that I do not fully understand why it is put there and how it will effect Ref+ and Ref- output)
U8/9 OP07 Ref-Buf dissipation/temperature: bipolar supplies needed? Could have single supply to GND (via separate trace) to cut disssipation in half
ATMEGA as SMD: cheaper & takes less space
(Alternative) SMD footprint(s) for X1 oscillator (TBD if SMD osc has influence on circuit - Kleinstein had bad experience, mechanism not clear [at least to me])
Remove unused/not (yet) supported parts in FW (same as in "Mark components/areas as optional") -> see former post from Kleinstein
RN202/3 integrator input resistor networks: support for one resistor network without bodges (e.g. 1x (M)ORN 4x50k)
Current version needs quite high AC input voltage due to quite high ripple on input caps, removing AC input capability and leave that to the PSU could be an option (lower EMI?)

[Kleinstein]

U9 does not need the -15 V. It can rund from GND and +15 V. No problem there.
U8 needs to operate around 0 V. So in therory it could run from +5 V and some -15 V or whatever is there.

If power / heat is an issue, there is the option to use the more modern OPA202 instead of old classic op07. It has slightly lower noise and lower supply current. If power is an issue there are a few other OPs that could be lower power or use a lower supply.

Normally there should not be ripply on the supply. I have run my board from a 2x18 V transformer with extra series resistors. A 2x15 V transformer should be about right. The Fitler caps may need to get a bit larger though.

C13 is there to filter the reference noise. The size depends on the needs. For just simple tests 470 nF or 1 µF would be good enough. The ciruit work also without the cap, just slightly higher noise. The higher value is mainly to help with the measurements for the linearity. There are 2 main frequency band to fitler out : one is at some 10-100 kHz from the modulation. This easy and would only need a few nF. The second band of interest is at around 25 Hz and maybe extending down to some 10 Hz (for the slower AZ loop with 4 readings). This helps as the normal AZ mode cares about the reference low frequency noise only half the time and thus also reacts to reference noise from the 25 Hz band. This is not really much, but still relatively easy to filter out.  Some 4.7 K and 1 µF with the addiotional gain of nearly 3 gives an cross over frequency of some 10 Hz. With 4.7 µF the cross over is at some 2 Hz and thus already quite some attenuation for the 25 Hz noise part.  It helps mainly with the difference test as this is not sensitive to even lower frequency noise. So the reduction at 25 Hz makes a big difference. For the more normal measurements it can not really replace a lower noise reference. 

I don't think protection is needed for the enable input, but it would not hurt either. The point would be more care with power sequencing or preventing the 5 V to be much higher than the +15 V with a diode.

A SMD oscialltor is definitely possible. However the SMD ones are often 3 - 3.6 V only. Very few run from 5 V. The LV4053 switch is not really happy with a 3.3 V logic signal, though the µC may run with this. In the ARM version I have an addition buffer for the clock signal to reduce the chance to effect the clock from this side and it seems to work well. So a SMD 3 V oscillator and AHCT14 or similar gate as level shifter may be an option and even lower power than the old large oscillator.

The Q2 and Q8 part at the Ne5534 is a bit odd. I had not so great experience with transistors as diode and for the ARM version use 3 diodes that work quite well. The BAS21 seems to be a good compromise between leakage and recovery time for the 1 critical diode. The other 2 can be simple fast ones (e.g. 1N4148 / BAV99). With just 3x 1N4148 the weak point is dirft of the gain (likely temperature dependent leakage). With a transisistor instead of 1 diode the problem with relatively large drift of the DC level / trimmer position, likely from slow recovery. With a relatively low gain for the final amplifier the drift of the DC level may be still acceptable.

Just a crystal is not working well, as the frequency is effected by the µC operation. Modulation of the frequency was a major reason for INL with my AVR version. So good supply filtering at the oscillator is important.

For normal operation just 1x50 K resistor network is OK the integrator. If one wants very good INL there can be a slight advantage from 2x25 K to reduce the self heating effect (1/2 the temperature rise and a chance to get better TC matching) so that the INL contribution would be expected to be reduced to about 1/3. I expect the INL contribution from the resistor array to be in the 0.1 to 0.5 ppm range, depending on the luck with the relative TC.

With the ARM based board I have an input stage relatively similar to the LTC2057 and OP07 part. I also tested this on the bread board - though I don't recall the exact parts (likely MCP6V51 and OP07).  It worked OK, though it needed some tweaks for the case with gain. The OP07 part may need a little more slow down. The filtering caps were a bit tricky. On the BB I had the capacitor equivalent to C21 towads the OP07 output instead of GNDS.  It is not directly related to the ADC, but would give a +-20 V input range with the same noise level and less need for reference filtering.

[MiDi]

FW is now changed as suggested by Kleinstein and works (see attachments).
Difference is very small and could even come from closed alu case now (was formerly open).
Currently a beefy linear bench PSU is used, could have some influence.
Next thing is to swap DG408 against new Vishay batch and test ADI/Maxim version (Reneseas could be cheaper option, but n/a at the moment) -> Options now added to mouser BOM (link see earlier post).

Edit:

FW diff to Kleinstein July 28, 2021

Code: [Select]

    Changed mux7 from Nr. 5 (S6 buffered 7V) to Nr. 6 (S7 unbuffered 7V) - there is no buffered 7V awailable
    Refined comments on mux0/1/Temp

--------------------------- Multislope ADC/main.asm ---------------------------
index 5df8705..f61ee93 100644
@@ -91,10 +91,10 @@
 #define portMUX portc            ; MUX port   , rest is input, e.g. ADC inputs
 
 ; mux setting, including fixed part (currently 0)
-#define mux0  8*7               ; Mux channel for 0 V = Nr. 7
-#define mux7  8*5               ; mux channel for 7 V ref = Nr. 5 = buffered 7 V
-#define mux1  8*2               ; mux channel 2 
-#define muxTemp  8*4            ; mux channel for diode (Temp) = Nr. 4
+#define mux0  8*7               ; Mux channel for 0 V = Nr. 7 (S8 = GNDS)
+#define mux7  8*6               ; Mux channel for 7 V ref = Nr. 6 (S7 = unbuffered 7V)
+#define mux1  8*2               ; Mux channel for Input3 = Nr. 2 (S3 = J2 Pin 3)
+#define muxTemp  8*4            ; Mux channel for diode = Nr. 4 (S5 = Temp)
 
 
 .equ  ADcontr  = (1 << aden) +  (1<< ADSC) + (1<<ADIF) + 6     ; ADC enable + start  + Flag (to clear) + clock / 64 (6 -> 125 kHz bei 8 MHz)
 
 
 
     Use external Ref for ATMEGA ADC

--------------------------- Multislope ADC/main.asm ---------------------------
index f61ee93..9e33073 100644
@@ -101,7 +101,7 @@
                                            ; include Interrupt flag to clear flag on start
 .equ  ADcontrStop  =  7        ; Disable ADC, set ADC divider to different values
 
-.equ  ADMUXval = 1 + 64      ;ADC channel (1) + Ref. (64=VCC , 192 = internal , 0 = external)
+.equ  ADMUXval = 1 + 0         ; ADC channel (1) + Ref. (64=VCC , 192 = internal , 0 = external)


    Swap ADC0 and ADC1 (change in rev of Kleinstein)

--------------------------- Multislope ADC/main.asm ---------------------------
index 9e33073..3c51ea1 100644
@@ -96,13 +96,15 @@
 #define mux1  8*2               ; Mux channel for Input3 = Nr. 2 (S3 = J2 Pin 3)
 #define muxTemp  8*4            ; Mux channel for diode = Nr. 4 (S5 = Temp)
 
+; ATMEGA ADC setting ADMUX – ADC Multiplexer Selection Register
+#define REFS 0                  ; Reference Selection Bits (0 = external, 64=VCC , 192 = internal)
+#define ADMUXICh 0 + REFS       ; ATMEGA ADC input channel for integrator charge level - output of U13B (ADC0 = 0 ... ADC7 = 7)
+#define ADMUXSlp 1 + REFS       ; ATMEGA ADC input channel for slope output level - output of U13A (ADC0 = 0 ... ADC7 = 7)
 
 .equ  ADcontr  = (1 << aden) +  (1<< ADSC) + (1<<ADIF) + 6     ; ADC enable + start  + Flag (to clear) + clock / 64 (6 -> 125 kHz bei 8 MHz)
                                            ; include Interrupt flag to clear flag on start
 .equ  ADcontrStop  =  7        ; Disable ADC, set ADC divider to different values
 
-.equ  ADMUXval = 1 + 0         ; ADC channel (1) + Ref. (64=VCC , 192 = internal , 0 = external)
-
                           
 
 start:
@@ -120,7 +122,7 @@ start:
  ; ADC initializing
  ldi temp, ADcontr     ; ADC config mit start
  sts ADCSRA,temp
- ldi temp,  ADMUXval         ; ADC channal + speed +  Ref. . for AVCC ref. (no link needed)
+ ldi temp,  ADMUXICh         ; ADC channal + speed +  Ref. . for AVCC ref. (no link needed)
  sts ADMUX,temp
 
  ldi temp, 1+2         ; Disable digital input for ADC inputs  0 and 1
@@ -955,7 +957,7 @@ mslope2:                  ; call point for just data collection of rundown
  st x+,coutBL
 
  rcall readAD_wait     ; ADC right after rundown;
- ldi temp, ADMUXval -1 ; MUX to auxiliary (for next conversion)
+ ldi temp, ADMUXSlp    ; MUX to auxiliary (for next conversion)
  sts ADMUX,temp
 
     lds temp,par_syncdel  ; extra delay to check delayed effect  (some gets hidden by wait for ADC)
@@ -963,7 +965,7 @@ mslope2:                  ; call point for just data collection of rundown
 
 
  rcall fullADC         ; 2nd reading for simpler data format , make drift visible (e.g. DA)
- ldi temp, ADMUXval    ; MUX to res charge
+ ldi temp, ADMUXICh    ; MUX to res charge
  sts ADMUX,temp
 




    Local uncommitted changes, not checked in to index

--------------------------- Multislope ADC/main.asm ---------------------------
index 3c51ea1..34272bc 100644
@@ -54,7 +54,7 @@
 #define  par_syncdel   0x105    ; delay in ADC sync (for testing)
 #define  par_runup_ver 0x106    ; runup version
 
-#define F_CPU 12000000
+#define F_CPU 16000000          ; Clock frequency of µC - change accordingly
 #define BAUD         9600       ; should be more than about 8000 Baud to transmit data during 20 ms conversion
 #define UBRR_BAUD   ((F_CPU/(16*BAUD))-1)

[Kleinstein]

I don't think the DG408 makes a big difference. The point is more with the supply, maybe EMI. One could also try to slow down the NE5534 a little with a larger capacitor.

 The 2 reading cycle may also show less noise, as reading the 7 V ref. can effect the reference a little. So this may add a little more noise. With stable resistors there is usually no real need to also read the reference in every cycle.

It is normal to see more noise with the reference reading, as the reference used for the ADC is filtered quite a bit and the one used to measure has only minimal filtering.

An interesting point could be using the 3 conversion cycle and use the temperature sensor as input. If one than warms up the circuit and lets it cool down, one can see how stable the ADC gain is.

Edit:
Looking at the raw data, there is still quite some change in the residual charge readings that are done direct after another ( end of one conversion and start of the next conversion). I have much lower noise (e.g. +-1 LSB) there. So this points to something like the slope amplifier with noise, too much BW, or maybe the signal not yet settled when the ADC reads it. The clock for the µC internal ADC is also alread boarderline high (250 kHz) with the 16 MHz clock, though I also have a 16 MHz clock on one of my baords.

[MiDi]

Attached 1/2/4/8 PLC, different runup modes and µC ADC slow down by 2, raw data in zip.

Diff µC ADC slow down by 2

Code: [Select]

    Slow down ATMEGA ADC conversion by 2

--------------------------- Multislope ADC/main.asm ---------------------------
index 3c51ea1..4ca82e4 100644
@@ -101,7 +101,7 @@
 #define ADMUXICh 0 + REFS       ; ATMEGA ADC input channel for integrator charge level - output of U13B (ADC0 = 0 ... ADC7 = 7)
 #define ADMUXSlp 1 + REFS       ; ATMEGA ADC input channel for slope output level - output of U13A (ADC0 = 0 ... ADC7 = 7)
 
-.equ  ADcontr  = (1 << aden) +  (1<< ADSC) + (1<<ADIF) + 6     ; ADC enable + start  + Flag (to clear) + clock / 64 (6 -> 125 kHz bei 8 MHz)
+.equ  ADcontr  = (1 << ADEN) +  (1<< ADSC) + (1<<ADIF) + 7     ; ADC enable + start  + Flag (to clear) + ADC Prescaler clock (6 = /64 -> 125 kHz bei 8 MHz, 7 = /128)
                                            ; include Interrupt flag to clear flag on start
 .equ  ADcontrStop  =  7        ; Disable ADC, set ADC divider to different values

[Kleinstein]

The noise goes down quite a bit with the longer conversions. So there is not much 1/f noise. Still the noise is not going down all the way like 1/ NPLC, so the residual charge noise is not the only source of noise.

The noise with the runup version "W" (= half the modulation frequency) is lower noise. Case "P" ( doubled frequency) is higher noise. This points to some noise from jitter. I also see this trend.
The version "W" also has a bit different reference reading (not much, but still visible) - this could be due to the resistor ratio after the opa145 in the integrator that slows it down a little too much. So the relative short pulses may behave different.

The offset with a short going down with more PLC is also what I see, though a little higher here. I am not so sure where this comes from. In the 3 reading cycle part of it can come from a delayed effect. The ADC has some kind of memory for the least reading and a little from the last conversion spills over to the next. This could be DA (though the effect is quite large for this) and thermal effects. I still don't fully understand that part.

I have not looked much at the ADC gain ( reading the own ref.) at different PLC settings. It is still a bit surprosing to see so much change. part of the effect could be memory effect.

[Kleinstein]

I did a more basic INL test. The idea is to check if the sum of 2 voltages actually reads as the sum. As an example have a 4 and a 5 V source in series and check if 4 + 5 is really 9. In my case the sum is fixed to some 9.4 V and a few different points in between are used.

For the connections this uses the 2 inputs from the DVM board (switching in software) and 1 external mechanical switch. The 2 ref voltages are generated from a single reference source with a divider - same as used with the AVR based board before. In addition to the 3 readings there is 1 more 0 reading.  This way each DVM input and each setting of the switch is used twice and offset errors for the inputs or at the switch should cancel out. With everything stable this test is relatively easy. However there is the complication that the LM399 references used at the DVM and for the external reference circuit are not that stable, but shows popcorn noise. So there can be jumps of some 0.5 ppm at either side. A know the external ref. is a bit noisy.
Trying to see an error in the 0.1 to 1 ppm range such a jump can cause a significant error. The idea is to get cycles of the 4 measurements with stable reference.
With a more manual process (switch and selecting data) brute force averaging is not so easy, but would be a theoretical option with a little more automation.

Attached it the result and a curve showing some raw reading. To get the data all one one screen the data are reduced to a little more than the last 2 digits (the digits further up do sum up correctly). So one can do the math with only looking on the end (100 nV resolution, 20 µV wrap around). The right scale / green symbols give the coarse voltage to see which step.

The known mechanism to cause such an error (voltage contribution proportional to U³) is the self heating of the resistor network from the input current. For comparison I did a short test for the TC of the ADC gain:  heat up the board to some 40 C and than on cool down record the board temperature and ADC gain (read the own ref.). The resulting TC is surprisingly low : ~ 0.4 ppm drop in the gain for some 4 K of temperature drop. I think I got lucky with the resistor this time (the AVR version was more like 0.5 ppm/K). This is still the combination of the 2 resistor networks, so no direct comparison to the nonlinear effect. Testing the networks separately was a bit tricky: the 50 K network showed the same positive sign fitting the sign of the nonlinear effect (more gain with a higher voltage). The 10 K network for the reference did react on temperature gradients too and could show positive and negative effects. There is also some mechanical effect on the resistors. Bending the board can change the ADC gain. So the rel. TC of the 50 K network may be a little larger than the total 0.1 ppm/K gain TC.

First quick turn over tests showed pretty low errors - may have to test a little more patient.
However the results so far not really sum up to the comparision of the 10 V range (more normal 0 and signal AZ mode) and the 20 V range (differential U/2 and -U/2 signal to the ADC). This comparison does show an higher error. So there still seems to be some additional error I don't understand so far.

[MiDi]

Changed slope amp C15 from 22pF to 44pF - no difference in noise with short
Operation from battery - no difference in noise with short

[MiDi]

Seems I found magic denoise button 
Noise now down to 100 / 110nVacrms (short / Ref @1PLC & 5min) and values now very close to where they should be:






Magic parameter in Pascal program:

Code: [Select]

xd = 1000*3;                 // extra  delay 3x xdel in ASM code
Went a bit crazy with 1000*3, formerly it was set to 0*3 (Kleinstein seems to use 12*3).

[Kleinstein]

In most of the later data files the raw ADC reading look good, so little residual noise for the 2 consecutive readings (e.g. columns 10 and 17) of the µC internal ADC. The version with the slower ADC clock still seems to have some problem (more noise and the last column is allways 0). So one can probably go back to the faster ADC clock.

The comparison of the noise for the different modulation speeds show quite some difference: for the cases P,Q and W ( double, normal and half the speed) I get noise of 2.9 µV , 2 µV and 1.4 µV for the 3 cases.  So there is quite some noise related to the switching / jitter.

One could try to slow down the modulation, e.g. about to make the slow case W mode like the more normal case, by increasing the xdelay constant in the ASM program (e.g. from 12 to something like 40). The slight higher clock (16 vs 12 MHz) makes it start a bit faster anyway. The integration cap is still large enough for this.
The other point would be trying to find the actual jitter source. The main candidates are the oscillator, the HC74 and the LV4053. This could be the chip itself, or there supply / decoupling. For finding the weak point in the HW side the faster modulation would be an advantage. Normally the HC74 and LV4073 should not be so bad, unless there supply is unstable.  Trouble with the clock decoupling would likely be also visible in the INL test via the difference test (B).

A very short xdelay (in the ASM program) could explain a little, though I still think there is more jitter than it needs to. A values of 1000 is likely way too high and may drive part in saturation. The upper limit is likely at around 63, as there may be some 4xdelay that has to fit in 1 byte. The numbers in the ASM and Pascal program also have to match !

A noise of only 100 nV would be too good to by true. The Johnson noise of the resistors should contribute about 300 nV. The best noise I got with the AVR version was with slow modultion, at some 420 nV. With faster modulation the noise is more like 500 nV. With the ARM version and an slightly slower modulation I get down to 360 nV, which I would consider well good enough and better than hoped for.

edit:
I lookes at the raw data: there is still some scattering in the raw resuslt, just the math for the 7 V ref reading is way of an this than divides down the result so much. WIth the slower ADC clock the reading also show more scatter. The values for the K1 and K2 factor should normally be relatively stable. So no real change needed unless some HW change or very different temperature. If K2 changes with the setting of the trimmer ( no need to be strictly in the center of the ADC range, just avoid hitting the bonds) this would indicate going to high in the residual votlage. I don't exactly know how the 2 transistors behave.

2nd edit:
If the ASM code still has xdelay=12 and the pascal code had 0, than the scaling was wrong (and massive INL/DNL errors) before too. So the actual noise may already be better by about a factor of 2.  So the appearent 1.4 µV noise would be more like 700 nV noise for the slow mode. Still not very good but already useful. One can get a quick check of the linearity by watching a capacitor discharge an error in the size of the runup steps is quite obvious.

[MiDi]

You always need to do compromises, so it´s the button to adjust noise vs. inl 

Meanwile the board got different XO (cheap Reichelt) and noise got a lot worse - around x2 (4µVacrms vs. 2µVacrms prior XO).
Seems the XO has quite high influence on noise - @Kleinstein, which one do you use?

The FW always had delay 12, but missed to change it in Pascal program
Did comparison of delay 12 & 0 in program with cheap XO and as proposed the noise with delay 0 is around 2x (4µVacrms vs. 8.1µVacrms) - this applies to the diff to the expected value as well (5.3µV vs. 10.3µV for short).

One thing I want to try is to have more delay after DG408 input mux switching, but have no idea where what to change.

The Q2 and Q8 part at the Ne5534 is a bit odd. I had not so great experience with transistors as diode and for the ARM version use 3 diodes that work quite well. The BAS21 seems to be a good compromise between leakage and recovery time for the 1 critical diode. The other 2 can be simple fast ones (e.g. 1N4148 / BAV99). With just 3x 1N4148 the weak point is dirft of the gain (likely temperature dependent leakage). With a transisistor instead of 1 diode the problem with relatively large drift of the DC level / trimmer position, likely from slow recovery. With a relatively low gain for the final amplifier the drift of the DC level may be still acceptable.

BAS21 diodes are in the pipe (with some other components) to try out.

[Kleinstein]

For the oscillators I have more like cheap parts. The 12 MHz one was an old recycled part from the 1980s  (AFAIR an old Comodore floppy drive). The 16 MHz one has a NKC mark - no idear were I got it, but should be nothing special.
The ARM Version uses a 8 MHz cheap  (some 1.2 EUR) ECS brand SMD crystal oscillator. I think it has 1 ps jitter specs.  It should be a true quartz crystal and not an PLL chip or MEMS chip. The old large can were usually true crstals, but often quite high in power.

Besides jitter the other point with the oscillator can be how easy it can be effected by supply or ouput load. This was a nasty INL part with my AVR version.

AFAIK the 74HC74 would have Jitter in the 2.5 ps range and AC74  would be at around 1ps. The LV4053 may also have some 1-2 ps of jitter, but I am really not sure here. The expected noise from jitter should be about 28 V * sqrt(2*mod frequency) * jitter.  Something like 3 ps total jitter would still be no big problem if the modulation frequency is not very high.

The delay / length of the runup steps have to match between the 2 programs. If not the INL is really bad, like % range, not just a little.
I think I had tested the 16 MHz board with very fast moduation and thus still had the zero there. Sorry for the confusion.
With the wrong setting the comparison between the speeds is also useless, as the factor is different for the speeds.

There is a bit of compromising noise versus  INL / speed, but it is not so simple:

Faster modulation allows a slightly faster rundown and gives less INL from DA, but more DA from switching artifacts and supply coupling. So there is no simple faster is better. Already for the INL there is some optimum value. Chances are this is about in the 25-100 kHz range, depending how good the decoupling on the PCB is. I don't think one would need a higher frequency just for the DA with the good TDK cap. It looks like the DA contribution is below 0.1 ppm even with only 32 kHz modulation.

Slower modulation can give slightly (goes with the square root) lower noise from jitter, but if very slow also needs a larger integration cap and than more noise for the final charge reading. The current 2.2 nF should be OK down to some 15 kHz or so and the residual charge noise would be an issue mainly below some 1-2 ms integration.

Adjusting the delay for the settling would be with the length of the rundown. This is the
#define rundown_wait   6 
part in the ASM code. This is the main part of the time from the start of rundown to start of ADC reading. The code will add a few more µs. The 3 ADC readings come extra to the rundown.

[Henrik_V]

Concerning the jitter of the µC: Awoid or check the internal PLL.... usually a cheapo BangBang .....   have seen nice sawtooths in the f_cpuclock/timer over time ..

[Kleinstein]

The AVR does not have an internal PLL.
The ARM version is not using the PLL. In theory one could use the PLL and higher clock, but it makes things more complicated. The critical ref. signals are synconized externally. This has a small window for the phase where the synchronization does not work ( I had that in my first try and had to remove a inverter to fix) and this is to be avoided. So one would have to somehow measure the phase of the external clock relative to the internal one.
For the AVR at some 10-16 MHz the same signal to the µC and HC74 flipflop is about perfect. For the STM32L051 the same configuration is at the wrong phase, violating the FF setup/hold timing. So one of the clocks needs to be inverted.

The problem is with the modern canned clock oscillators. They look similar, but can be quite different inside:
1) crystal at the right frequency or a simple mutiple and than a simple divider - that is the good way. For the lower frequencies in a small case I would expect a divider.
2) crstal at some frequency and a fractional N PLL chip to output a different frequency. This way they can provide many frequencies from the same HW, but the jitter is usually poor, especially if the PLL is not in a simple ratio.
3) mems oscillator and than maybe a PLL too. I would expect these to be relatively high jitter even without a PLL.
 The mems ones got surprisingly good, but I don't think good enough here.

The good ones are not necessary expensive, just have to read the data-sheet and if in doubt (the DS are not all very specific), use a different type. There are plenty of types to choose from and I don't think the requirements are very high. I would consider 1-2 ps period jitter (down to some 10 kHz) acceptible. AFAIK this should correspont to about -140 dBc phase noise for a 10 kHz frequency offset.

[Andreas]

Concerning the jitter of the µC: Awoid or check the internal PLL.... usually a cheapo BangBang .....   have seen nice sawtooths in the f_cpuclock/timer over time ..

Hello,

Sometimes a spreading of frequency is done intentionally to reduce EMI (at least for the small band EMI receiver).
But for precision measurement this or using PLL or R/C oscillator is cruical and leads to increased noise.

with best regards

Andreas

[MiDi]

Meanwile the board got different XO (cheap Reichelt) and noise got a lot worse - around x2 (4µVacrms vs. 2µVacrms prior XO).
Seems the XO has quite high influence on noise - @Kleinstein, which one do you use?

The FW always had delay 12, but missed to change it in Pascal program
Did comparison of delay 12 & 0 in program with cheap XO and as proposed the noise with delay 0 is around 2x (4µVacrms vs. 8.1µVacrms) - this applies to the diff to the expected value as well (5.3µV vs. 10.3µV for short).

One thing I want to try is to have more delay after DG408 input mux switching, but have no idea where what to change.

The Q2 and Q8 part at the Ne5534 is a bit odd. I had not so great experience with transistors as diode and for the ARM version use 3 diodes that work quite well. The BAS21 seems to be a good compromise between leakage and recovery time for the 1 critical diode. The other 2 can be simple fast ones (e.g. 1N4148 / BAV99). With just 3x 1N4148 the weak point is dirft of the gain (likely temperature dependent leakage). With a transisistor instead of 1 diode the problem with relatively large drift of the DC level / trimmer position, likely from slow recovery. With a relatively low gain for the final amplifier the drift of the DC level may be still acceptable.

BAS21 diodes are in the pipe (with some other components) to try out.

Weird things happening: when the original 16MHz XO was put back, noise stayed at same level as with cheap XO - have to withdraw conclusion that XO has quite high influence on noise 
Have tested couple of things (e.g. another 16MHz XO), but not found the source yet - maybe easier to build second ADC.

The XO is now 12MHz and FW & Pascal program now back to standard settings.
Noise ~1.3µVacrms (short 5min), but noise distribution is not gaussian anymore as it was before.
Swapping Q2 & Q8 against BAS21 & 1N4148 @NE5534 as in Kleinsteins schematic did not change anything significant regarding noise.



Setting high delay after DG408 switching did not change anything significant regarding the offsets.
Seems overshoot and settling on DG408 output is not relevant or measurements give wrong picture 

Code: [Select]

#define rundown_wait 200          ; Length für rundown  (256 cyles = 16 µs units) standard = 6



Edit:
Another run, sitting on my bench gave different picture of noise, if just considering values >= 6µV the noise is in the ballpark at 0.53µVacrms:

[Rerouter]

I'm implementing the suggestions today, out of curiousity, could you try bodging C13 to connect to ground instead of negative ref, to see how it effects things.

[Kleinstein]

C13 to ground instead of the neg reference would not make a large difference. I had this in my original PCB and it works, but with a slightly higher (some 2.9 times) fitler cross over. The difference is likely only really visible with the testmode for INL with 2 different run-up modes. Especially the noise for reading a short is not significantly effected by noise of the reference. This only needs filtering the really high frequency part like > 10 kHz.

The non gaussian histogram shows some DNL problem. I would guess this could be some error in the constants K1 or K2. Changing from transistors to diodes in the slope amplifier would not directly effect the noise, but it can effect K2 and the main reason for a change is to get a more stable K2 value. The transistor or 2 diode form may also depend slightly on the setting of the trimmer, as the linear range is limited.

It may be worth to now check the linearity first. Without the 2nd group of points the noise looks OK (last graph with only the upper points). So fixing the linearity problem could also improve the noise. Chances are the noise would be also a bit lower with the slower modulation mode.

edit: I looked at the raw data, and it looks like the K1K2 value may be off a little. When the board is still new there is a slight chance that the resistors may still drift a little.

One of the data files includes a result of the K1/K2 meaurement:
# 9/30 22:1 with k0=150 k1=20.9638 k2=150.50
# 3R short XO 12MHz.txt
# 12 Mhz XO, long delay after switching DG408
; k1= 20.963542
; k2= 122.81373 150.326  95.301  SF= 56.55118
So the k2 values should be more like 123  and not 150 as used for the data.

[Kleinstein]

I took one datafile  (3R short P-Q-R-V-W Runup.txt) and did a correction of the k2 factor from the raw data.  This way kind of cheating - fitting K2 to give the least correlation of the resuadual ADC readings with the result and thus about the lowest noise.

Looking at just the columns 10 or 11 also support the wrong K2 values assumption: the difference from the min to max value is a bit over 120 and no way reaching 150. 

The noise goes down to to 0.78 µV rms over the data, excluding the start with mode "P", that shows more noise
This is a reasonable good noise value. Chances are just taking the slow modulation case (mode W) would give lower noise.

[MiDi]

I took one datafile  (3R short P-Q-R-V-W Runup.txt) and did a correction of the k2 factor from the raw data.  This way kind of cheating - fitting K2 to give the least correlation of the resuadual ADC readings with the result and thus about the lowest noise.

Looking at just the columns 10 or 11 also support the wrong K2 values assumption: the difference from the min to max value is a bit over 120 and no way reaching 150. 

The noise goes down to to 0.78 µV rms over the data, excluding the start with mode "P", that shows more noise
This is a reasonable good noise value. Chances are just taking the slow modulation case (mode W) would give lower noise.

My fault, took first K2 reading of console, but in console it is last value, in logs it is first
Now K1 K2 corrected:

Code: [Select]

     adcclock = 12000000;      // clock on ADC board
     scale = 6951.95;             // Ref voltage in mV 7106.8384
     xd = 12*3;                 // extra  delay 3x xdel in ASM code !!! has to match FW !!!
     k1 =  1.0 / 20.96333;   // measured ref ratios from adjustment - was formerly 20.9638
     k2 =  4.0/ 121.74;  // fine step / adc LSB - was formerly 148.5
Cold start - 50min K1 K2:


Short/Ref with corrected K1 K2 values after > 1h warmup


Edit: Quite impressive noise figure already, for a short at 100PLC it translates to <0.5µVpp or 0.05ppmpp - already on par with lowest noise 3458A (Dr. Frank)

[MiDi]

Some more results and comparison of different PLC settings with mode W runup and different runup versions.
Better cable for UART (sacrificed USB cable) and reduction of possible EMI sources has improved noise further and is now in the ballpark of Kleinsteins AVR version.