DIY high resolution multi-slope converter

[MiDi]

For the difference test with 2 run-up modes shown earlier, the 2 cases to compare may have been a bit too similar and the result thus a bit too optimistic. With more different run-up modes the difference looks a little worse, but still not too bad. The plot in the attachment shows 2 cases with different modulation frequency ( 23.5 and 61.5 kHz). The run-up parts are a bit more different and especially with some offset relative to each other. The slower modulation curve looks a little better, but not much.
The idea of the comparison at different modulation frequencies is that errors due to DA get smaller with a faster modulation. Errors from switching related interference should get larger with faster modulation. The curves look different, but no clear pointing to one culprit. It looks more like a combination of both types of error: The more shorter range periodic like part (e.g. at abound -300 mV and -1.5 V) seem to be stronger with the slow modulation (this would point towards DA).

Are you referring to this post?

I got a first higher resolution test for the difference of 2 variations of the run-up.  So the same, slowly changing voltage (capacitor charge and discharge) is measured with 2 different versions of the run-up.  Ideally the 2 versions would get the same result, but the details can vary, e.g. due to errors from DA in the integration capacitor and also coupling effects at the clock. One can see the curve (deviations from a stright line) as indication for the more wiggly parts to the INL.  INL from the amplifier, ADC input buffer and thermal effects (e.g. in the resistors) are not included. The main effects included are DA, integrator input settling and unwanted electrical coupling / supply variations.

Compared to a classic INL measurement this test is easy (not much extra instruments needed) and relatively fast (some 3 h for the curve), but still quite sensitive (low noise).

The curve is still not perfect, but allready quite good and better than in the AVR based version. The improvment is not from the different µC, but more with a better layout / better decoupling. Using a slower modulation may also be part of it: so decoupling gets less important but DA gets more important.
The points are the average over 192 conversions or 2x20 ms each.

The curve is still not perfect, but allready quite good

is a bit understatement, with linear regression by eye the wiggly part would be in the order of +-0.3µV = +-0.03ppm - what is your goal?
Top pink curve looks better than bottom one, despite the dip around -2.8V and seems to be noisier or more higher frequency wiggles between -1..-2V - difficult to compare properly.
It is a bit hard to follow which runup you used for comparison, the above curves are quite different from each other.

[Kleinstein]

The INL test form sepr. 19 was the one that was a bit too optimistic. Likely the 2 run-up mode where too similar, so I got the INL error too similar for the 2 curves. The residual error from that curve would be great, but it was to optimistic. The later curves show more like 1-2 µV of maximim deviation.

For the fast periodic part it is relatively easy to make sure that the 2 run-up versions are different: use different step size with the run-up and thus a slightly different period and thus areas where this parts adds, and where it cancels. With the other more longer range part this is not so easy, as I still don't fully understand where that effect comes from. The test with the intentional poor capacitor indicates that this is also related to the capacitor. On the other hand the effect got larger with faster modulation and also in one case (though only that one example) reacted to changes at the clock.

For the comparison of the 2 frequencies (oct. 30), what looks like extra noise in the upper pink curve is a repatable periodic part of the INL error. The noise should be rather close for both measurements, with the tendency to be slightly better in the upper curve due to less jitter effect.
Noise is a bit tricky, as more averaging also suppressed the fast periodic part.

The gaol with the difference tests and variations in the circuit was to find the mechanism that causes the nonlinearity. Somehow the measurements don't give a clear answer and are more confusing. It is definitely worth using a good capacitor and for the simple 2 pattern modulation 20-30 kHz seems to be about the lower limit for the modulation. If the noise from jitter permits faster modulation seems to be preferred.

Maybe I have to accept that there is some INL error (some 0.1-0.2 ppm range) of unkown origing. At least I could not find an easy solution ( the optional extra DG419 part could be an option). I somehow forgot to include it in the ARM based PCB  .

There are than still the 3 parts of soft INL of know origin:
The nearly periodic part from DA in the integration cap (some 0.05 ppm with 30 kHz modulation).
Some 0.7 ppm of turn over error (U² part for the 10 V range) mainly from the on resistance of the 4053. This one is compensated by the internal turn over in the differential mode (e.g. 20 V range).
Some 0.5 ppm of INL error of U³ type from self heating of the resistor array. It depends on the luck with the resistor matching. Chances are this part could be better with the 2 x 25 K in series (less heating and statstic averaging for the matching).

[Kleinstein]

I just realized that my ARM program was averaging (N+1) instead of (N) readings. So what was assumed 1 reading at 1 PLC was actually the average of 2. So the calculated noise was too low by about a factor of 1.4 . So the noise of the ARM based version is not much lower than the AVR based version. The noise is similar at some 450-500 nV for the 1 PLC AZ conversion.  Some of the time scales are thus also wrong - though in most cases the time scale is not that critical.

[Kleinstein]

Here I share are the plans for the STM32based ADC version and voltmeter front-end (amps and ohms part are planed, but not yet build / final).
I have a working DVM unit with some bodges and limitations (e.g. output to PC only, no case yet). I still don't consider the project finished, but far enough to have the  main parts working. A photo of the board was already shown.

Like some older MS-ADCs, the ADC is build around a µC and not a FPGA as many new designs.
The principle of the ADC and the analog circuit is still essentially the same as in the AVR based version. Different from the AVR version the code is in C and thus a little easier to modify / extend. It is still not easy to port to a much different µC, as non standard details of the timer hardware (trigger timer start from comparator) are used to do the critical timing part. With the ARM CPU the µC can already do the conversion to a decimal format and thus no special software needed on the PC side - just a terminal program.

The µC is an STM32L051 in 48 pin LQFP. A few similar types (e.g. STM32L053 or L071) should work as well. The availability of the STM32 µCs is poor, with the STM32L0xx a bit less critical so far, but still not good. The code is a mix of using the HAL libraries / cube MX environment for the initial configuration and direct register access later on. So the code has some of the cube MX specific files and most of the code in separate files.
The actual ADC control part is in the ISRs. The non interrupt code is for the UI and converting the raw result to a final number.

The front-end part of the DMM/DVM is a bit more complicated than the low end commercial designs. I have considered a simpler version (e.g. more like the Keithley 2000), but the savings are not that large. Part of the extra circuit is to include extra features.

The front end includes the possibility to do internal measurements of the gain and divider ratio both for the positive and negative sign.

To support linearity testing there are 2 inputs (needed for 4 wire ohms anyway) and also switching between 2 low sides. This allows an automated turn over and sum test. While currently only a DVM, provisions for the ohms mode (2 and 4 wire ohms) and extra internal inputs for the amps mode are included.
The extension to a 20 V (some 24 V maximum reading) range with high Z also needs a little extra HW.

To avoid special, expensive and large relays the maximum input voltage is limited to some 200 V (up to 400 V when brave) and I would not give the protection a CAT2 rating. So this is for lower power and limited voltage, more like a precision DMM, not for mains work. There are no AC ranges anyway.
The voltage ranges are for some 200 mV / 2 V / 20 V / 40 V / 200 V .

The board was planed to also work inside the BB3 measurement system - though not yet tested there and the interface part is not populated and SW still missing.
The EMI sensitivity makes a stand alone use more practical, at least for the initial tests.
The front end part could also be used with a different ADC. The first tests were done with the AVR based ADC version instead of the ADC on the board.

There should still be a bit of hardware optimization and quite some additional functions in the software needed.
The main hardware issues still to address are:
 - the DCDC converter can be a source of interference. The DCDC part may need a make over anyway, as the SN6505 is hard to get.
 - EMI sensitivity
 - there is some extra low level (~20 nV) low frequency noise at the input. So the noise with longer integration is not as good as hoped for.
 - some offset voltage drift (around 2 µV on warm up), likely from the protection part as the 2 inputs drift different.
 - during start up the LM399 heater current overloads the DCDC - maybe add soft start from lower voltage (Ok for stand alone, but not good inside BB3)
 - The PCB still has a few errors and needs some bodges. So I would not recommend a 1:1 copy of the layout.
 - The ESD protection is likely not really good.
 - additional protection with fusible resistors would be good as a last resort
 
The output and control so far is from the PC only, so no display or keys, but just an UART-> USB interface with a terminal program at the PC side.
So far the user interface is a bit simple: 1 letter commands with 1 digit parameters, with the digit coming first. So something for the fans of RPN calculators.
The SW has some limitations
 - the control needs delay between commands (OK for manual typing, but could be annoying for a program)   
 - the user-interface is a bit cryptic
 - the ACAL results (gain, divider, offsets) are not yet included in the result. So some of the math is still on the PC side.
 - the parameters for ADC fine tuning are included at compile time. Should be added to the SW to include at run time.
 - limited to 1 PLC conversions and averaging for higher resolution so far.

The schematics are as a PDF. If needed I can also provide the KiCad (5.1.8) files. This still need a bit sorting out the local parts/footprints.
The LTspice simulation is for the amplifier in gain 10 configuration (2 V range). It may help to understand the configuration with the driven low side.
The Code files are zipped (I hope all the required files to use in ST Cube MX are included). The compiler should use optimization also for debugging.
Debugging still works reasonable, as there is not that much optimization possible with many of the variable as volatile.

[MiDi]

A short update, now got a more automated test setup with a K236/7/8 as voltage source.
4th order RC filter (4x220µF MKS with 2x4x1k) is used to get a smooth linear slope when stepping the SMU (~2.5mV/s +-10V).
Attached the measurements mainly done to evaluate the setup - quite different results for different runup modes.
Next will be real INL test against 3458A, for this the pascal program needs to be converted to python to gain more control and easier automation of the setup.

[Kleinstein]

Are the measurements still with R10 = 6.8 K ? This would be with a relatively slow settling integrator. With the OPA145 a smaller value (like 3 K to 5 K) for R10 would be more appropriate. This would especially make a difference for the mode P with rather short time for settling. Overall the shape is similar what I have seen.

A real INL test to a 3458 would be interesting. With the relatively noisy LM399 ref. this may still take some time for averaging. So for the voltage source there is no need to have a much lower noise one, especially if the readings are at the same time. The tricky point are the jumps from popcorn noise of the LM399.  To suppress this low frequency noise one would ideally run through the sequence of test voltages several times and not just every voltage once.
For the start the interesting points would be a general overview (e.g. 1 V steps) and than maybe the readings around 0.6 V, where the DIY ADC is likely weakest.

For the start the Python program to read the data could get away with only the normal measurements. The small slope part is not needed very often and one of the more complicated parts.

[MiDi]

Are the measurements still with R10 = 6.8 K ? This would be with a relatively slow settling integrator. With the OPA145 a smaller value (like 3 K to 5 K) for R10 would be more appropriate. This would especially make a difference for the mode P with rather short time for settling. Overall the shape is similar what I have seen.

HW & FW is unchanged, first want to have a baseline for comparison incl. real INL measurements and then apply changes.

A real INL test to a 3458 would be interesting. With the relatively noisy LM399 ref. this may still take some time for averaging. So for the voltage source there is no need to have a much lower noise one, especially if the readings are at the same time. The tricky point are the jumps from popcorn noise of the LM399.  To suppress this low frequency noise one would ideally run through the sequence of test voltages several times and not just every voltage once.
For the start the interesting points would be a general overview (e.g. 1 V steps) and than maybe the readings around 0.6 V, where the DIY ADC is likely weakest.

Several challenges are expected: reading at the same time when sloping the input (jitter, interpolation), noise - especially popcorn - from LM399, temperature changes, ...
Simpler would be to check discrete input voltages, but sloping the input gives DNL (local wiggles) as a bonus.

For the start the Python program to read the data could get away with only the normal measurements. The small slope part is not needed very often and one of the more complicated parts.

Already ported the pascal program nearly 1:1 to python (attached), not cleaned up yet, but all functions should work.
To get married with 3458A & SMU there is some work left.

[MiDi]

Discovered an unexpected effect regarding the 0V offset in 3 readings mode (AZ+AS).
If the input is set to the same 0V used for AZ (S8), expectation is to read ~0µV avg, but it is ~6µV avg (run-up W).
The input mux switching (In 0V 7V) occurs after the run-down is finished and before the µC ADC reads the residual charge.
Switching the input mux after reading residual charge the result is ~0.4µV avg.
With 7V (S7) it changes from ~-7µV to ~+7µV relative to expected value.

[Kleinstein]

I have seen such an effect before. There is something near the start of this thread:
https://www.eevblog.com/forum/metrology/diy-high-resolution-multi-slope-converter/msg2532315/#msg2532315

It looks like some delayed effect / spill over from one conversion to the next.  Some such effect is expected due to DA, but AFAIR it should be less.
Another possible path is some capacitive coupling, though this should normally also be less.

As much of the delayed effect seems linear I did not worry too much about this part. It is however a problem with the 3 step cycle if the extra 7 V reading is used to correct for the gain. In this case one would need to use a numerical correction.
Moving the switching of the MUX to a later time is a good idea, at least for the more slower conversions like 1 PLC and more and especially if there is a separate reading for the initial charge of the next conversion anyway, like in the current code.

[miro123]

Discovered an unexpected effect regarding the 0V offset in 3 readings mode (AZ+AS).
If the input is set to the same 0V used for AZ (S8), expectation is to read ~0µV avg, but it is ~6µV avg (run-up W).
The input mux switching (In 0V 7V) occurs after the run-down is finished and before the µC ADC reads the residual charge.
Switching the input mux after reading residual charge the result is ~0.4µV avg.
With 7V (S7) it changes from ~-7µV to ~+7µV relative to expected value.

Just looked at schematics for first time - signal 'Res_adc' must to be decoupled with at least 10nF as close as possible to uC pin. Please follow the STM AN.
https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&ved=2ahUKEwiwuuXW6ML0AhXS_7sIHYDtBc4QFnoECAQQAQ&url=https%3A%2F%2Fwww.st.com%2Fresource%2Fen%2Fapplication_note%2Fcd00211314-how-to-get-the-best-adc-accuracy-in-stm32-microcontrollers-stmicroelectronics.pdf&usg=AOvVaw2Xw7l_zV_8OzywL7FFVi2H

[Kleinstein]

As far as I understand the µC internal ADC has 2 possible modes of operation: one with a relatively low source impedance and low capacitance (< 20 pF) at the input and the other is with a relatively large capacitance (10 nF may still be on the low side) and than possibly higher source resistance.
 
The ADC is use with a relatively long sampling time (7.5 cycles and AFAIR 8 MHz clock) and low capacitance at the input. Even with 2.2 K in series this should be still OK for the ADC to work without a capacitor directly at the ADC input. The data-sheet wants for the standard inputs < 3.2 K for 12,5 cycles and 16 MHz clock. So 2.2 K should be OK with 7.5 cycles at 8 MHz. If needed a smaller resistor (R51) would be no problem. So this is still the relatively low resistance source case with no extra capacitor.

Some 10 nF to ground would be an option too, as there is some waiting time before the ADC conversion starts. However I don't have a footprint for this on the PCB.  This would lower the BW for the residual charge, that is currently set by the relatively slow MCP6001/2 at a gain of 10 (or a bit higher).
It would need some 100 µs for settlling, so a bit on the slow side already. So one would use it would a smaller resistor to the OP.

For the AVR base version the ADC is sampling relatively slow and it can tolerate even more resistance than the STM32.

[dietert1]

Even 1 nF can help to keep the ADC input pin quiet. It depends on where R51 is (trace length between R51 and ADC input pin).

Regards, Dieter

[Kleinstein]

In my case R51 is about 8 mm from the µC pin. So not very much extra capacitance. The µC internal ADC also does not really needs its full resolution / accuracy. There is usually (1 PLC conversion) some 10 LSB of noise on the signal anyway.

[MiDi]

Did some investigation on delayed (settling) effects with interesting results - still unchanged HW & FW (Rerouter PCB ATMega48).
For this first test only the internal awailable voltages were used (0V & 7V from LM399) - results with external -7V follow.
Mode B (INL-comparison) with run-up Q is used in unusual way (FW lacks non AZ mode): repeatedly take n readings @0V followed by m readings @7V to get each step response.
The offset & scale factor are obtained from median of 200 readings in mode B on 0V & 7V before each run.

Unexpected that 0V is little effected (~0.15ppm) - in contrast to 7V, which suffers ~9ppm until it settles after ~20 readings.
From that I would exclude integrator capacitor DA & self-heating of resistors as source, but have no idea what it could be.



The impact of switching the input mux before µC adc reading residual charge is clearly visible at the last readings (0V: ~0.5ppm, 7V: ~1.5ppm) .
Seems a good idea to change the input mux switching after adc reading as indicated already in former posts:

Discovered an unexpected effect regarding the 0V offset in 3 readings mode (AZ+AS).
If the input is set to the same 0V used for AZ (S8), expectation is to read ~0µV avg, but it is ~6µV avg (run-up W).
The input mux switching (In 0V 7V) occurs after the run-down is finished and before the µC ADC reads the residual charge.
Switching the input mux after reading residual charge the result is ~0.4µV avg.
With 7V (S7) it changes from ~-7µV to ~+7µV relative to expected value.

[Kleinstein]

The observed rather slow settling is interesting.

The dielectric absorption is symmetric and would thus give a same size effect for the step up and down. In addition the DA usually does not follow a single time constant and thus a slower than exponential settling. So DA can not be the main effect for the settling. It may cause the small effect seen at 0 V.

For a thermal effect the change for the 7 V is quite large. At least with the 3 versions I have build and also with 2 more sets of resistors I have not seen that much change in the gain with temperature. With the resistor arrays the TC was not much above 1 ppm/K for the ADC gain in the AZ mode. The non AZ mode step is a little different though. One extra term is from a shift in offset from temperature, but this would also effect the 0 V measurement. So this part is small. It is relatively easy to mesure the gain TC with the program mode C and the temperature sensor as the input channel. This reads temperature, zero and the reference in a 3 step sequence. So one get the ADC gain and the temperature.

As a 3rd possible mechanism there is an effect on the reference. Switching to the 7 V ref. will cause a small current spike there, and this can effect the refrence voltage to the ADC. The low pass filter for the reference has a time constant of some 75 ms and would thus about match the observed settling.
However this can not explain the effect seen with the short 2 conversion 0 case: it seems to takes quite some time to reset the settling. A thermal effect on the reference is possible, though normally not expected to be that large and I would expect a slower reaction.

[MiDi]

Pending results on delayed (settling) effects with external -7V & 10V attached.
Looking at the results, the 3rd possible mechanism mentioned is likely (effect on the reference) - did not have that source on my screen 
I guess the unbuffered 7V to the input mux effects the LM399, although it is filtered by 100nF - 100R -100nF - let's find out.
Kleinstein later added a buffered 7V, but rerouters version is based on older schematic w/o this buffer.

Comparison between different voltages (20 readings each - 10V with different scale):

[Kleinstein]

I added the buffer for the 7 V reference only after the PCB was made. The OP was planed as a buffer for an input and only as a after-though was used as reference buffer. So the buffer was not in my initial circuit plan. I though I would need it mainly for a signal , zero and reference mode to measure the ADC gain in real time (like the Keithley 19x meters). I don't think I had actually see the effect on the reference, just the current spike to the input.

The effect of swtiching the input while the conversion is running looks a little larger than what I remember. This could be a slight difference in the parasitic capacitance.

[MiDi]

Pending results on delayed (settling) effects with external +/-7V with disconnected unbuffered 7V from input mux (100R removed) attached.

Comparing 7V vs 7Vext confirms that the input mux effects the unbuffered 7V:




Comparing the -7V gives no difference, small settling (~0.5ppm) & jump at last reading (~1ppm) remains same:

[MiDi]

Changed the firmware so the input mux switching happens after the residual charge read by µC adc.

FW Diff:

Code: [Select]

@@ -873,7 +873,7 @@ rundown:
  out portSW,t2               ; start of Rundown: start with larger Ref.; Input off
    ; may need extra delay here  (min length for phase)
  ldi t2,control_neg       
- out portMUX, nextmux        ; change MUX for next conversion : DG408 is slower than 4053, so likely no extra delay needed
+ /*out portMUX, nextmux        ; change MUX for next conversion : DG408 is slower than 4053, so likely no extra delay needed */
 
  LDI temp,1                  ; timer1 start (already 0 and OC1A flag cleared in runup prepare)
  STS TCCR1B,temp
@@ -959,6 +959,8 @@ mslope2:                  ; call point for just data collection of rundown
  rcall readAD_wait     ; ADC right after rundown;
  ldi temp, ADMUXSlp    ; MUX to auxiliary (for next conversion)
  sts ADMUX,temp
+ ; Debug change input mux after ADC readout
+ out portMUX, nextmux        ; change MUX for next conversion : DG408 is slower than 4053, so likely no extra delay needed
 
     lds temp,par_syncdel  ; extra delay to check delayed effect  (some gets hidden by wait for ADC)
     rcall longdelay       ; schon viel delay ! (startwert ist 26 -> 1.6 ms)
The results for external +-7V in mode A (AZ), run-up Q, median(1000 rdgs.) are as expected, the readings are getting closer where they should be, but still some deviation left - see attachments.
Improvement for +-7V is ~1.5ppm of range, 0V is nearly down to noise floor (<<0.1ppm of range).
To get a ratio measurement, the scale factor is calculated from input value with median(200 rdgs.) in mode B run-up Q before each run.

Comparison table:

Input	| dev to 0V in µV	| -> in ppm (10V)	| dev to +-7V in µV	| -> in ppm (10V)
7V orig FW	19.7	1.97	-27.7	-2.77
-7V orig FW	-12.9	-1.29	-19.0	-1.90
7V adc first	0.6	0.06	-9.4	-0.94
-7V adc first	0.3	0.03	-5.5	-0.55

[Kleinstein]

Part of the settling one still sees after the step in the input voltage can be from DA. In the non AZ mode this is stronger than in the more normal AZ mode, as effects from longer time scales are included. To a large part the effect from DA is linear and thus would in the AZ mode only lead to a slight (e.g. 0.5 ppm range) change in the gain.

The observed settling is a bit different for the +7 and -7 V case and thus nonlinear. For the small difference seen for the zero reading, there are a few poible nonlinear effects, like self heating in the resistor array at the integrator input. The heat can not only change the gain, but also cause an offset of the ratio of the 2 reference channels changes.  A similar effect would also effect the +-7 V test cases. The observed difference between the + and - sign case is still quite a bit larger than at zero. So there is still a bit unclear about the mechanism behind this. There is some possible asymmetry with thermal effects from the buffer amplifier, but this should be rather slow. Settling after the charge injection spike at the input of the MUX may a factor - though this shuold be quite fast. Hard to tell how much is still there for the 2nd sample after the jump.

[MiDi]

The project for the ATMEGA version is now on github: https://github.com/Multi-slope-ADC?tab=repositories
Separated into four parts:

• PCB from Rerouter - BOM & additional information under Releases
• Firmware
• ADC control program (Free pascal)
• ADC control program (Python)

[MiDi]

Part of the settling one still sees after the step in the input voltage can be from DA.

Any ideas how to test if it is related to DA?
Still do not understand why DA could be asymetric between +-7V input and why wouldn't DA then show up in the zero reading more pronounced as well?
Maybe worth to test with other run-up versions to see if they behave the same as run-up Q.
Due to lack of non-AZ mode, it would need some FW mod - either change fixed run-up in mode B for every run-up to check or even better to implement non AZ mode @Kleinstein? 

In the non AZ mode this is stronger than in the more normal AZ mode, as effects from longer time scales are included. To a large part the effect from DA is linear and thus would in the AZ mode only lead to a slight (e.g. 0.5 ppm range) change in the gain.

Both - AZ mode A and first reading of mode B - are very close together, not sure what you are referring to?
The delayed/settling at 1 PLC might not be an issue, but would show up in higher PLC settings as gain error - maybe not really relevant as higher PLCs are noisier then averaging n times 1 PLCs, but still not satisfactory.
To test if unbuffered Ref+/Ref- are still effected, R22 (Ref filter) was halved in value, see attached results.



There is a minor effect ~0.1ppmFS visible for +7V input, -7V essentially shows no change.
Might be the Ref+- buffers are effected, but the settling should be much faster then, so unlikely.
There is some gain error ~0.1ppmFS, therefore the trailing values were matched manually for better comparison and the results in the table should be handled with some grain of salt.

Comparison table mode A (AZ):

Input	| dev to 0V in µV	| -> in ppm (10V)	| dev to +-7V in µV	| -> in ppm (10V)
7V orig FW	19.7	1.97	-27.7	-2.77
-7V orig FW	-12.9	-1.29	-19.0	-1.90
7V adc first	0.6	0.06	-9.4	-0.94
-7V adc first	0.3	0.03	-5.5	-0.55
7V adc first R/2	0.3	0.03	-7.9	-0.79
-7V adc first R/2	0.2	0.02	-5.3	-0.53

The observed settling is a bit different for the +7 and -7 V case and thus nonlinear. For the small difference seen for the zero reading, there are a few poible nonlinear effects, like self heating in the resistor array at the integrator input. The heat can not only change the gain, but also cause an offset of the ratio of the 2 reference channels changes.  A similar effect would also effect the +-7 V test cases. The observed difference between the + and - sign case is still quite a bit larger than at zero. So there is still a bit unclear about the mechanism behind this. There is some possible asymmetry with thermal effects from the buffer amplifier, but this should be rather slow. Settling after the charge injection spike at the input of the MUX may a factor - though this shuold be quite fast. Hard to tell how much is still there for the 2nd sample after the jump.

The differences in the zero readings between +-7V are << 0.1ppmFS, I would consider this good enough even for 8.5 digits.

[Kleinstein]

With the external +-7 V signal there is little reason to expect an effect of R22. R22 gives low pass filtering of the reference with a time constant of about 2.8*R22*C13  or some 62 ms for the initial setting. From the test with half R22 it looks like this time constant is not what we see.

I don't see much reason why the input signal should effect the reference. The refrence switching at the ADC is to keep the current essentially constant. There may still be some effect via the supply current and maybe ground current.

The more likely reason would be a thermal effect. The resistor array heating up and this changes the gain and effecting the offset. The offset part may be the larger effect and normally this part would be corrected from AZ mode. The thermal induced offset would effect the + 7V and - 7V different (same change in voltage is opposite effect on gain). So there are symmetric and anti-symmetric parts.
The thermal effect can also be temperature dependent: the TC matching of the resistor arrays may have a square part. In my 2nd AVR version the gain has a significant 2nd order TC and a zero in the TC at around 10 C. This can vary between units and with the other resistor arrays. I don't remember a measurement of the ADC gain of the temperature. This relatively simple in mode C, reading 0, the reference and the temp sensor while the whole ADC circuit slowly warms up or cools down. This would give a curde idea on how much thermal effect to expect.

Another possible test for the thermal effect at the resistor array is heating the resistor array locally and then record the cool down to get the time constant.  This can be a bit tricky, as there is a general temperature and a local temperature gradient that can have an effect. The temperature gradient can relax a bit faster than the mean temperature.

The effect of the slow part of the DA should be largely linear. This would be linear in the average integrator voltage and the relation to the input voltage is approximately linear, but not perfect. So it should be largely symmetric between the +-7 V tests. The asymmetric part could still be from a thermal effect or maybe something else.
 
A way to check for DA effects would be with a different runup mode. Slower modulation would give a larger integrator voltage and thus more effect of DA (about proportional to modulation period, and thus 2 x more for the slow mode).

An extra non AZ mode may be a good idea, as the mode B is limited to only one run-up case. I am currently finishing the amps+ohms PCB for the ARM version and will soon have some time to look at the AVR version again, maybe add the DG419 part to reduce the DA effect.

[ogden]

Hello @Kleinstein,
I am long follower of your work, appreciate your dedication and hard work. Thank you for sharing your wizdom, if I can say so. Suggestion for n00bs - listen & learn carefully what he tells you

[MiDi]

To test for DA on the delayed/settling effect, the FW & control software was modified to run mode B in selected run-up version (formerly one of the two readings was done everytime in run-up Q):

FW hack diff:

Code: [Select]

@@ -1053,10 +1053,11 @@ mslopeB:                   ; run multi-slope, 2 Runup versions for tests
  ldi temp,255
     st  x+,temp            ; Data are send during next runup, one ADC is ready
 
+    rcall mslope1          ; 2 nd conversion
 
-    rcall runup_P3nF        ; nromal mode
+/*    rcall runup_P3nF       ; nromal mode
  rcall rundown
- rcall mslope2          ; data collecton 2nd conversion
+ rcall mslope2          ; data collecton 2nd conversion*/
     rcall control          ; Check UART
    rjmp mslopeB
Control software hack diff:

Code: [Select]

@@ -283,11 +283,11 @@ def read2 (n):              # 254, 251: 2 readings (modes A, B, E)
 
     if n == 254:
         u2 = readADC(k0[ruv])   # result of 2. conversion
         du = u1 - u2
     else:
-        u2 = readADC(k0[1])     # result of 2. conversion, mode B for INL test
+        u2 = readADC(k0[ruv])     # result of 2. conversion, mode B for INL test
         #du = u1-0.5*(u2+u2old)      # TODO should be only for mode B? Or better avg 0V reading even for mode A/E?
         du = (3*(u2old-u1)-u1old+u2)/4   # interpolate both values
 
     #f.write('{:11.3f}\t{:11.3f}\t{:13.4f}\t{:6.0f}'.format(u1, u2, du*sf, adcdiff))
     writeraw()
Comparison of 3 run-up modes were done for P: fast, Q: normal, W: slow (P shows higher noise then Q, W lower)
Edit: Results not compareable due to screwed up FW
Mode A for run-up W&P show some improvement ~0.3ppmFS vs. run-up Q - on 7V run-up P a little better ~0.4ppmFS (compared against +-7V adc first with regular R22).
W&P differ not that much, see attached four comparison for mode B for run-up Q vs. W and P vs. W (20 readings +-7V input).
In mode B the tendence is much better visualized then from the comparison table.
There is some gain error ~0.1ppmFS, therefore the trailing values were matched manually for better comparison and the results in the table should be handled with some grain of salt.

Comparison table mode A (AZ):

Input	| dev to 0V in µV	| -> in ppm (10V)	| dev to +-7V in µV	| -> in ppm (10V)
7V orig FW	19.7	1.97	-27.7	-2.77
-7V orig FW	-12.9	-1.29	-19.0	-1.90
7V adc first	0.6	0.06	-9.4	-0.94
-7V adc first	0.3	0.03	-5.5	-0.55
7V adc first R/2	0.3	0.03	-7.9	-0.79
-7V adc first R/2	0.2	0.02	-5.3	-0.53
7V adc first RU W	0.0	0.00	-6.6	-0.66
-7V adc first RU W	-0.4	-0.04	-3.2	-0.32
7V adc first RU P	0.1	0.01	-5.1	-0.51
-7V adc first RU P	-0.7	-0.07	-3.1	-0.31

I had to repeat the measurements a couple of times as there was a pronounced popcorn or 1/f noise ~1ppmFS, that did not show up in former measurements.
If it is from internal LM399 reference, it will spoil INL measurements against 3458A significantly