DIY high resolution multi-slope converter

[dietert1]

Apropos popcorn noise: In the above schematic C210 = 100 nF isn't ideal, as the LM399 zener pin is in fact an operational amplifier input and output at the same time. Better use a 50 Ohm resistor in series with the capacitor. Otherwise the circuit may exhibit RF instability, that may appear as popcorn noise.

Regards, Dieter

[Kleinstein]

As the settling effect does not get much larger in mode W, it looks like the DA is not an important part there.
The expected direction from an DA effect is more settling with mode W (slower modulation), but the observed difference is the other way around.
The thermal effects should be unaffected from the modulation.
So it looks a bit like there is some settling effect on the switching part, maybe the supply of the 4053. I don't expect the 4053 to heat up very much, as there is not much change in the power.

The interpolation for AZ mode for case B is not so much for lower noise (as a kind of digital filtering, but mainly for the difference test, so that both versions get the value for the same time. So with 3 conversions V1,V2,V3 the first and last (using the same input / conversion mode) are averaged to get a values for the same time. This is needed for the linearity test to avoid an effect of the rate of change.  For a normal reading in AZ mode, it would be possible to average 2 zero readings without an extended step response. So though actually using 2 PLC for the zero the response would be the same as 1 PLC, just with slightly lower noise and little extra latency compared to the zero and signal case.
The effect gets smaller, when more readings are averaged.
In my ARM version I have those 2 versions of the AZ mode to choose as an extra parameter. The interpolation makes sense for a classic AZ mode and is needed for the linearity test, but it makes less sense in the +- mode I use with my DVM. For the AVR version averaging is a point for the PC side only.

A series resistor for a capacitor in parallel to the ref is definitely a good idea. Not sure if 50 Ohms is best - from the impedance curve with some 30 ohms at 100 kHZ my guess would be a little lower (e.g. 22 ohms), though not much.

[MiDi]

The interpolation for AZ mode for case B is not so much for lower noise (as a kind of digital filtering, but mainly for the difference test, so that both versions get the value for the same time. So with 3 conversions V1,V2,V3 the first and last (using the same input / conversion mode) are averaged to get a values for the same time. This is needed for the linearity test to avoid an effect of the rate of change.  For a normal reading in AZ mode, it would be possible to average 2 zero readings without an extended step response. So though actually using 2 PLC for the zero the response would be the same as 1 PLC, just with slightly lower noise and little extra latency compared to the zero and signal case.

The remark

# TODO should be only for mode B?

was due to the fact that the pascal program interpolates in all modes A, B, E (see last line).
This means all measurements in Mode A/E have lower noise for value of du (values u1, u2 are uneffected).
It was fixed in the python port (interpolation only in Mode B) and improved for sligtly lower noise:

Python control progam:

Code: [Select]

     if n == 254:
         u2 = readADC(k0[ruv])   # result of 2. conversion
         du = u1 - u2
     else:
         u2 = readADC(k0[1])     # result of 2. conversion, mode B for INL test
         #du = u1-0.5*(u2+u2old)      # TODO should be only for mode B? Or better avg 0V reading even for mode A/E?
         du = (3*(u2old-u1)-u1old+u2)/4   # interpolate both values
 
     #f.write('{:11.3f}\t{:11.3f}\t{:13.4f}\t{:6.0f}'.format(u1, u2, du*sf, adcdiff))
     writeraw()
Pascal control program

Code: [Select]

       254, 251 :                  // 2 readings (modes A, B, E)
         begin
          u1 := readADC(k0[ruv]);    { result of 1 st conversion }
          if n=254 then
            u2 := readADC(k0[ruv])    { result of 2. conversion }
           else
            u2 := readADC(k0[1]);     { result of 2. conversion, mode B for INL test }
          du:=u1-0.5*(u2+u2old);


Considering the remark

Or better avg 0V reading even for mode A/E?

It is not implemented and just an idea.
It would come only at cost of one additional zero reading for first cycle, for following cycles you get that for free.
Not sure if it helps or hurts, it would shift noise from lower to higher frequency for value du.
Edit: This would be applicable even to mode C -> 3 readings - S 0 7 and a bit different to mode E -> 2 readings (S S2 (channel 2) - difference to channel 2

[MiDi]

Apropos popcorn noise: In the above schematic C210 = 100 nF isn't ideal, as the LM399 zener pin is in fact an operational amplifier input and output at the same time. Better use a 50 Ohm resistor in series with the capacitor. Otherwise the circuit may exhibit RF instability, that may appear as popcorn noise.

A series resistor for a capacitor in parallel to the ref is definitely a good idea. Not sure if 50 Ohms is best - from the impedance curve with some 30 ohms at 100 kHZ my guess would be a little lower (e.g. 22 ohms), though not much.

Thought about replacement of reference RC filter with something like R22=22Ω, C13=1mF (electrolytic, low leakage), then C210=100nF could be paralled to C13.
Idea is to mitigate influence of input current noise/changes from U9 OP07 (and +15V psu noise), size should be likely the same, cost a bit lower.
The unbuffered 7V to the input should be buffered, as there is quite some influence of input mux charge injection, but with the mod this should improve even w/o a buffer.

[Kleinstein]

When doing auto zero with a true zero it makes sense to use the interpolation. Averaging the zero before and after does not effect the result except for the slightly (by a factor sqrt(0.75) ) resuced noise. For things like the difference reading the interpolation may be good (e.g. if the common mode part drifts), but it can also be confusing. So it depends if the interpolation is wanted. For the noise measurements it is better to use it without, especially for the scattering calculated in real time, as the readings are no longer fully indetendent. Most of the time I use some averaging over mutliple 1 PLC conversions anyway and than the interpolation makes less of a difference in the noise.

Using an electrolytic cap and smaller resistor for the filter may be an option. It may still need a little longer for the filter to settle, as the electrolytic caps need quite some time for settling of DA (can be in the 10-20% range). R22 could still be larger than 22 ohms. The large cap may cause some problems if the supply is turned off very fast (e.g. with a short) from the charge searching it's way out.

For dampening possible RF, the 100 Ohms and 100 nF aready there already help, so C210 is not really needed. It is not so rare to have a cap directly parallel to the LM399, so it should not do much harm.

[MiDi]

Recognized today that I screwed up and patched the wrong branch of the FW, which had long delay between readings
The results for different run-up versions W&P are not compareable to former results, have to repeat the measurements:

To test for DA on the delayed/settling effect, the FW & control software was modified to run mode B in selected run-up version (formerly one of the two readings was done everytime in run-up Q):
Comparison of 3 run-up modes were done for P: fast, Q: normal, W: slow (P shows higher noise then Q, W lower)

[MiDi]

Next try to test for DA on the delayed/settling effect, the FW & control software was modified to run mode B in selected run-up version (formerly one of the two readings was done everytime in run-up Q):

Diffs for completeness, they did not change since last time.

FW hack diff:

Code: [Select]

@@ -1053,10 +1053,11 @@ mslopeB:                   ; run multi-slope, 2 Runup versions for tests
  ldi temp,255
     st  x+,temp            ; Data are send during next runup, one ADC is ready
 
+    rcall mslope1          ; 2 nd conversion
 
-    rcall runup_P3nF        ; nromal mode
+/*    rcall runup_P3nF       ; nromal mode
  rcall rundown
- rcall mslope2          ; data collecton 2nd conversion
+ rcall mslope2          ; data collecton 2nd conversion*/
     rcall control          ; Check UART
    rjmp mslopeB
Control software hack diff:

Code: [Select]

@@ -283,11 +283,11 @@ def read2 (n):              # 254, 251: 2 readings (modes A, B, E)
 
     if n == 254:
         u2 = readADC(k0[ruv])   # result of 2. conversion
         du = u1 - u2
     else:
-        u2 = readADC(k0[1])     # result of 2. conversion, mode B for INL test
+        u2 = readADC(k0[ruv])     # result of 2. conversion, mode B for INL test
         #du = u1-0.5*(u2+u2old)      # TODO should be only for mode B? Or better avg 0V reading even for mode A/E?
         du = (3*(u2old-u1)-u1old+u2)/4   # interpolate both values
 
     #f.write('{:11.3f}\t{:11.3f}\t{:13.4f}\t{:6.0f}'.format(u1, u2, du*sf, adcdiff))
     writeraw()
New comparison of 3 run-up modes P: fast, Q: normal, W: slow (P shows higher noise, W lower than Q) were made.
Each measurement was repeated 3 times and best with lowest noise was chosen for comparison (only values with original FW were kept in table for reference).
This time only one out of 18 showed pronounced 1/f noise, no popcorn noise was spotted.

Both modes (A/B) do not show significant differences, in mode B there is a marginal difference between run-up versions (see attachments), this means no relevant effect from DA.
There is some gain error ~0.1ppmFS, therefore the trailing values were matched manually for better comparison and the results in the table should be handled with some grain of salt.


Comparison table mode A (AZ):

Input	| dev to 0V in µV	| -> in ppm (10V)	| dev to +-7V in µV	| -> in ppm (10V)
7V orig FW	19.7	1.97	-27.7	-2.77
-7V orig FW	-12.9	-1.29	-19.0	-1.90
7V adc first RU Q	0.4	0.04	-7.4	-0.74
-7V adc first RU Q	-0.5	-0.05	-3.6	-0.36
7V adc first RU W	0.4	0.04	-7.1	-0.71
-7V adc first RU W	-0.6	-0.06	-4.9	-0.49
7V adc first RU P	0.7	0.07	-7.1	-0.71
-7V adc first RU P	-0.6	-0.06	-3.6	-0.36

[Kleinstein]

Part of the slightly different gain for the 2 run-up modes is from settling (µs time scale) of the integrator.  A faster setting of the integrator can improve on this. The gain difference corresponds to the slope seen in mode B comparing 2 versions.

It is a bit strange to see that the settling / delayed effect is similar for cases P (fast) and W (slow), but a bit different from the intermediate case.
For a DA caused effect one would expect more delayed effect for the slow mode.
Anyway the effect is small (settling to 0.2 ppm within some 80 ms is quite good).
So much of the delayed effect that I also saw with the original FW is fixed with switching the input signal only after reading the µC internal ADC.

[RikV]

Is there a Github repostory linked to this thread?

[MiDi]

Is there a Github repostory linked to this thread?

The project for the ATMEGA version is now on github: https://github.com/Multi-slope-ADC?tab=repositories
Separated into four parts:

• PCB from Rerouter - BOM & additional information under Releases
• Firmware
• ADC control program (Free pascal)
• ADC control program (Python)

[MiDi]

Took a while but now there are the promised INL measurements.
FW is same as prior - late input MUX switching (and mode B with same run-ups - not relevant for INL).
K238 was used as the voltage source with 4th order LPF and 3458A as reference.
K238 was stepped through the ranges in both directions, the ADC was set to mode A (AZ) with run-up W.
ADC & 3458A are set to 1 PLC and capture isochronous (correlated).

Fullscale -11 .. 11V:



Let's just call it good enough for 8.5 digits - limited by LM399 LF noise, 3458A and test-setup 


Problematic range around -300mV (K238 & 3458A in 1V range):



Not to bad, but spoiling the INL quite a bit - could be corrected in software

[Kleinstein]

The INL result looks really good. The 20 mV periodicity should be the run-up steps and chances are the DA could be a large part of the residual INL error. So it may be interesting to also test the range around 300 mV with a slightly faster run-up mode (e.g. version V).
For the problematic region it already helps to know where it is - the range around -300 mV is not used that much, especially not as much as readings close to 0.

Is the first, full range curve really done without auto zero mode ? In this case the noise is surprisingly small and little drift effect. This could explain why the reference noise (going up with larger voltage) is not so pronounced.

[MiDi]

Run-up Q and V will follow...

Yes, full-range is evaluated w/o zero reading and problematic region with zero reading.
Strange thing is that the noise of the readings is higher when evaluated with zero reading  .

Difference between non AZ and AZ is negligible for full-range (6 runs combined - same data as last post):



But not for the problematic region, where the curve is less noisy and better shaped with AZ (2 runs combined - same data as last post):



Direct comparison of the two runs with AZ shows very good matching, the non AZ show more deviation:



1st run (descending):



2nd run (ascending):



The lesser overall noise for the problematic region is mainly due to 3458A set to 1V range (same with K238, but should not contribute that much)

[Kleinstein]

The non AZ mode adds extra low frequency noise, but it also samples the input all the time and this redues the noise bandwidth. Longer sampling also helps with noise from 236 signal source and getting better correlation with the 3458 DMM.  The noise of the DIY ADC is only one part of the total noise and the extra 1/f noise seems to quite low.  With the 236 in the 1.1 V range the noise is already quite a bit lower and there the extra 1/f noise from the non Az mode than gets important.

The RMS noise calculated from the mutiple reading to average is more of the higher frequency noise and does not include the extra 1/f noise that effects the non AZ readings. So for the +-1 V range the non AZ mode reading get a lower RMS noise, but still shows the more jagged (noisy) INL curve. For the full range the difference may not be so relevant as there is more noise from the 3458 and the K236 source.
The 1/f noise would be visible in the difference between runs.


The choice of AZ and non AZ mode should also effect the INL error due to the slow part of the DA in the integration capacitor: In the Az mode there is a charge carry over between the signal and zero reading and thus from positive to a negative effect. This increases the INL effect for the intermediate time scales (e.g. around 20 ms). With the non AZ mode the carry over is between one conversion and the next, nearly negating the effect of slow DA, especially the intermediate time scales.
The very similar INL error for the AZ and non AZ mode thus suggests that the slow DA is not the dominant contribution to the INL.

[MiDi]

The non AZ mode adds extra low frequency noise, but it also samples the input all the time and this redues the noise bandwidth. Longer sampling also helps with noise from 236 signal source and getting better correlation with the 3458 DMM.  The noise of the DIY ADC is only one part of the total noise and the extra 1/f noise seems to quite low.  With the 236 in the 1.1 V range the noise is already quite a bit lower and there the extra 1/f noise from the non Az mode than gets important.

The RMS noise calculated from the mutiple reading to average is more of the higher frequency noise and does not include the extra 1/f noise that effects the non AZ readings. So for the +-1 V range the non AZ mode reading get a lower RMS noise, but still shows the more jagged (noisy) INL curve. For the full range the difference may not be so relevant as there is more noise from the 3458 and the K236 source.
The 1/f noise would be visible in the difference between runs.


The choice of AZ and non AZ mode should also effect the INL error due to the slow part of the DA in the integration capacitor: In the Az mode there is a charge carry over between the signal and zero reading and thus from positive to a negative effect. This increases the INL effect for the intermediate time scales (e.g. around 20 ms). With the non AZ mode the carry over is between one conversion and the next, nearly negating the effect of slow DA, especially the intermediate time scales.
The very similar INL error for the AZ and non AZ mode thus suggests that the slow DA is not the dominant contribution to the INL.

To be clear: The dataset is the same for AZ and non AZ evaluation, the raw values from adc are recorded (input & zero reading) and all processing is made offline.

The K238 (incl. 4th order LPF -3db@0.04Hz) does only contribute little noise, because the readings of ADC and DMM are correlated (isochronous equivalent acquisition) and the data processing works on those value pairs (triples with AZ).
There is no time interpolation done as usually, the differences between ADC and DMM are calculated on a per sample basis and aggregated into one datapoint for INL afterwards.
This was neccessary for the ability to ramp the input voltage continous to capture more voltage levels in one go and get the wiggly parts (bit like in the INL test between different run-ups).
This worked out somehow, but not good enough at that level were the INL is (noise from jitter exceeds 0.1ppm with 1000 rolling mean over input).

One of the best ramp INL-tests I got:


Processsing for one staircase is as follows (excerpt):
- Linear regression for dmm & adc
- Scaling adc from slope ratio of both regressions (gain normalization)
- Offset correction for adc
- Diffs between adc & dmm on a per sample basis gives INL (correlated)
- Aggregation to one point for INL

[MiDi]

Short follow-up for INL range -1 .. 1V (2 runs), no surprises:



Separated runs are attached.

[miro123]

Hello,
I have one question. What causes the consistent jump around -320mV?

[Kleinstein]

The -320 mV point is the center of the range and thus the point with a 1:1 positive / negative ratio for the feedback steps. This results in quite some change in the average intergrator voltage and the variations in the integrator voltage are large in this range. There is also the transitons from the cases with 2 postive phase in a row to 2 negative phases in a row. This effects how switching transitions can interact.

It is not totally clear what is than causing the INL error. The prime candidate is the DA in the integration capacitor, so the capacitor giving back some of it's charge only with a delay.
There are also a few other possible contributions. In my early versions I had some interaction with the clock frequency and improving the decoupling there and the extra FF for synchronization had quite some effect.

[MiDi]

Results for run-up V (faster than W, same as Q) with same setup as prior tests with run-up W.

No surprises, the noise is higher and the INL shape is slightly curved downwards to both FS sides (5 runs):



-1 .. 1V, showing the problematic region (2 runs):



problematic region in detail (2 runs):




Comparing to prior INL differences between run-up versions:

[Kleinstein]

The smaller error around -320 mV points towards DA as the reason behind that error. The effect from DA is expected to get smaller with faster modulation, while most other canditates for INL are either not effected (e.g. thermal effects at the resistors, nonlinear fet resistance, buffer amplifier) or would get stronger with faster modulation (e.g. settling effects, inductive coupling, charge injection effects).

It is a bit surprising to see quite some (still not so bad, but visible) bending / quadratic contribution to the INL with the faster (twice the frequency) modulation. The main mechanism I suspected for a quadratic term was the switch resistance and this should not be effected by the modulation frequency.

[MiDi]

Results for run-up Q (faster than W, same as V) with same setup as prior tests with run-up W & V.

-10 .. 10V (4 runs):



-1 .. 1V, showing the problematic region (2 runs):



problematic region in detail (1 run):

[Kleinstein]

At least in my SW version the modes V and Q use the same modulation frequency for the feedback, and the difference is only in the length of the shortest pulses. Here the mode V has longer min pulses (comes with the downside of a slightly reduced full scale range) and is less sensitive to integrator settling.

Even for the test in the +-1 V range some of the fine structure around -300 mV may be missed.  With faster modulation the excursions in the INL are expected to also get more local ( e.g. half the horizontal scale for modes P and V compared to W). So it may be interesting to also have a more detailed curve (e.g. -360 to -260 mV) for the faster modulation to do the comparisons to the mode W (there is already a detail curve).

In principle one could add some dithering to the ADC, at least for the slower results (more than 1 PLC). For the initial phase one could add some offset (e.g. half a run-up step), like shifting the curve some 5 or 10 mV horizontally and than average. This could smoothen the INL curve and reduce the error from local effects quite a bit.

[MiDi]

At least in my SW version the modes V and Q use the same modulation frequency for the feedback, and the difference is only in the length of the shortest pulses. Here the mode V has longer min pulses (comes with the downside of a slightly reduced full scale range) and is less sensitive to integrator settling.

Even for the test in the +-1 V range some of the fine structure around -300 mV may be missed.  With faster modulation the excursions in the INL are expected to also get more local ( e.g. half the horizontal scale for modes P and V compared to W). So it may be interesting to also have a more detailed curve (e.g. -360 to -260 mV) for the faster modulation to do the comparisons to the mode W (there is already a detail curve).

In principle one could add some dithering to the ADC, at least for the slower results (more than 1 PLC). For the initial phase one could add some offset (e.g. half a run-up step), like shifting the curve some 5 or 10 mV horizontally and than average. This could smoothen the INL curve and reduce the error from local effects quite a bit.

Corrected run-up V to have same modulation frequency as run-up Q in former post.
Is there an overview of the modulation frequencies and details for all the run-up versions?

Detailed curves around -300mV are already running, results tomorrow.

[Kleinstein]

I had an overview in an earlier desciption.
X is the parameter xdel in the program to extend the length (could be something around 10)
The length of the active phases and the fixed phases (min pulse lenght) in clock cycles are:

 P =  fast             35+3*x  , 8   , 8         
 Q =  normal        78+6*x  ,12  , 12       2nd version for mode B
 R =  short pulse   86+6*x  ,8    , 8
 V =  long pulse    66+6*x  ,18   ,18
 S,T   4 step mode             - causes extra INL error from settling
 T = dummy 4 step mode with no input signal
 U =  4 step with 0 phase
 W = slow           168+12*x ,18 , 18

So the periode lengths are in a 1:2:4 ratio

[Chen Li]

Sir, may I ask you compared with off shell commercial adc, why would us diy adc like hp do in 3458a? And have a conclusion of your project, compared with adc in 3458a, how this diy adc perform? I want to diy and share an open source dmm, and if I implement your adc design, how far it will go, 6.5 digit? Thank you very much sir.