Author Topic: DIY high resolution multi-slope converter  (Read 125745 times)

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Offline MiDi

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Re: DIY high resolution multi-slope converter
« Reply #525 on: March 19, 2022, 08:08:56 am »
Detailed curves around -300mV for run-up Q & V are added to the corresponding former posts, R & P follow.

Sir, may I ask you compared with off shell commercial adc, why would us diy adc like hp do in 3458a? And have a conclusion of your project, compared with adc in 3458a, how this diy adc perform? I want to diy and share an open source dmm, and if I implement your adc design, how far it will go, 6.5 digit? Thank you very much sir.

3458A ADC has INL <0.1ppm (HP Journal p. 14), TC ~0.4ppm/K (HP Journal p. 13), noise input short ? (~0.1µV AC RMS @100PLC incl. frontend), long term drift ? (Keysight allows up to 0.43ppm/day according to SN18A)
DIY MS ADC has INL ~0.1ppm (excl. around -300mV), TC tbd, noise input short ~0.06µV AC RMS @100PLC (w/o frontend - 3 reads ru W), long term drift tbd

Performance of a DMM with this ADC will be limited mainly by references and frontend.
E.g. LM399 is good up to 6.5 digits, selected up to 7.5 digits.
« Last Edit: March 19, 2022, 08:26:09 am by MiDi »
 

Offline KleinsteinTopic starter

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Re: DIY high resolution multi-slope converter
« Reply #526 on: March 19, 2022, 09:53:19 am »
Some modern ready made ADC chips ( AD7177,  AD4630, LTC2500-32) got impressive performance, both from the noise and also the INL. These chips are still expensive and need special drivers and a 2.5-5 V reference (the usualy high end references are 6.6-7 V). So even a ready made ADC chip would need some critical circuit around it (ref. divider and buffer, maybe input divider, input driver).
The more common SD ADCs are cheap and relatively easy to use, but they are also more noisy and higher INL (e.g. 1-5 ppm range).
The SD chips are low power and small - so at the lower end range with 5.5 and 6.5 digits they are a very viable way.
SD ADC usually also offer different choices of frequency response / digital filtering (e.g. sinc³ filter). This can help, but also make a comparison difficult.

A seprate build MS-ADC has the advantage of getting a native range of some +-10 or similar, so that one can directly measure a 10 V or 7 refrence. They can use a 7 V reference (LM399, LTZ1000,...) without an extra divider. The INL is often better than most (if not all) of the SD chips.

The DIY ADC so far is noise wise at the level of the 8.5 digit DMMs, that is comparable to the 3458 or Fluke8858 or the AD7177 ADC chip.
Speed wise the software is mainly made for the 1 PLC case, slower is included but of limited interest. Faster is possibly but not tested very much. I had initiall tests working with 100 µs integration time as well - here the data transfer is the more limiting factor. As the rundown takes some 100-150 µs the current version is never as fast as 3458 in it's fastest modes, but still OK for a normal DMM.

The last linearity measurements from MIDI are very promissing, putting it in the 8.5 digit range. My test had a little more INL (and more uncertainty in the tests), but still better than most ready made ADC chips.

For me the important point is getting the INL good enough to allow using an ACAL procedure similar to the 3458, at least for the 6 digit range. This helps expecially for a DIY project with little means to adjust the other ranges. It also helps to get long term stability, which is otherwise difficult without long experience on aging of the parts.  In this sense it is OK to combine a rather high performance ADC with "only" a LM399 reference that limits the performance to the 6-7 digit range. After all the ADC circuit is still relative simple / low cost, more comparable to the ADC in the 34401 or Keithley 2000.
 

Offline MiDi

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Re: DIY high resolution multi-slope converter
« Reply #527 on: March 20, 2022, 06:28:56 pm »
Comparison of different run-up versions:

Full-range:



Run-up V, P, R showing curves bent downwards, while Q & W seem to be quite linear.


Problematic region V vs. W (same fixed time 18/18, W has half the modulation frequency of V):



Problematic region P vs. R (same fixed time 8/8, R has half the modulation frequency of P):



Problematic region R vs. Q vs. V (same modulation frequency, but different fixed times R: 8/8, Q: 12/12, V: 18/18):

« Last Edit: March 20, 2022, 06:30:37 pm by MiDi »
 
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Offline KleinsteinTopic starter

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Re: DIY high resolution multi-slope converter
« Reply #528 on: March 20, 2022, 07:34:37 pm »
The run-up versions R, Q and V are with the same frequency (and thus similar DA effect expected), but different (increasing) minimum time for the short phase. This makes the settling of the integrator more important for case R and less important (more time for settling) for case V.
AFAIR the mode V already has a slightly limited full scale range and there is no real need to use the very short pulses like in case R.

Comparing the critcal range for V and W, there is some imporvement, but not directly a factor of 2. So the INL errors more looks like a mix of several effects ( DA and some settling/ switching related part).

One more parameter to change may be the integration time at a piece. At least 2 and maybe 4 PLC at a piece should work with only little more noise and may lead to slightly better INL.
 

Offline miro123

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Re: DIY high resolution multi-slope converter
« Reply #529 on: March 25, 2022, 10:57:42 am »
I have an question
How the INL test performed?
 - startup time / stabilization etc.
 - steps sequence
 - measurement equipment settings
 - PC post processing.
 - timing
 - logging information - temperature , at which point to sense temeprature, humidity, atmospheric pressure
To many questions. Isn't it? :-) :)





 

Offline MiDi

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Re: DIY high resolution multi-slope converter
« Reply #530 on: March 25, 2022, 03:44:48 pm »
I have an question
How the INL test performed?
 - startup time / stabilization etc.
 - steps sequence
 - measurement equipment settings
 - PC post processing.
 - timing
 - logging information - temperature , at which point to sense temeprature, humidity, atmospheric pressure
To many questions. Isn't it? :-) :)

To answer the last question first: no  :box:

startup time: ~220s
stabilization: 45s settling of 4th order LPF (postprocessed), ~400s measurement / ~4500 values for each step (as 3458A is slower than ADC, only every 2nd ADC cycle is captured quasi isochronously)
steps sequence for +-11V (see attached charts): 500mV steps (~440mV @ input), 4x ramp down & ramp up (8 ramps), +-1.1V/-300mV: 10mV/1mV steps 1x ramp down & ramp up (2 ramps)

Settings 3458A (connected to the input of ADC):
Code: [Select]
PRESET FAST
DCV {int(range)} #10V or 1V, depending on range of source (constant over one run)
AZERO ON
TARM HOLD
TRIG SYN # only capture data on read
NPLC {int(nplc)}
FIXEDZ OFF
ARANGE OFF
NRDGS 1,SYN
MEM OFF
END ALWAYS
DELAY 0
TARM SYN # only capture data on read

Settings K236/7/8:
Code: [Select]
F0,0XB{float(Source.start_value)/1000:7f},{Source.range_set},0X # Function: F0,0 = source V, B: Range setting 0 = Auto, 1 = 1V/nA, 2 = 10V/nA, 3 = 100V/nA, delay = 0 in ms
H0X # only with immediate trigger it sets the output
N1X # N1 = operate
O0P0Z0S3W0L10E-3,8X # other settings O0 = local, O1= remote sense, P5 = Filter 5 = 32 readings, Z0 = suppression disabled, S3 = 50Hz 20ms integration time, W0 = disable default delay, L compliance 0=auto range

Settings ADC:
Code: [Select]
[init()] #reset, initialise & gain corrections (k factors)
A # mode: A=AZ
[run-up] # run-up version W, Q, ...
[input_ch] # input channel of mux (0..7)

Post-processsing for one staircase is as follows (excerpt):
- Linear regression for dmm & adc
- Scaling adc from slope ratio of both regressions (gain normalization)
- Offset correction for adc
- Diffs between adc & dmm on a per sample basis gives INL (correlated)
- Aggregation of n Diffs to one point for INL

From the results of the single staircases (e.g. 8 ), the outliers are sorted out and the remaining good staircases are aggregated for final chart

Timing between 3458A and ADC is quasi isochronously, so we get correlated value pairs (triples for ADC AZ), see details in former post.
Side-note: this was a major development  task, with all the oddities of UART-to-USB-adapters, incorporating a PLL and much more little things you never dreamed of and gets you nightmares...

Temperature (humidity, atmospheric pressure) is usually stable enough for one staircase (usually <0.1°C - lab is in basement), limiting is probably most the drift/LF noise of the LM399.

excerpt of the python code to generate staircase e.g. +-11V:
Code: [Select]
src_set_values = collections.deque() # list of values for voltage source (K236/7/8), each value for one ADC cycle

# +-11V
range_set = int(2) # range of K236/7/8 - 1: 1V, 2: 10V, 3: 100V, 4: 1000V
factor = int(10**(int(2-range_set))) # multiply start/stop value for stepping in range: 1: *10, 2: *1, 3: *0.1 = *10^(2-[range])
stop_value = int(12500) # gives ~11V on ADC input due to 4th order LPF (4x2x1kΩ, 4x220µF)
stop_value_range = int(stop_value*factor) # max value in range-steps of K236/7/8, for 10V range: factor = 1 (see factor)

#Staircase +-11V
for _ in range(5000): # 5000 * ADC cycletime initial value (~220s +11V)
src_set_values.append(stop_value_range/(1000*factor))

step = int(500)
repeats = 2
for _ in range(4): # generate staircase with steps of 500mV with 2x500 values for each step (440s) going from +11V .. -11V .. +11V repeated 4 times
for i in range(stop_value_range - step, - (stop_value_range + 1), -step):
for _ in range(repeats*step): src_set_values.append(i/(1000*factor))
for i in range(-(stop_value_range - step), stop_value_range + 1, step):
for _ in range(repeats*step): src_set_values.append(i/(1000*factor))

src_set_values.append(0) # set source to 0V

Test-Setup (old picture, cable to 3458A not installed):
« Last Edit: March 26, 2022, 09:48:59 am by MiDi »
 
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Offline branadic

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Re: DIY high resolution multi-slope converter
« Reply #531 on: May 27, 2022, 12:26:58 pm »
Any updates?

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Offline KleinsteinTopic starter

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Re: DIY high resolution multi-slope converter
« Reply #532 on: May 27, 2022, 03:28:44 pm »
Any updates?
-branadic-
Currently no real news:

The software (for the ARM based version) needs a rewrite to include full control for the amps an ohms part. The current version lacks some of the relay control. My first try on a rewirte failed half way through.
For the 2nd try I have the ideas, but no code yet. It's not about the ADC part itself, but the tricky part is having things like a dual measurement and the ACAL procedure without getting too much code.

The ADC part seems to work fine: low noise (about on par with the 3458 at 1 PLC) and from MIDIs measurements the INL also looks good already at 1 PLC and a little hope that it could even get a little better with 4 or 8 PLC integration at a time (not yet tested).
The ACAL procedure still has a little more than hoped for difference between the positive and negative side, though still not too bad. It could well be the amplifier part that has problems.

The DMM frontend for the main part works but still has 3 issues:
First is with leakage at one of the reed relays. I get very slow oscillations when measureing the voltage at a high impedance source (e.g. > 5 M) at the ohms source terminal. Without the relay the lowest current range (some 2 µA FS) is missing. The problem looks fixable with an additonal CMOS switch and maybe a different relay.

A second issue is a little unexpected extra noise at the front end, like some hum or effect of supply ripple adding some 30 nV of low frequency noise to the input. So while the higher frequency noise looks good, over longer time the noise does not average out well. I suspect the DCDC converter with it's spread spectrum part that does a modulation at some 50 Hz and may thus give me a low beat frequency. The DCDC converter (SN6505) part is definitely a part to change - it is currently out of stock anyway.

The more serious weakness is with the 200 mV range of the voltmeter front-end: it too does not like a high impedance source. With more than some 100 K it tends to oscillate. I can shift the limit a little with more capacitance at the input, but no easy fix so far.
I got an idea (actually 2 versions) to modify the input section so this problem should no longer happen. It somewhat interferes with ohms readings (the ranges are cut in half and the high ohms may have a little more drift), but otherwise should work, with only slightly more noise in the 200 mV range. The change for 1 version is small enough to try as a bodge to the existing PCB. The other, more clean version would likely need a new PCB.
 
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Offline Anders Petersson

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Re: DIY high resolution multi-slope converter
« Reply #533 on: May 27, 2022, 06:24:52 pm »
Happy three year thread anniversary!
Do you have a target specification to bring us newcomers up to speed on the project scope?
 
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Offline KleinsteinTopic starter

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Re: DIY high resolution multi-slope converter
« Reply #534 on: May 27, 2022, 08:06:02 pm »
There is no real target specs. There was a rather modest one at the start of the project, looking for something like 5 µV noise and 1 ppm of INL to make it a usable 6 digit meter while keeping the circuit simple. It by now well exceeded that.

By now with small refinements (manily better resistors, layout improvements, reference filtering,  74AC74 for synchornization and the LV4053 instead of HC4053) the noise is down to about 500 nV (for 1 PLC AZ mode in the 10 or 20 V range) and thus 7 digits and more with averaging.  From the calculations the noise is not expected to go below some 430 nV with this circuit. So there is still a little noise not accounted for (e.g. supply ripple, mains hum, additional jitter), but not that much anymore.
The INL looks good enough (likely better than 0.2 ppm of FS), but the measurements at that level are hard. A minimum target for the INL is to have it good enough to use the ADC to link the DMM ranges to each other with good accuracy.

I consider the actual ADC part finished - maybe a few more INL tests and maybe SW for faster than 1 PLC conversions, but not sure if this would happen.

For me the main point now is more the DMM front end part, that is DC only. The front end so far is for ranges of 400 V(~ 300 V because of relay rating), 20 V, 3 V (using an on hand resistor, should be 2 V), 200 mV, some 1 A, 100 mA, 10 mA , 1 mA, 300 µA, 30 µA, 3 µA with limitations, optional 2 µA and lots of ohms ranges from some 20 Ohms (10 mA test current) to some 2 Gohms (8 nA test current - but limited stability, may change to 1 Gohms). In principle the calibration should be to 1 voltage and 1 resistor. The amps and Ohms part is not yet tested in this respect. The SW still needs quite some work.

The main limitations are missing AC functions, limited maximum voltage and somewhat limited protection and so far no display, but data send to the PC only, some even in a raw format. E.g. the ACAL part needs support on the PC side.
The voltage ranges are still limited by the LM399 reference. Similar the resistance reference is a plastic case foil resistor only - so not very stable either, but Ok for a proof of concept.
 

Online Echo88

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Re: DIY high resolution multi-slope converter
« Reply #535 on: April 21, 2023, 10:34:37 pm »
Came across this and assumed this is the most relevant thread for it...
https://hackaday.io/project/190528-multislope-adc

Edit: As hes apparently also on this forum and showed his design, this link is unnecessary. Doh.
« Last Edit: April 22, 2023, 04:03:07 pm by Echo88 »
 

Offline iMo

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Re: DIY high resolution multi-slope converter
« Reply #536 on: April 22, 2023, 07:20:34 am »
A pity the hacker "NNNI" is not discussing his design here (even he mentions the eevblog directly and indirectly there), perhaps the experts here could help him with the noise and none-linearity of his multislope design..
« Last Edit: April 22, 2023, 09:45:10 am by iMo »
 

Offline branadic

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Re: DIY high resolution multi-slope converter
« Reply #537 on: April 22, 2023, 07:58:25 am »
He discussed his multislope design here and was also looking for help/support at MM2022. There are even some videos on youtube by him about his design.

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Offline KleinsteinTopic starter

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Re: DIY high resolution multi-slope converter
« Reply #538 on: April 22, 2023, 08:20:46 am »
That design on Hackaday still has a linearity problem from too small resistors at the interator input: The on resistance of FETs and CMOS switches is somewhat nonlinear and this is the main cause of the square law INL. For the SN74LV4053 switches with 3.3 V supply appropriate resistors are more like 50-100 K, not 10 K.

The ADC seems to be working a bit like the MS-3 ADC of the 34401. So no extra rundown and just reading the residual charge. This means the resolution is likely somewhat limited, even though the µC internal ADC can be a little better than that of the 80196 in the 34401.
 

Offline iMo

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Re: DIY high resolution multi-slope converter
« Reply #539 on: April 22, 2023, 09:44:26 am »
He discussed his multislope design here and was also looking for help/support at MM2022. There are even some videos on youtube by him about his design.

-branadic-
Ok, my bad.. I even made a post there..  :palm:
 

Offline r6502

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Re: DIY high resolution multi-slope converter
« Reply #540 on: May 05, 2023, 11:44:15 am »
Hello all,

interesting discussion here. I have rough looked from the start to the end.

Q:
Is there somewhere a simplified scheme with a description of the of the individual sections and the timings - would be very helpfully to understand what's going on.

May be I've missed it?

Guido
Science can amuse and fascinate us all, but it is engineering that changes the world - - Isaac Asimov
 

Offline KleinsteinTopic starter

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Re: DIY high resolution multi-slope converter
« Reply #541 on: May 05, 2023, 01:11:07 pm »
I don't remember showing a really simplified version of the schematics. 

There are more of less complete versions: for the AVR version the very first post has a schematics that is still largely up to date for the ADC. The µC should however get an external clock oscillator and not use just a  crystal. The input buffer as shown has also problems.  There is some description of the parts and on the timing in the first few posts too (my 3rd / 4th post in the thread).
A part to change from the old sequence / timing is to change the input only after the µC internal ADC is read and do a 2nd conversion of the µC internal ADC for the starting value of the new conversion. So the run-down part takes a little longer.

Later on there is a plan for the STM32 based version ( https://www.eevblog.com/forum/metrology/diy-high-resolution-multi-slope-converter/msg3827432/#msg3827432) including the DVM front end.
The analog part of the ADCs is still essentially the same with only minor differences.
The main part added is synchonization of the control signals with extra flip-flops (needed with the ARM to also do level shifting).
The DVM front end part is a bit unconventional and not necessary a part to copy, though with the tweaks is works OK.
 

Offline 3roomlab

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Re: DIY high resolution multi-slope converter
« Reply #542 on: May 06, 2023, 10:49:05 pm »
Hello all,

interesting discussion here. I have rough looked from the start to the end.

Q:
Is there somewhere a simplified scheme with a description of the of the individual sections and the timings - would be very helpfully to understand what's going on.

May be I've missed it?

Guido

maybe this?
https://www.eevblog.com/forum/projects/multislope-design/?all
 

Offline NNNI

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Re: DIY high resolution multi-slope converter
« Reply #543 on: June 10, 2023, 08:40:44 pm »
A pity the hacker "NNNI" is not discussing his design here (even he mentions the eevblog directly and indirectly there), perhaps the experts here could help him with the noise and none-linearity of his multislope design..
Hello! Apologies for not being very active here, somehow I find myself more active on Discord and just got around to reading some of the threads here and randomly found a mention ;D
As for updates regarding the project, I've been writing a lot of logs under the Hackaday project documenting some of the problem fixes.
First off, regarding residue ADC noise - that turned out to be improper decoupling and layout, I investigated that here: https://hackaday.io/project/190528-multislope-adc/log/218489-a-path-forward
Second, regarding the non-linearity: I was just recently advised that the 10K input resistor's PCR was causing that since the INL curve was clearly parabolic. I don't remember exactly who it was, but they recommended using a 10K input resistor for increased resolution and better TC tracking with the reference resistances. There is one resistor in the network that's not being used for anything useful, so I'll probably reconfigure the input resistor to 2 10K in series and see if that changes the INL in some way. I also came up with a fully analog PCR compensation circuit, but that might be somewhat overkill. https://tinyurl.com/2osjob8x
I'm slowly working on fixing the ADC's problems (with every day that passes, I realize how badly I half-assed it last time  |O ) and I hope to have some good results to show in the near future. I also got hold of some TMUX1134 which I might use in a future revision.
MM2022 was quite enjoyable but a little overwhelming since I'd been in Germany for less than two weeks and being among such amazing people left me in a daze. I've spent the last nine months settling down here so not much time to work on projects.
For now, I think I'll do most of the documentation on Hackaday and update the thread I started once I get better results.
« Last Edit: June 10, 2023, 08:48:00 pm by NNNI »
 

Offline KleinsteinTopic starter

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Re: DIY high resolution multi-slope converter
« Reply #544 on: June 10, 2023, 09:06:16 pm »
With respect to INL the 10 K resistors for the input and reference are quite a bit on the low side for 2 reasons. The relatively high current makes 2 INL contributions larger:
1) the self heating of the 10 K resistor at the input in combination of the TCR of the resistor (or the relative TCR if in an array with the reference resistors. This part leads to mainly a thrid power contribution.
2) the CMOS switches are slightly nonlinear. As a crude first approximation about half of the voltage drop on the on resistance adds to the effective gat votlage and this changes the on resistance. As a first part this gives a square part in the INL. How important that part is depends on the R_on of the switches.

The reason why one would want a not too large resistors is because the resistors can add quite a bit to the noise. In my design (and also for the HP3458) the resistors contribut about half of the total ADC noise with resistors of 50 K for the input. So the resistor value is a kind of compromise between noise and INL contributions. The of the shelf arrays somewhat limit the available choices.
 
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Offline NNNI

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Re: DIY high resolution multi-slope converter
« Reply #545 on: June 10, 2023, 09:43:50 pm »
This is my first time hearing about the non-linear on resistance of analog switches, I suspected that PCR was the primary contributor to the parabolic non-linearity. Thanks for that tip, I'll keep it in mind. The SN74LV4053 has a worst case on resistance of 190 ohms at 3V, but the TMUX1134 at around the same supply voltage has 8.8 Ohms worst case.
As for the resistor values, NOMCT comes in 20K, 25K, 50K and 100K. I'll see if I can get hold of some of the higher resistance ones. 
 

Offline KleinsteinTopic starter

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Re: DIY high resolution multi-slope converter
« Reply #546 on: June 10, 2023, 09:57:20 pm »
In my ADC I use the LV4053 with 5 V supply and a measured on resistance of some 20 Ohm. With 10 K resistors (and 10 V at the input) the INL contribution is quite significant already. So even the TMUX1134 may want a little more than 10 K - maybe 20 K as a resonable lower limit. Besides the R_on a higher supply voltage also help in reducing the voltage dependence.
The 50 K resistors already allow quite low a noise and noise wise there is little need to go much lower with a 10 V or similar input range.
 

Offline iMo

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Re: DIY high resolution multi-slope converter
« Reply #547 on: June 11, 2023, 06:37:57 am »
Nice to see this thread (as well as the other related) has not bitten the dust!
Hopefully, after the years of elaborating the Multislope here, we would soon see an easy to build design with 7.5+digits resolution here :D
 

Offline NNNI

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Re: DIY high resolution multi-slope converter
« Reply #548 on: June 11, 2023, 10:26:07 am »
Has anyone already taken a look at Agilent's Multislope-IV implementation that's used in the 34410A already? I just managed to find someone who let me borrow their L4411A (which basically has the same insides as a 34411A) for further investigation. There was a small description of MS-IV in The Art of Electronics 3rd Edition pg. 921 footnote 61, but that was not very clear to me.
I will definitely be posting the results of my investigation here.
 

Offline KleinsteinTopic starter

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Re: DIY high resolution multi-slope converter
« Reply #549 on: June 11, 2023, 11:49:04 am »
The multi-slope 4 ADC is a bit strange with quite some effort. It is good for high speed (e.g. some 600kSPS for the AC mode), but not great for linearity or overall noise at low speed (e.g. 1 PLC). There is a patent that describes the basics, but leaves out a lot of the details.  I see it more like a variant of a contineous time sigma delta ADC and not so much a multi-slope ADC. Already the multi-slope 3 lacks the multiple rundown slopes of the more classical MS ADC (e.g. HP3458, 3456, Keithley2000). The main point of the MS-3 is low cost, not better performance than the older MS-2 (e.g. 3456, 3457).

The ADC type shown here in the thread is still more like a classic multi-slope ADC with a rundown, but the auxiliary ADC instead of the integrator reset. One could also see it as an improvement on the MS-3, by just adding the run-down part of the classic MS-ADC. Also the hardware side is still quite similar.
The MS-4 is a more radical change and in a different direction: even higher modulation frequency (kind of in a brute force way), switching on the voltage side and quite some effort. This is more like a step up in performance, at least with noise and speed.
A point that does not make it attractive for a DIY build is that it needs quite a lot of parts, including fast ADCs and the control part kind of needs a FPGA for the high speed. It is impressive speed, but awfully complicated.
 


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