some experimental data regarding thermal EMF at SMD resistor

[NWerner]

Hello,

I recently finished some measurements on thermal EMF at SMD resistors.  I want to share data and invite comments. I hope that these data

a) stops people from trying "low thermal solder"
b) helps peoply  layouting nV-level DC circuitry.

Experimental setup:
Custom PCB with preamplifier (Gain=101) and several resistor strings. Opposing leg was formed by copper track on PCB. Each resistor was 0805 Susumu RR series 1K82 Ohm. One end of PCB was heated by some power resistors and other end was passively cooled which should result in simple temperature gradient. Resulting output voltages (heated and unheated) were measured using DMM. Temperature at both ends of PCB was measured by PT100. Usually two measurements were taken. Those showed "good enough for me" repeatability. Reported values are rounded mean values. If anyone is interested in details regarding experimental setup I can provide these, when requested.

First different wires were characterized.
To do so, all resistor strings were open and different wire clamped at hot and cold side of PCB
Measurement of different wires (against copper track):

copper magnet wire:
74nV/K

plastically deformed copper magnet wire which was uniformly wound around mandrel forming a spring:
57nV/K

SnAgCu soldering wire
3,4uV/K

InAg soldering wire:
0,94uV/K

Isaohm wire:
-0,5uV/K


Next some resistor strings were characterized one after another.
image provides better explanation of resistor strings than text.

string A - plain string of 20 resistors:
1.1uV/K  or
54 nV/K per resistor

string B - plain string of 20 resistors soldered with InAg solder:
1.1uV/K or
57 nV/K per resistor

string E - plain string of 10 resistors:
385 nV/K  or
39 nV/K per resistor

string F and string L - string of 10 resistor groups where each group consists of 2 paralleled resistors:
F:
269nV/K
27nV/K per group

L:
273nV/K
27nV/K per group

string G - string of 10 groups where each group consists of 2 resistors in series but opposedly (is this even a word?  ) aligned.
I only know one published reference to this trick - some obscure microchip(??) app-note.
129 nV/K
6,5 nV/K per resistor

string M - string of 5 groups where each group consists of 2 resistors in series but opposedly  aligned. Contrary to G each group is connected by copper tracks from alternating sides.
Sadly I forgot my rational to test this type of string. 

82 nV/K
8,2 nV/K per resistor
I can't  explain why this performs poorer than string G 

string H - string of 10 resistors with meandric copper lines connecting each group.
seemingly meander performs poorly and does not effectively increase thermal resistance of copper tracks.
466 nV/K
47nV/K per resistor

string I - string of 10 resistors, where each resistor is oriented perpendicular to global temperature gradient.
Note that this gradient is likely distorted by copper tracks. Obviously temperature gradient must be known to use this technique in practice.
146nV/K
15 nV/K per resistor

string K - string of 10 resistors where each resistor is connected at inside border of pads.
This probably works by increaing thermal resistance of copper tracks.
261nV
26 nV/K per resistor


string D - string of 5 resistor groups each group consisting of two pairs. Each pair consists of two paralleled resistor. Pairs are serially connected but opposedly aligned.  copper tracks are meandric and connect at inside border of pad.
26nV
3nV/K per pair

[aronake]

It seems you have been doing something interesting, but i dont really understand and hence not convinced to not try low thermal solder Could you explain in more detail?

[CurtisSeizert]

Do you have the ability to connect trace 0 to the strings on the hot side and connect both leads on the cold side? I would think this might give better cancellation of things you're not trying to measure. If one is using this to provide guidance for string DAC layout, some of the setups (especially G) may mask the impact at individual resistors. It would also be helpful to have probes oriented perpendicular to the direction of the temperature gradient to make sure there is actually not a gradient along that axis. Good stuff overall and thanks for sharing. This sort of thing was very much on my mind when I was doing layout in my last board.

[Conrad Hoffman]

Seems appropriate to bring up a question I had recently. I've been using some low melting solder, tin/bismuth/silver, and wondered if anybody knew how it performed for thermal emf against copper? Turns out it's pretty common stuff and can be had from Digikey. Brittle and not great conductivity, but seems to flow well and works like, well... solder.

[Kleinstein]

An interesting test. It looks like a reasonable way to get it at least somewhat quantitative.


For the effect of different solder types one likely gets compensation from both sides of the resistors. To really see an effect of the solder one would have to mix 2 solder types on one resistor.
With the usually good symmetry around resistors the 2 solder joints will compensate well and nothing is visible.

It is somewhat odd to divide the voltage by the number of resistors. The voltage is the sum over the resistors, but the temperature difference is also distributed.
In this sense it makes sense that the short meanders in string H likely concentrate more of the temperaure gradient at the resistors and less at the trace part.

[ch_scr]

I guess this is the Microchip App note (AN1258) you reference?

[CurtisSeizert]

Seems appropriate to bring up a question I had recently. I've been using some low melting solder, tin/bismuth/silver, and wondered if anybody knew how it performed for thermal emf against copper? Turns out it's pretty common stuff and can be had from Digikey. Brittle and not great conductivity, but seems to flow well and works like, well... solder.

I found the value at one point, and don't remember it exactly, but it is worse than lead free solder. I want to say around 6 uV/K, but I am sure someone with the value at hand will fact check that.

Regarding the OP, you bury the lede a bit here - the identical values using two solders with Seebeck coefficients you have characterized in the experiment seems to suggest that the observed effects are attributable to the resistors alone. In my first comment, I didn't really understand how the connections were made, but it's obvious that the amplifier is on the board, so I withdraw that objection. I still am not 100% clear on this though. It would be helpful if you could show the whole board layout. Also, I can't tell this to a certainty by looking at the picture, but it looks like you have a ground plane on the bottom based on color. Is this the case? Could you comment on the layer count and stackup?

I am not saying you should make another board, but I would think the ideal design of the board would be one where one prioritizes having a predictable thermal gradient. I would use a four layer board with ground planes on three layers and thermal vias. At the ends where you are applying or removing heat, it would be good have a lot of thermal vias and large areas where the solder mask is removed so you can solder heat pipes onto both sides of the board perpendicular to the intended thermal gradient axis. This would seem to do the most to ensure the temperature differential between two points of the board is easy to characterize from position alone. This experimental setup is certainly capable of showing the impact of solder, but with significant uncertainties around the nature of the thermal gradient, it becomes somewhat difficult to apply these results to layout.

Having just laid out a nanovoltmeter, I'll give the considerations I weighed as they may suggest avenues of experimentation:
-placement of things that dissipate power to minimize thermal gradients at sensitive nodes. I would have liked to use FIE to simulate different designs, but I don't have access to such tools so I listed out the largest dissipators using envelope calculations or SPICE simulation and placed things that dissipated approximately equal amounts of power on opposite sides of sensitive nodes.
-Routing key differential signals next to each other and placing junctions symmetrically about the axis of (assumed) temperature gradient
-Using 0402 resistors and no-lead packages (DFN, QFN, etc.) where feasible for minimizing space between sensitive junctions.
-Balancing the size of traces at the ends of discrete resistor dividers and orienting them perpendicular to my best guess of the direction of thermal gradients.
-Using minimal lands on the largest dissipators to minimize conducted heat transfer.

It would be interesting to know the impact of different resistor sizes and the amount of padstock in the footprint to see how that changes things. The other question in my head during layout was "how bad will this be if I am wrong about the thermal gradient here," which would suggest experiments where a certain resistor string is oriented at two different angles to a known temperature gradient. That is a crucial issue because different operating conditions (for example, changes in power dissipated along gain-setting resistors) would hopefully have little impact. I would assume that anyone laying out nV-level circuitry has a general familiarity with how to orient things in the ideal case when the temperature gradient is known, but minimizing the impact of uncertainties or forced non-idealities in thermal layout (for example, when trace length needs to be minimized because a node is sensitive to parasitic capacitance) is more difficult. I believe this sort of information would provide the greatest value for anyone laying out low level dc boards. I personally based my design decisions on assumptions from first principles, as well as common design guidelines, but some of those assumptions were probably wrong, and some of those guidelines may not be well grounded. For you to suggest a systematic and quantitative evaluation of this is good science, and I appreciate that you have done the work and are sharing the results. As such, take these suggestions as potential avenues for improvement on what I consider nonetheless to be very positive work. Some things, like substituting resistors could even be implemented with this board.

Also, this isn't criticism because I am sure everyone understands what you are talking about, but for "opposedly" the word you are looking for is "oppositely", and for "meandric", the word is "meandering".

[NWerner]

It seems you have been doing something interesting, but i dont really understand and hence not convinced to not try low thermal solder Could you explain in more detail?

Thanks for asking 

InAg solder exhibits only 0,94uV/K while SnAgCu shows 3.4uV/K. Nonetheless strings A and B show only little difference. String B which was soldered using InAg even turned out slightly worse than string A which was soldered using SnAgCu. I see no evidence whatsoever that "low thermal solder" is a sensible mean to reduce thermal EMF.

[NWerner]

It is somewhat odd to divide the voltage by the number of resistors. The voltage is the sum over the resistors, but the temperature difference is also distributed.
In this sense it makes sense that the short meanders in string H likely concentrate more of the temperaure gradient at the resistors and less at the trace part.

Not all strings have same number of resistors. But all strings are subjected to same overall temperature difference.

In my understanding the key to achieve low thermal EMF in this situation is to
minimize thermal differences where it matters (at resistors) and having maximum thermal difference where it is nicely compensated (along copper tracks).
I like to think in terms of a "temperature divider" along the lines of  a voltage divider.

For me it is however not always clear how to do so.  During layout of meander in string H - I eg foolishly assumed that heat is only conducted alongside coppertracks and that by maximizing copper track length I would maximize  it's thermal resistance and hence the temperature difference along the copper track. I totally forgot to check heat flow by PCB substrate. 

[NWerner]

It would be helpful if you could show the whole board layout. Also, I can't tell this to a certainty by looking at the picture, but it looks like you have a ground plane on the bottom based on color. Is this the case? Could you comment on the layer count and stackup?

Standard two sided FR-4 board. 1.55mm overall thickness with 35um copper.
no ground plane under resistor string but only at edges of board in heating/cooling area.
heating/cooling area electrically insulated but thermally
coupled to larger aluminium heatsink.
find gerber and eagle files attached

I am not saying you should make another board, but I would think the ideal design of the board would be one where one prioritizes having a predictable thermal gradient. I would use a four layer board with ground planes on three layers and thermal vias. At the ends where you are applying or removing heat, it would be good have a lot of thermal vias and large areas where the solder mask is removed so you can solder heat pipes onto both sides of the board perpendicular to the intended thermal gradient axis. This would seem to do the most to ensure the temperature differential between two points of the board is easy to characterize from position alone. This experimental setup is certainly capable of showing the impact of solder, but with significant uncertainties around the nature of the thermal gradient, it becomes somewhat difficult to apply these results to layout.

Your approach makes it certainly easier to apply results to modern multi-layer layouts with planes. Such a board is certainly on my TODO-List. I guess that a
lot of differences will be reduced by planes so even more care is needed during experimentation and thermal gradient will be harder to predict.  Unfortunately I lack  FEM skills. But I guess that such
test boards are needed to transfer results into real-world-layouts.

Having just laid out a nanovoltmeter, I'll give the considerations I weighed as they may suggest avenues of experimentation:
-placement of things that dissipate power to minimize thermal gradients at sensitive nodes. I would have liked to use FIE to simulate different designs, but I don't have access to such tools so I listed out the largest dissipators using envelope calculations or SPICE simulation and placed things that dissipated approximately equal amounts of power on opposite sides of sensitive nodes.
-Routing key differential signals next to each other and placing junctions symmetrically about the axis of (assumed) temperature gradient
-Using 0402 resistors and no-lead packages (DFN, QFN, etc.) where feasible for minimizing space between sensitive junctions.
-Balancing the size of traces at the ends of discrete resistor dividers and orienting them perpendicular to my best guess of the direction of thermal gradients.
-Using minimal lands on the largest dissipators to minimize conducted heat transfer.

I may suggest an additional point as it relates to the data obtained:
- don't squeeze sensitive components in small area. Compare eg. results for string A and string E
and think about how bigger distance between components reduces temperature difference across those components.

The other question in my head during layout was "how bad will this be if I am wrong about the thermal gradient here," which would suggest experiments where a certain resistor string is oriented at two different angles to a known temperature gradient. That is a crucial issue because different operating conditions (for example, changes in power dissipated along gain-setting resistors) would hopefully have little impact. I would assume that anyone laying out nV-level circuitry has a general familiarity with how to orient things in the ideal case when the temperature gradient is known, but minimizing the impact of uncertainties or forced non-idealities in thermal layout (for example, when trace length needs to be minimized because a node is sensitive to parasitic capacitance) is more difficult.

This is achilles heel of string I. the beauty of string F and  G is that they don't rely on a priori knowledge about temperature gradient.
I expect paralleling to be even more effective when resistors are stacked. In fact I just prepared a string for this. Hopefully results will be
available 'till sunday.

Also, this isn't criticism because I am sure everyone understands what you are talking about, but for "opposedly" the word you are looking for is "oppositely", and for "meandric", the word is "meandering".

[Overspeed]

Hello

Interesting project , be careful on the PCB strain as long thin track can vary in resistance as a Strain Gage

A simple mean is to rest the PCB by using soft Oring allow to provide stress free mounting for precision tests

I will follow this interesting test

Regards
OS

[NWerner]

This is achilles heel of string I. the beauty of string F and  G is that they don't rely on a priori knowledge about temperature gradient.
I expect paralleling to be even more effective when resistors are stacked. In fact I just prepared a string for this. Hopefully results will be
available 'till sunday.

Small update:
when paralleling two resistors by stacking instead of placing them side by side thermal EMF totals
252nV/K or
25,2nv/K per group

very unimpressive when compared to string F (27nV/K per group). This "optimization" is hardly worth the hassle.