feedback/shunt ammeter design

[Crossphased]

I'm putting together a piece of test equipment similar to the joulescope, with higher sample rate and much better bit resolution. Perhaps this could be a digitizing solution others could use as well. It will be open source of course. First part to tackle is the current sense.

Target specs are:

0-5A
1nA resolution
DC-500khz, maybe DC-1Mhz if possible
low burden Voltage ( <40 mV)

For low currents, (less than say 10mA) a transimpedance amplifier seems wise. OPA192 was chosen as first opamp. It has similar offset to OPA189 but has only 5pA bias current. There is 5k resistor in the feedback loop to allow for wide dynamic range of currents. Followed by a gain stage which performs two functions: provides some initial gain, brings the signal output back to positive polarity (not inverted). A small amount of capacitance on the output to stabilize the loop. This is switched to next gain stage.

Larger currents are measured via shunt. The individual shunts are selectable via fets. Part selection here was challenging. The ideal components would have low capacitance, and low Rds_on. Low C_ds  requires a physically smaller part, which tends to higher Rds on. If you have any better component suggestions, please advise. Two shunt selection FETs were placed in series (common source) to lower the capacitance for each "switch", and also to help lower leakage current. Negative gate voltage of -5V should help with leakage currents. The shunt voltages are fed to OPA189 which also does gain of 5. Then to the selector switch.

After selector switch is is composite amplifier. OPA189 auto zero in front for good dc performance followed by fast amplifier AD8065. Each amp has its own FB network for stability. I haven't done composite amp before so if you have better design in mind please advise. I wasn't sure if outer loop needed to be compensated or not. The outside FB network has default 200k resistor, and then other resistors added in parallel, to lower the value of the FB resistor. This provides gain ratios of 2,5,10,40, and 201. Total gain of 10, 25, 200, 1005. MAX4614 does the switching. It has good performance. 1k resistor placed in front of the switch to help isolate off capacitance of the switch from the output.
Edit#1: put 1k resistor in front of each switch
Edit#2: replaced TMUX1119 w/ FETs. Realized this needs to be make before break
Edit#3: switches changed from ADG721 to ADG1221
Edit#4: differential amp LT6373 and ADA4003 added



Here is picture of schematic, but pdf also attached because its hard to see part numbers and such in schematic picture. Any feedback is welcome. The next step is putting together differential driver for the ADC, and ADC selection.

[Kleinstein]

The nominal offset of the OPA192 is good, but the drift is not that great.  So I would not consider the OPA192 a really good choice. The 5K resistor in the FB is relatively small. At higher currents one would get quite some heating of the resistor and the OP. So the TIA allready starts showing weaknesses from some 1 mA on.

The composite amplifier at the output has some flaws: the switches are in sereis with the gain setting resistors. So the gain would not be very stable. There are usually better ways, e.g. by having the divider at the outut side and only switching the feedback path to the OP.
With a fixed gain for the inner amplifier the low gain setting will likely have a stability problem. So usually one has to switch the gain of both amplifiers: one MUX (e.g. 1/2 of  HC4052) for the inner amplifier and the other halt for the total gain. Usually the gain of the inner amplifier should be a little lower than the total gain. Only at very high total gain the inner gain should be limited to about 1/3 the GBW ratio of the OPs times the square root of the total gain.

I see littel need for so many amplifier settings: the full scale voltage for the shunts is usually relative fixed and thus not much gain switching needed.
The TIA output is more like a high voltage and thus no need for the extra fixed amplifier stage after the TIA. It would be more that one could consider a divider to get levels comparable to the shunts. So the switching would be chosing the shunt path, the TIA direct and the TIA with a divider.

[Crossphased]

Thankyou as always for your excellent replies Kleinstein. You are a wealth of knowledge and I always enjoy your rich with experience feedback.

The nominal offset of the OPA192 is good, but the drift is not that great.  So I would not consider the OPA192 a really good choice.

Quite right, did not notice the drift. I'll stick with OPA189 then for first OP.

The 5K resistor in the FB is relatively small. At higher currents one would get quite some heating of the resistor and the OP. So the TIA already starts showing weaknesses from some 1 mA on.

I think I misunderstand here, are you suggesting 5k is too small or too large? I agree, at 5k, only good up to ~1mA, or too much heat dissipation. Will reduce that to 1k. Its difficult to find a balance of getting good resolution at nA range, but still have higher ranges available. 1nA*1k = 1uV, then gained to 5uV on next stage so I guess that's ok. At 10mA that's (.01^2)*1k = 0.1W, that's doable. Will split 1k into two 500R for good margin.

The composite amplifier at the output has some flaws: the switches are in series with the gain setting resistors. So the gain would not be very stable.

Do you mean because of changing Rds_on of the switches due to temperature? I considered that, but according to the datasheet for MAX4614 the on resistance flatness is 1 Ohm over 0-85 C. So 1R change out of the smallest leg, 7.2k, is not too much. Then that in parallel with the other legs makes it very small change. I see what you mean though. I just looked at HC4052 datasheet and it changes on resistance by a factor of 3 over the temp span. That would definitely lead to unstable gain!!

There are usually better ways, e.g. by having the divider at the output side and only switching the feedback path to the OP.

Oh I see what you mean, got it- divider string of resistors, and switching tapped resistor to inverting input. Makes sense and then the switches don't carry current. Cool.

With a fixed gain for the inner amplifier the low gain setting will likely have a stability problem. So usually one has to switch the gain of both amplifiers: one MUX (e.g. 1/2 of  HC4052) for the inner amplifier and the other halt for the total gain. Usually the gain of the inner amplifier should be a little lower than the total gain. Only at very high total gain the inner gain should be limited to about 1/3 the GBW ratio of the OPs times the square root of the total gain.

I see littel need for so many amplifier settings: the full scale voltage for the shunts is usually relative fixed and thus not much gain switching needed.
The TIA output is more like a high voltage and thus no need for the extra fixed amplifier stage after the TIA. It would be more that one could consider a divider to get levels comparable to the shunts. So the switching would be choosing the shunt path, the TIA direct and the TIA with a divider.

I agree not so many amplifier settings are needed.
Figure for 1nA we get 5uV out of TIA, it would be nice to have 1000 gain to get to 5mV for ADC. Then have a good span 1nA-900nA (5mv-4.5V), with 1000x gain
Now 1uA, takes us to 5mV already,  don't need any more gain in microamp land
1mA, well that requires attenuation as you suggested. Ok, will fix that part.

As usual Kleinstein, you are totally right. Changing to fixed gain for shunts, and attenuation for TIA. With fixed gain of shunt amp will set the gain of the second OP higher. Thank you as always, you are very helpful!

[Crossphased]

After quite some thinking and analysis, a better approach was found. For the TIA, measuring over 3 decades of range requires variable gain somewhere. Either switching the FB resistors, or variable gain post TIA, or switchable attenuation post TIA. It seems the simplest and best accuracy is switching the FB resistor in the TIA. Using the largest resistor possible per current range.

Some simulation was done with OPA189, and it performs very well at DC, but very poorly above  ~200-250 khz in TIA configuration! I found most op amps had quite reduced gain bandwidth in transimpedance configuration. A good compromise was found: OPA380. Not quite as good at DC as OPA189, but much wider bandwidth performance.


Method for switching the FB resistor was found here: https://www.analog.com/en/analog-dialogue/articles/programmable-gain-transimpedance-amplifiers.html
Two switches per resistor. An interesting part is ADA4350, which is variable gain transimpedance amp with all those switches built in. Quite an expensive part though! $26.

The shunt amp was improved as well, with composite amp. The OPA189 for DC accuracy and the AD8065 to provide the bandwidth. Doing some simulation with two series OPA189 in X10 configuration like in uCurrent, it starts to lose accuracy above ~700 khz. So composite amp was chosen, and simulation shows it is accurate to above desired BW of 1 Mhz.
updated schematic in original post and below

[David Hess]

After quite some thinking and analysis, a better approach was found. For the TIA, measuring over 3 decades of range requires variable gain somewhere. Either switching the FB resistors, or variable gain post TIA, or switchable attenuation post TIA. It seems the simplest and best accuracy is switching the FB resistor in the TIA. Using the largest resistor possible per current range.

A TIA made with a log amplifier can achieve better than 1% accuracy over more than 6 decades.

[Kleinstein]

The switching of larger signals does not work with single MOSFETs (at least not the normal ones), because of the parasitic reverse diode. One should use CMOS switches there.
The leakage from the switches limits the range to low currents when using it for low currents.

The OPA380 is more like made for low currents and a FB resistor >> 10 K. If more BW and lower noise is wanted from a TIA, one can build a similar TIA from 2 separate OPs.

[Crossphased]

Thank you for that David, much appreciated.

Would you suggest an off the shelf log amp, or rolling your own log amp? If rolling your own, do you have to temperature stabilize the diode to avoid distortion, or somehow compensate for temp changes? Just curious what your approach would be. I may stick with the current approach, but it is good to hear this suggestion from you.
Cheers

[Crossphased]

The switching of larger signals does not work with single MOSFETs (at least not the normal ones), because of the parasitic reverse diode. One should use CMOS switches there.
The leakage from the switches limits the range to low currents when using it for low currents.

The OPA380 is more like made for low currents and a FB resistor >> 10 K. If more BW and lower noise is wanted from a TIA, one can build a similar TIA from 2 separate OPs.

Thank you as always Kleinstein. I'm always grateful for your expert advice.
Ok gotcha - CMOS switches for the switching of the FB resistors.
Now regarding building TIA from 2 separate OPs, would this be similar to composite amp with accurate DC first amp and high speed second OP? Its a good idea. I'm wondering if the OPA189 would be suitable in this case.


And now a related question:
The voltage will be sensed as well, with high bandwidth also. An objective is to capture the phase relationship between V + I. Not so important with the TIA range of currents, but at the higher currents the phase relationship of V to I is important.  How does one maintain the phase delay / group delay between the two different signal chains? Or I guess more precisely, how does one extract the phase delay from a given OP and gain configuration?
Thank you very much
Cheers

[tszaboo]

Did you consider using an instrumentation amplifier? Those are great for these purposes.
Also for 5A you might already want to use 4 wire method, so these stacked shunts and "measure against GND" might already give you errors.

[Kleinstein]

The composite TIA would essentially look like the internal circuit shown for the OPA380. So a AZ OP as integrator to correct the DC/ low frequency error and that a fast OP for the main part / ouput. The OPA189 has a relatively high current noise. So it may be OK for the relatively high current ranges, but is no that good for really low currents (e.g. FB resistor > 50 K). The AZ OP would not see a higher voltage, so one is free to use a low voltage type (e.g. OPA388).

Using 4 wire connection is important for the very high currents and it can still be combined with a stacked set of shunts. The connection between the lowest 2 shunts should be low impedance.

For the phase relation-ship one would likely need to do a calibration anyway. So the amplifiers for voltage and current are still made to have a stable (and thus usually low) phase shift, but the actual phase shift / delay is measured and than taken into account in the math after the ADCs. There are some multi channel ADCs made for power measurement that include extra delay adjustment. This may simplify the math a little. The adjustment / calibration would than be with some low inductance / low capacitance resistors as a load, a little like the calibration measurements at a VNA.

[David Hess]

Would you suggest an off the shelf log amp, or rolling your own log amp?

Either is feasible.  Analog Devices appears to have discontinued all of their old log amplifiers, but they still make some, albeit in difficult to use packages.

If rolling your own, do you have to temperature stabilize the diode to avoid distortion, or somehow compensate for temp changes?

If you make your own, then either the temperature of the logging transistor can be stabilized, or an external thermister can be used for correction.  However this still requires a matched transistor.

The major complication if it can be called that is that log amplifiers are inherently unipolar, but there are ways to handle this like with a log inverter which uses a pair of matched transistors to reverse the input current, or with a PNP transistor log amplifier.

[Crossphased]

Ok got some more work done on this. Thanks to Kleinstein for suggesting CMOS switches for the FB resistors. ADG721 look like good switches. Low leakage, low rds_on, low charge injection, fast switching, and allows for make before break. Picked that part to use for signal switching.

Also put together the TIA configuration Kleinstein suggested. Works pretty well after tweaking the values a bit. I found the large value input resistor to the integrator opamp caused a bit of an offset on the output. Decreasing the size of this resistor to 10K left an offset voltage of only a few uV. Very good. Intersting offset correction. Took some thinking to see how it was working. I like that OPA388 part, very low offset. Added an inverting OPA388 on the output of TIA to flip the phase back to being in sync with the input (or close to it). Things are looking much better.

Also a buffer was added to the two lowest shunts. I'm curious what the full meaning of the comment on req't for low impedance path to ground for the lowest two shunts. Did you mean low impedance path between the ground side of the shunt, and the ground pin of OPA189 in composite amp? In that case removing any offset from current in ground plane? Or did you mean low impedance path like measuring the high current shunts with diff amp? I'm thinking you mean voltage offset from current in ground path. Here's a question for you though, what if VSS of OPA189 is not connected to GND, but to negative supply? What would ensuring low impedance path mean in that context?

See attached updated schematic.

[Crossphased]

The OPA380 is more like made for low currents and a FB resistor >> 10 K.

Were you able to determine this by the size of the input resistor to the integrator in OPA380 datasheet?

[Crossphased]

Using 4 wire connection is important for the very high currents and it can still be combined with a stacked set of shunts. The connection between the lowest 2 shunts should be low impedance.

could you explain a little more what you mean by this? I'm not sure I follow. Thank you very much.

For the phase relation-ship one would likely need to do a calibration anyway. So the amplifiers for voltage and current are still made to have a stable (and thus usually low) phase shift, but the actual phase shift / delay is measured and than taken into account in the math after the ADCs. There are some multi channel ADCs made for power measurement that include extra delay adjustment. This may simplify the math a little. The adjustment / calibration would than be with some low inductance / low capacitance resistors as a load, a little like the calibration measurements at a VNA.

Thank you very much for this, it was a question that was bothering me. Very good and simple solution. As always thank you for your advice

[Crossphased]

Either is feasible.  Analog Devices appears to have discontinued all of their old log amplifiers, but they still make some, albeit in difficult to use packages.

If you make your own, then either the temperature of the logging transistor can be stabilized, or an external thermister can be used for correction.  However this still requires a matched transistor.

The major complication if it can be called that is that log amplifiers are inherently unipolar, but there are ways to handle this like with a log inverter which uses a pair of matched transistors to reverse the input current, or with a PNP transistor log amplifier.

Thank you much for your tips and advice David. You are very knowledgeable and I always enjoy reading your contributions. Thank you for the assistance

[Crossphased]

Did you consider using an instrumentation amplifier? Those are great for these purposes.
Also for 5A you might already want to use 4 wire method, so these stacked shunts and "measure against GND" might already give you errors.

Yes I checked some In amps. I didnt check extensively, but looks like most of them have higher offset voltage, like min 15-25 uV, and lower bandwidth, couple hundred khz. I was shooting for ~1M bandwidth, but min 500k. Is there an In amp you can suggest that would work well for this case? Or make your own with  LTC5400?

[Kleinstein]

There is usually no real need for an INA. There is mainly the lowest shunt would a separate low side therminal to care about. One can do this with a careful layout and having that low side pin as the analog ground point. So the amplifier gain would be relative to that point. Many higher ADC chips have a differential input an can use this to compensate for a small shift on the low side.

Chances are the offset specs are not that critical - especiall if the signal is going to an ADC and thus control over the digital side. It is mainly if the signal goes to a ready made DMM or panel meter, that one case about the absolute offest. The more critical parameters are normall offset drift , noise and for the low currents ( < µA)  also input bias current and maybe current noise.
Especially with higher BW noise tends to become important.

For the switches at the TIA, it depends on the supply range. A TIA works best when the amplifier can also use a little higher voltage, as this gives more dynamic range. So a switch for 5 V only may not be such a great solution. There is also a balance between leakage and on resistance - low resistance switches tend to have more leakage. The circuit shown would not care mich about the switch resistance and could work with higher resistance too. So I don't think the ADC721 is suiteable for the circuit. I would more consider DG20x or DG40x type switches, depending on the supply. The TIA has more dynamic range that the direct shunt and may thus not need so fine steps resistors, so 1:100  steps may be enough, so less switches and thus less leakage.

[tszaboo]

Did you consider using an instrumentation amplifier? Those are great for these purposes.
Also for 5A you might already want to use 4 wire method, so these stacked shunts and "measure against GND" might already give you errors.

Yes I checked some In amps. I didnt check extensively, but looks like most of them have higher offset voltage, like min 15-25 uV, and lower bandwidth, couple hundred khz. I was shooting for ~1M bandwidth, but min 500k. Is there an In amp you can suggest that would work well for this case? Or make your own with  LTC5400?

You have to be careful on how that offset voltage is defined. Some of it is input and some of it is output referred. For example if it is defined as ±10±100/G µV typical, then with a 100 gain, you only have 11µV offset.
I see the INA849 for example is quite fast INA. Or LT1102, AD8229.

There is usually no real need for an INA.

Usually not, and they are more expensive than regular opamps. I like using them because of the excellent CMRR, which is usually neglected when designing with regular opamps. The matching errors between discrete resistors could upset a traditional designs. They are also very well characterized, less chance of errors. Versatile due to the ref pin.
Perfect for shunts where you have high gain, and want to have zero loading of the shunt ie with bias currents.

[Crossphased]

Hello,
I have an update. The schematic has become more finished. Voltages, labels, decoupling caps have been added. Also, as Kleinstein pointed out, CMOS switches with higher Rds on have lower leakage. The ADS721 has been replaced with ADG1221. ADG1221 has higher on resistance, ~120R, but only 2pA leakage. The on resistance will not matter as it is within the feedback loop of the TIA. Also the ADG1221 has wider supply range , allowing for larger range of currents. I found 3 shunts were still necessary however, to cover the wide range of currents: nA, uA, mA.

To select between TIA or shunt amp output requires lower resistance switch, as the switch is in series with fully differential amplifier. Too high of resistance throws off the gain balance. For this switch, ADG1421 was used- only 2 Ohms on resistance. ADG1421 feeds fully differential amplifier LTC6373, then filter network, then AD4003. Also, fast comparator LT1715 used to detect when range switch is necessary. The ADC: AD4003 is 18 bit 2Msps SAR ADC. A faster 5 Msps ADC would be nice but price quickly climbs with sample speed.

Digital isolator on the output of AD4003, which will feed USB powered controller, either microcontroller or FPGA. Most likely FPGA, as SPI bus speed needs to be 100 Mhz to read out the ADC @ 2Msps. Next steps to complete:
  -power isolation from digital side to analog side
  -analog volt measure section
  -controller and USB interface

See attached schematic

[Kleinstein]

I see very little need for the extra buffer U24. The output from the sunt is well low enough in impedance. There is also little need to switch the ouput at the shunts - it should be OK to take all the shunt signals from the 10 Ohms shunt. A tap in between my be needed of there are very large shunts (like >10 K) because of noise and maybe effect of leakage.

I don't think the extra phase inverter for the TIA is a good idea. Inversion can be better done in software.

C70 at the compound TIA can probably be larger, so that the cross over from the conventional OP to the AZ op is at a lower frequency. The coresponding cap is very small in the OPA380, because large caps are expensive on chip.

Ideally the gain setting resistors at the amplifier for the shunts would be a bit lower. The noise of the OPA189 corresponds to some 1.6 K Ohms. So the noise contribution from 1 K ohms would be still visible. Slightly lower resistance is also less sensitive to parasitive capacitance, which may be an issue at high speed.
The AD8065 is not 100 times faster than the OPA189 - so the amplication of the inner loop should be lower, so more like 90 times total and may be 20-30x for the inner loop. I am still not sure so much gain is really needed. It is more likely to have peak voltages at the shunt to the 100 mV range.

[Crossphased]

I see very little need for the extra buffer U24. The output from the sunt is well low enough in impedance. There is also little need to switch the ouput at the shunts - it should be OK to take all the shunt signals from the 10 Ohms shunt. A tap in between my be needed of there are very large shunts (like >10 K) because of noise and maybe effect of leakage.

Gotcha- yea it was added when I misunderstood the comment about about low impedance ground path for the composite amp. Going to remove that and the switch

I don't think the extra phase inverter for the TIA is a good idea. Inversion can be better done in software.

I'm curious, what could be bad about the phase inverter? Just wondering. Extra chance for oscillation? More phase delay?

C70 at the compound TIA can probably be larger, so that the cross over from the conventional OP to the AZ op is at a lower frequency. The corresponding cap is very small in the OPA380, because large caps are expensive on chip.

I see, so the cap governs the switchover frequency when AD8065 takes over from the AZ OP. I'd like to understand this part better. Could you say a bit more about what function C32 and R29 perform here? (image attached)

The noise of the OPA189 corresponds to some 1.6 K Ohms. So the noise contribution from 1 K ohms would be still visible. Slightly lower resistance is also less sensitive to parasitive capacitance, which may be an issue at high speed.

How does one calculate the noise from resistor? Also, does the large value of the 99k (now 75k) resistor add quite some noise here?

I understand now why the gain should be split up more. AD8065 has ~ 10x the gain bandwidth of OPA189, so AD8065 should be making around 10x the gain of OPA189. So gain of 3 and 30 satisfies those specs nicely. Will round down to 3 and 25, for little less gain

As always, thankyou very much for sharing your knowledge Kleinstein, I very much appreciate it. I've learned so much from you over the past couple years, much more than I ever did in the classroom! Thanks

[Kleinstein]

C32 , R29 are filtering the ouput of the AZ OP. The main purpose is to fitler out the fast switching transients of the AZ OP. However the fitler should not be to slow to add too much phase delay. So the filter frequency should not be too low in frequency unless extra measures are taken.

For calculating noise of the resistors the approximate (there is a temperature where this is exact) value is 1 nV/sqart(Hz) from a 60 Ohms resistor and than proportional to the square root of the resistor. Uncorrelated noise sources add squared. A convenient way (though not standard practice) is to convert the OPs noise to resistance of equivalent noise and than add the resistors and equivalent noise resistances. Adding the resistance values is equivalent to adding the squared noise sources. Gain stages act squared on the resistors.

In the FB divider the 1 K is relative to the input, while the 100 K total resistance would have noise relative to the output. So the more relevant noise is the noise from the 1 K resistor.  Actually it would be the 1 K and 100 K resistors in parallel to set the ouput impedance of the divider, but this does no change much. The point is making the divider lower impedance. With a maximum output of some 2 V something like 10 K total resistance should be enough, not to have too much load to the OP, heating of the resistors and ground current.

The extra phase inverter adds some noise. In addition the inverter also is effected by the switch resistance at the input. The OPA388 would also add dealy / phase shifts. The extra amplifier stage would not oscillate (it is not part of a feedback loop), but it adds noise and errors with essentially no benefit. Modern OPs are amazingly accurate, but they still can't beat a simple wire when it comes to noise, offset and linearity.
The digital part has to know which path the signal is coming from. So there should be no problem doing the inversion with the digital data. The control of the range could also be done from the ADC data - so there is little need for the extra comparators.

[Crossphased]

C32 , R29 are filtering the ouput of the AZ OP. The main purpose is to fitler out the fast switching transients of the AZ OP. However the fitler should not be to slow to add too much phase delay. So the filter frequency should not be too low in frequency unless extra measures are taken.

For calculating noise of the resistors the approximate (there is a temperature where this is exact) value is 1 nV/sqart(Hz) from a 60 Ohms resistor and than proportional to the square root of the resistor. Uncorrelated noise sources add squared. A convenient way (though not standard practice) is to convert the OPs noise to resistance of equivalent noise and than add the resistors and equivalent noise resistances. Adding the resistance values is equivalent to adding the squared noise sources. Gain stages act squared on the resistors.

In the FB divider the 1 K is relative to the input, while the 100 K total resistance would have noise relative to the output. So the more relevant noise is the noise from the 1 K resistor.  Actually it would be the 1 K and 100 K resistors in parallel to set the ouput impedance of the divider, but this does no change much. The point is making the divider lower impedance. With a maximum output of some 2 V something like 10 K total resistance should be enough, not to have too much load to the OP, heating of the resistors and ground current.

The extra phase inverter adds some noise. In addition the inverter also is effected by the switch resistance at the input. The OPA388 would also add dealy / phase shifts. The extra amplifier stage would not oscillate (it is not part of a feedback loop), but it adds noise and errors with essentially no benefit. Modern OPs are amazingly accurate, but they still can't beat a simple wire when it comes to noise, offset and linearity.
The digital part has to know which path the signal is coming from. So there should be no problem doing the inversion with the digital data. The control of the range could also be done from the ADC data - so there is little need for the extra comparators.

Thank you very much for that Kleinstein. Excellent response! Very informative. Yes I agree about not the need for extra comparators. I was going to try to do gain switching in hardware to make gain switching faster, but after some thinking I think ADC->MCU will be plenty fast enough.

I had a thought about the inverting phase amp section. I think it is required, or at least a buffer is required. If no OPA is there, then series resistance from second TIA gain switch, ADG1221, is in series with the differential amp, and will throw off the gain ratio. So it may be best to have at least a buffer on the output before the FDA. A do not populate resistor could be added to the layout to configure the OPA as a buffer or inverting phase. What are your thoughts? Maybe a faster OPA for this component? I see a couple others that are faster but have higher offset V are LT1028 or ADA4625

Also, I have a question about using OPA388 as buffer/phase invert. I was looking at specs of OPA388 vs OPA189. OPA189 has 14 Mhz bandwidth for -3db point, OPA388 has 10 Mhz for -3db point. Looking closer, OPA189 has slew rate of 20V/us, while OPA388 has slew rate of only 5V/us. A factor of 4 difference. I'm trying understand how there is a factor of 4 difference in speed, but only 1.4 factor in bandwidth. How to resolve those two?
Thanks very much

[Kleinstein]

The slew rate is set by 2 factors: one is the GBW and the other is the input voltge up to which more voltage still results an a faster slew rate. The second factor depends on the input stage : BJT based OPs often already saturate from some 50 mV on, while FET based OPs are linear up to a higher voltage (like 1 V). The low voltage OPs tend to faster saturate in the slew speed.

The advantage of the OPA388 is the slightly lower current noise and possibly less current spikes from switching. So it should be the better choice at the TIA. The slew rate should not really matter there, as this OP only compensates for the offset and LF noise of the fast OP. So even a very slow AZ OP would be OK - though usually higher noise.

You are right, the amplifier for the ADC input is relatively low impedance. The logical position of the extra buffer would thus be behind the extra switches to choose between the shunt path and the TIA path (and possibly the TIA part with a divider).

[Crossphased]

The slew rate is set by 2 factors: one is the GBW and the other is the input voltge up to which more voltage still results an a faster slew rate. The second factor depends on the input stage : BJT based OPs often already saturate from some 50 mV on, while FET based OPs are linear up to a higher voltage (like 1 V). The low voltage OPs tend to faster saturate in the slew speed.

The advantage of the OPA388 is the slightly lower current noise and possibly less current spikes from switching. So it should be the better choice at the TIA. The slew rate should not really matter there, as this OP only compensates for the offset and LF noise of the fast OP. So even a very slow AZ OP would be OK - though usually higher noise.

You are right, the amplifier for the ADC input is relatively low impedance. The logical position of the extra buffer would thus be behind the extra switches to choose between the shunt path and the TIA path (and possibly the TIA part with a divider).

Awesome thank you so much Kleinstein, ok will keep it as a buffer. Yes I think a divider is a good idea to put after the TIA as well. 

Here's a question about the ADC: it has +-2.5V inputs. To clamp the voltage within this range I have the supplies to the FDA as +-2.5V. Do you think this is adequate? Or should protection diodes be added in the filter area of ADC inputs?

Also, do you think it would be wise to monitor the back to back input protection diodes at the very front of the current measure circuit? I mean monitor the diodes for current flow, in case of some kind of overcurrent event, or if a shunt goes open circuit for some reason.

Cheers and thank you always for your help and advice

[Kleinstein]

For the ADC the limited supply to the driving amplifier / buffer is enough protection. The problem is more how to protect the buffer/LTC6363 from a possibly high voltage from the TIA. The shunt part could work with a limited supply too, so no real problem there.
 
The critical path would be the TIA ouput without a divider. A simple solution could be some series resistor (or 2 JFETs as a current limit) and than clamping. To some +-2.5 to 3 V. It may need 2 switches in sereis, so that the clamping part is only active if the channel is actually used.
The LTC6363 should be OK (non damaging) with the input voltage slightly exceeding the supply.


In the circuit shown in the PDF there is a OPA388 supplied with +-5 V : this is too much, the OPA388 is kind of the low voltage brother to the OPA189, so some 5 V max. for the supply. 

[Crossphased]

For the ADC the limited supply to the driving amplifier / buffer is enough protection. The problem is more how to protect the buffer/LTC6363 from a possibly high voltage from the TIA. The shunt part could work with a limited supply too, so no real problem there.
 
The critical path would be the TIA ouput without a divider. A simple solution could be some series resistor (or 2 JFETs as a current limit) and than clamping. To some +-2.5 to 3 V. It may need 2 switches in sereis, so that the clamping part is only active if the channel is actually used.
The LTC6363 should be OK (non damaging) with the input voltage slightly exceeding the supply.


In the circuit shown in the PDF there is a OPA388 supplied with +-5 V : this is too much, the OPA388 is kind of the low voltage brother to the OPA189, so some 5 V max. for the supply.

Thanks very much for that Kleinstein. Very good advice as always.

After giving it some thought, divider was added to extend range of the TIA, and protect LTC6363 from TIA output. Division ratios of 1/1, 1/2, 1/4, and grounded input were added. The grounded input is to measure the offset and calibrate out the next stage buffer amp. It was changed to a faster part, ADA4625. It has slightly higher typical offset V, (15uV typical), and still has low noise and reasonably low tempco. Do not populate resistors were kept to change configuration between buffer, and phase invert.

For the shunt section, in lieu of lowering shunt amplifier input voltage, it was opted to add protection diodes to each rail. As you rightly suggested, the slew rate partly depends on input voltage amplitude, lowering input voltage may slow the response. Perhaps may even raise the voltage on the second OPA in the composite amp section.

I think that about wraps up the current sense section, next up is voltage sense section  and power isolation. Latest schem is below:

[Kleinstein]

Usually the slew rate limit of an OP does not depend much on the actual supply voltage. It is more like parts designed for a higher supply often also allow a higher slew rate. This is because a higher output voltage also needs a higher slew rate.

The problem with the switches before the amplifier also applies to the shunt path. So ideally the buffer would be right before the LTC6363.
With a reasonably high resoltion ADC there is no real need for fine steps at the divider. 1:1 and 1:4 (or whatever is the maximum voltage) should be sufficient.
The buffer should be a non inverting buffer - the phase inverter has the same problem with input resistance as the LTC6363.

[Crossphased]

Usually the slew rate limit of an OP does not depend much on the actual supply voltage. It is more like parts designed for a higher supply often also allow a higher slew rate. This is because a higher output voltage also needs a higher slew rate.

Interesting. Intuitively, it made sense that output voltage could slew faster with higher difference between supply and output. Are you saying that for most OPAs, higher input voltage capable part will also have higher slew rate (in general)? Wondering what the defining characteristic is that gives OPA higher slew rate, or alternatively, GBW. Say for instance the shunt composite amp, are you saying AD8065 will have similar slew rates, for both +-2.5V & +-12V supply ? (for output voltage contained within the rails).

The problem with the switches before the amplifier also applies to the shunt path. So ideally the buffer would be right before the LTC6363.
With a reasonably high resoltion ADC there is no real need for fine steps at the divider. 1:1 and 1:4 (or whatever is the maximum voltage) should be sufficient.
The buffer should be a non inverting buffer - the phase inverter has the same problem with input resistance as the LTC6363.

Yes noticed the issue in the shunt path, that was the reason ADG1421 was selected, only 2 Ohms Rds on. Leakage should matter less there, as it is directly after buffers. What you're saying makes sense though, the best place for buffer is directly before LTC6363.

Good point on the buffer vs phase inverter. I hadn't considered switch resistance problem on input to phase inverter. Thats a good point to remember about inverting amp input impedance.

As always, thanks for the good advice and critiques

[Kleinstein]

A main factor for the slew rate is the GBW. The other part is the input stage and on with how much input difference it is still increasing the rate of voltage change. A simple BJT based input is linear for some 40 mV or so and saturates when higher. With extra resistors for input degeneration the range can be extended, but at the cost of higher noise.  So the very low noise BJT based OPs should have a relatively fixed ratio of slew rate to GBW with a rather low slew rate.

FET inputs usually have a larger linear range and thus a higher slew rate for the same GBW. How much depends on the design details. For low voltage parts the slew rate is a less important design parameter. So lower priority to a slew rate and often not that mich slew rate. With higher supply the slew rate gets more important as a design target. So these OPs may have a higher slew rate at the same GBW. The effect of the design supply voltage is more like a market thing, AFAIK not a principle effect - so it is only a general trend, with possible exceptions.

The slew rate is usually a thing of the current the input stage can deliver and the compensation cap. So it does not change much with the ouput voltage. So the slew rate should be valid nearly all the way to the ouput limits.  For RR OPs the slew rate may change with the common mode voltage, especially near one end. This is because there are usually 2 input stages and a cross over beteween the 2, usually some 1-2 V from one rail. The two stages often have the same GBW, but not necessary the same slew rate.
To get a good PSRR the input stage current usually does not change much with the actual supply. So yes the sew rate would be essentially the same with a 5 V or 24 V supply. It is just less likely to find a high slew rate in a 5 V specified part, than for a part designed for 30 V.
As an example the CMOS MCP6021 and OPA192 have both 10 MHz GBW, but 7 V/µs for the 5 V part and 20 V/µs for the 30 V OPA192. The OP192 would still keep the speed at 5 V supply. The BJT based OP27 is lightly slower at 8 MHz but still has only 2.8V/µs  (because it is a low noise BJT baed part). There are higher SR (at comparable GBW) BJT based parts (e.g. TLE2141), but this comes at higher noise.

[David Hess]

Slew rate is limited by the input stage current charging the compensation capacitance.  Increasing the input stage current without limiting transconductance requires a larger compensation capacitance for stability so slew rate does not increase.  So the way to increase slew rate is to reduce input stage transconductance to allow for higher input stage current without increasing the compensation capacitance.

JFETs start out with lower transconductance than bipolar transistors so for the same compensation capacitance, they can operate with a higher input stage current producing a higher slew rate.

Emitter degeneration is not the only way to reduce transconductance so there are low noise high slew rate bipolar amplifiers.  Transconductance reduction is also used for other purposes.  324 style amplifiers use it to reduce the size of the compensation capacitor from about 30 picofarads to 5 picofarads, which saves considerable die space making them less expensive to produce.  Later 741 style operational amplifiers did the same thing to reduce cost which also allowed dual parts to be made.

National application note A has an excellent analysis of the issues.

[Crossphased]

Thanks for that David, interesting. So does higher slew rate generally imply higher bias current then as well?

That is a really good article

[Crossphased]

Here's another sort of unrelated question-

Started work on the Voltage attenuation and sampling section. Working on the OVP. A thought came to mind regarding using protection diodes: sometimes it is assumed the rail is a good reference point to sink overvoltage. But that depends on the sinking capability for the LDO on that rail. So... when using protection diodes, do you typically place series resistance ahead of the diodes, to limit current the LDO must handle in case of overvoltage event?

[Kleinstein]

The slew rate does not directly correlate with the bias current. It is more like a little more supply current needed. The bias current tends to go up with lower noise devices, though FET inputs can get low noise also with a low bias.
With BJT based OPs, lower noise often comes with more bias, though there can be some compensation on the current (but not on the current noise that comes with the bias).

For the protection it usually needs some way to limit the input current and only than clamp the voltage seen by the amplifier to a safe values.
The current limit can bea simple resistor (or a chain for higher peak voltage), but also a PTC and a combination of FETs (e.g. 2 depletion MOSFETs back to back with a resistor in between). A combination is also possible and maybe needed. For the longer time a relay may reduce the current even more.
The supply can sink some current - usually up to the minimal supply current needed for the circuit. LDO usually can not sink much current. It is more like some need a minimal current to be stable.  The limit at the supply may be a bit high anyway, and one may want a slightly lower limit / auxiliary voltage with something like zeners. The clamping to the supply is more like a secondary path in case the power is off.

[David Hess]

Thanks for that David, interesting. So does higher slew rate generally imply higher bias current then as well?

In practice it does not because before the input stage current is raised to increase the slew rate, the compensation capacitance will be decreased instead producing the same result.  Eventually however the compensation capacitance cannot be decreased further and the input stage current will have to be increased resulting in greater input bias current.

Note that it may not be possible to decrease the input stage current for the reasons given in that National Semiconductor application note.  Doing so will move the input stage poles to lower frequencies compromising performance.  The input stage tail current and compensation capacitance are not the only things which ultimately limit AC performance.

[Crossphased]

Put together some preliminary part of the AFE for the Voltage sense. Small choke/resistor/cap to help attenuate transients. For current limit protection , using the depletion fets. These ones, CPC3982TTR, seem to be the best ones available. Tolerates up to 800 V, and also only 380 Rds on. On the other hand the LND150 only tolerates up to 500V, and has 1k Rds_on. Most of the other depletion fets only go up to 600V.

+5V to +50V expected at the input. With 1k series R in between the depletion fets, this should limit current to 1 or 2 mA. Then, divide by 20 (compensated @ 1 Mc), followed by diff Amp PGA. LTC6373 has very low bias current, 2pA typical, 25 pA max over temperature. With 300k series resistance on input this yields error of .6uV typical, 7.5uV max.  The PGA has gains of .25, .5, 1,2,4,8, so can do further attenuation or some gains too. With 300k resistance + depletion fets I think the PGA is well protected, and internal protection diodes should be able to handle a few mA in overvoltage event.

Next step is anti alias filter before the ADC. What target freq for the filter do you shoot for? Certainly you want something above the target BW, so you're not attenuating the signal. What harmonic do you shoot for in the pass band for the filter? Pass the second or third harmonic? For The ADC, it samples up to 2 Msps, so Nyquist freq is 1 Mhz. It would be nice to get 1 Mhz bandwidth out of this, but 500 khz would be ok

[Kleinstein]

The capacitance for compensation is rather small. Compared to the parasitics 0.5 pF is rather small.  Is a trim of the gain actually needed ? Just for trimming the compensation it is usually easier to trim the capacitance at the low side.  The amplifier usually also has some input capacitance, and this may be nonlinear.

The Nyquist limit is the theoretical absolute maximum - so a practical AA fitler has to be quite a bit lower. Getting 1 MHz BW is essentially impossible 500 kHz would already be hard. The AA fitler sets the BW and usually one starts with the required BW for the task and than decides on the sampling rate and ADC. The required BW and accuracy depends on the application. It is more than a certain harmonic to include. There is also more than a hard limit all good below the BW limit and all bad above. The transition is gradually, often with phase errors coming up well below the amplitude changes.

A point that effects the filter calculation is the amplitude of out of band signals. It makes a difference if the out of band signal is small anyway (e.g. a sensor with limited BW) or if there is possibly large interference (E.g. radio signal). One may have to accept that a large out of band signal will still get trough at a level higher than the noise limit.

[Crossphased]

The Nyquist limit is the theoretical absolute maximum - so a practical AA fitler has to be quite a bit lower. Getting 1 MHz BW is essentially impossible 500 kHz would already be hard. The AA fitler sets the BW and usually one starts with the required BW for the task and than decides on the sampling rate and ADC. The required BW and accuracy depends on the application. It is more than a certain harmonic to include. There is also more than a hard limit all good below the BW limit and all bad above. The transition is gradually, often with phase errors coming up well below the amplitude changes.

A point that effects the filter calculation is the amplitude of out of band signals. It makes a difference if the out of band signal is small anyway (e.g. a sensor with limited BW) or if there is possibly large interference (E.g. radio signal). One may have to accept that a large out of band signal will still get trough at a level higher than the noise limit.

Thankyou for that Kleinstein. Ok, so you're saying the AA should be set lower than Nyquist limit? ie less than half the sample rate? I mean, then some of the in band signal could be attenuated. What freq do you shoot for as -3 db point?

Another question I have is regarding the practicality of paralleling of ADCs. Two scenarios:
1. Two ADCs, one is SAR to capture high freq content, say 1-10Msps, 14-16 bit resolution. Second ADC is 24 bit, delta sigma, 30 ksps, to capture high resolution at low frequency. Is it possible to parallel these two, without degrading the signal of interest? Do they need to be attached to separate buffers to avoid sample and hold noise from interfering with each other, or maybe just single high speed buffer to drive the ADC inputs?

2. Two ADCs, both delta sigma, same speed and resolution. Put in parallel to decrease noise and jncrease resolution. Basically correlated double sampling. What measures need to be taken to actually decrease noise in this scenario. Do the sample periods need to be synced so they are non overlapping?

[Kleinstein]

For the AA filter one usually wants quite some attenuation at the Nyquist frequency. This is often the starting point. Some want an attenuation of the full dynamic range there - though I thing this is a bit too strict a requitement in most cases. So still some -40 dB at the Nyquist frequency may be a reasonable target. Depending one the type of AA filter this may mean a rather low -3 dB point (e.g. a factor 10 below the Nyquist limit with simple 2nd order fitler), or the other way around it needs a rather steep filter (e.g. 7 th order elliptic) to get the -3 dB point relatively close to the Nyquits limit, like a factor of 2 or 1.5. Things are a bit the other way around as with DDS frequency generators with the DACs there.
Because of the complications with the AA filter, it is often good to have a rather high sampling rate and than use some digital filtering AA to reduce the data rate a bit.

How much different ADCs influence each other really depends on the ADCs. Some have internal buffers and may get away without seprate buffers, but for the highest performance separate buffers are definitely a good idea. The buffers already with one ADC have trouble to provide the ideally low source impedance wanted by most low noise ADCs.

Because of the AA filtering problem the sampling rate of a SAR and SD ADC are not directly comparable. The SD ADC can often get away with a lower sampling rate, as less of the BW is lost to the AA filter. One still has to look at the type of filter in the SD ADC - the BW may be lower the fs/2.

A high speed 16 bit ADC may still be good also for the low frequency part and the higher sampling rate also adds to the dynamic. So the slower 24 bit SD ADC  may not give much lower noise. Especially with the SD ADCs the nominal resolution is quite a bit higher than the effective resolution. This especially true for the higherst BW they support. The resolution is usually given for the lowest BW they support, or just as the digital side data format.

[Crossphased]

Got some more work done on this over the weekend. Put together two AA filters, which one is used will depend on which ADC is used for Vsense. The AD4003 (2Msps) looks good, but a couple others that are interesting are ADS1675 (4 Msps) and AD7960 (5 Msps). The two filters thus are targeted for cutoff @ 1Mhz and 2 Mhz. Performance of two filters:

Filt1:
300 khz = -3 db
1 Mhz = -35 db

Filt2:
800 khz = -3db
2 Mhz = -36 db

Schematic for the two filters is attached. Also, picture is attached of the filter performance.

Is there a name for this type of filter, where capacitor is coupled to the opposite output phase of the FDA?

[Kleinstein]

The FETs at the input may not work very well together with the relatively low impedance divider at the input. The protextion adds some resistance and this can effect the gain stability. The transistor R_on is highly temperature dependent (some 6000 ppm/K).
With already a resistor for the divider, one may get away with just the upper resistor in the divider for protection (still needs a suitable type - so not a single 0603).
A fast, high Z input is allways a challange.

The filter behind the drivers looks like is may work, but could have quite some output impedance. Parasitics could also cause some trouble, especially with the inductors. There is coupling and parasitic capacitance / self resonance. I would like to have at least some filtering already before the first amplifier. 

[Crossphased]

The FETs at the input may not work very well together with the relatively low impedance divider at the input. The protextion adds some resistance and this can effect the gain stability. The transistor R_on is highly temperature dependent (some 6000 ppm/K).
With already a resistor for the divider, one may get away with just the upper resistor in the divider for protection (still needs a suitable type - so not a single 0603).
A fast, high Z input is allways a challange.

The filter behind the drivers looks like is may work, but could have quite some output impedance. Parasitics could also cause some trouble, especially with the inductors. There is coupling and parasitic capacitance / self resonance. I would like to have at least some filtering already before the first amplifier.

Thanks very much for that Kleinstein. I understood your message about level of attenuation for f_nyquest/2. Signals higher than f_nyquest/2 get folded back and add noise to signal of interest.  Effort was made to add as much attenuation as possible while still keeping reasonable passband.

Regarding the filter having quite some output impedance, would you recommend placing the inductor networks in between the the PGA and LTC6363? Or adding another buffer after the filter networks?

I thought about self resonance from the inductors, but expected the 100R resistors would dampen it some. Maybe its a good idea to add pads for series resistors at the chokes. 5R resistors could be placed, or if not necessary, 0R. For the 3.3 uH chokes, actual spice model was downloaded from Wurth, which included parasitic capacitance in the model. Simulation didnt show any issues. I think SRF of the chokes was some 45-50 Mhz.

I have some of those CPC3982 depletion fets on hand, going to do some testing and see what the performance looks like. I see your point about tempco of the fets potentially causing gain stability issues. If the fets are removed, would you suggest adding low leakage protection diodes? Perhaps  bootstrapped.

[Kleinstein]

Without the FETs at the input, one would need protection diodes at the amplifier input. The low end of the divider is relatively low impedance. So one may get away with simple low capacitance diodes. I don't think there is much need to worry about leakage, it is more about the capacitance that can be depend on the voltage. A constant capacitance would not be a big deal, as there is already quite some capacitance, it is the variable part that can cause trouble.

The self resonane would likely not cause a real problem. Just include the capacitance in the simulation, as it can have a slighte effect on the filter passband.
One may even add a capacitor to one pair of coils to make it an additional zero, like in an eliptical filter. So it is more about less resistors, not more.
I don't think one would need an extra buffer stage. An LC filter can be designed in different ways and one has some freedom there to also choose an ouput impedance lower than the input impedance.  It also depends on the ADC in mind. The ADC usually have some suggestions for the input, possibly also with some filtering to get an idea on the preferred capacitance / resistance range. Some also want capacitance to ground.