feedback/shunt ammeter design

[Kleinstein]

For the ADC the limited supply to the driving amplifier / buffer is enough protection. The problem is more how to protect the buffer/LTC6363 from a possibly high voltage from the TIA. The shunt part could work with a limited supply too, so no real problem there.
 
The critical path would be the TIA ouput without a divider. A simple solution could be some series resistor (or 2 JFETs as a current limit) and than clamping. To some +-2.5 to 3 V. It may need 2 switches in sereis, so that the clamping part is only active if the channel is actually used.
The LTC6363 should be OK (non damaging) with the input voltage slightly exceeding the supply.


In the circuit shown in the PDF there is a OPA388 supplied with +-5 V : this is too much, the OPA388 is kind of the low voltage brother to the OPA189, so some 5 V max. for the supply. 

[Crossphased]

For the ADC the limited supply to the driving amplifier / buffer is enough protection. The problem is more how to protect the buffer/LTC6363 from a possibly high voltage from the TIA. The shunt part could work with a limited supply too, so no real problem there.
 
The critical path would be the TIA ouput without a divider. A simple solution could be some series resistor (or 2 JFETs as a current limit) and than clamping. To some +-2.5 to 3 V. It may need 2 switches in sereis, so that the clamping part is only active if the channel is actually used.
The LTC6363 should be OK (non damaging) with the input voltage slightly exceeding the supply.


In the circuit shown in the PDF there is a OPA388 supplied with +-5 V : this is too much, the OPA388 is kind of the low voltage brother to the OPA189, so some 5 V max. for the supply.

Thanks very much for that Kleinstein. Very good advice as always.

After giving it some thought, divider was added to extend range of the TIA, and protect LTC6363 from TIA output. Division ratios of 1/1, 1/2, 1/4, and grounded input were added. The grounded input is to measure the offset and calibrate out the next stage buffer amp. It was changed to a faster part, ADA4625. It has slightly higher typical offset V, (15uV typical), and still has low noise and reasonably low tempco. Do not populate resistors were kept to change configuration between buffer, and phase invert.

For the shunt section, in lieu of lowering shunt amplifier input voltage, it was opted to add protection diodes to each rail. As you rightly suggested, the slew rate partly depends on input voltage amplitude, lowering input voltage may slow the response. Perhaps may even raise the voltage on the second OPA in the composite amp section.

I think that about wraps up the current sense section, next up is voltage sense section  and power isolation. Latest schem is below:

[Kleinstein]

Usually the slew rate limit of an OP does not depend much on the actual supply voltage. It is more like parts designed for a higher supply often also allow a higher slew rate. This is because a higher output voltage also needs a higher slew rate.

The problem with the switches before the amplifier also applies to the shunt path. So ideally the buffer would be right before the LTC6363.
With a reasonably high resoltion ADC there is no real need for fine steps at the divider. 1:1 and 1:4 (or whatever is the maximum voltage) should be sufficient.
The buffer should be a non inverting buffer - the phase inverter has the same problem with input resistance as the LTC6363.

[Crossphased]

Usually the slew rate limit of an OP does not depend much on the actual supply voltage. It is more like parts designed for a higher supply often also allow a higher slew rate. This is because a higher output voltage also needs a higher slew rate.

Interesting. Intuitively, it made sense that output voltage could slew faster with higher difference between supply and output. Are you saying that for most OPAs, higher input voltage capable part will also have higher slew rate (in general)? Wondering what the defining characteristic is that gives OPA higher slew rate, or alternatively, GBW. Say for instance the shunt composite amp, are you saying AD8065 will have similar slew rates, for both +-2.5V & +-12V supply ? (for output voltage contained within the rails).

The problem with the switches before the amplifier also applies to the shunt path. So ideally the buffer would be right before the LTC6363.
With a reasonably high resoltion ADC there is no real need for fine steps at the divider. 1:1 and 1:4 (or whatever is the maximum voltage) should be sufficient.
The buffer should be a non inverting buffer - the phase inverter has the same problem with input resistance as the LTC6363.

Yes noticed the issue in the shunt path, that was the reason ADG1421 was selected, only 2 Ohms Rds on. Leakage should matter less there, as it is directly after buffers. What you're saying makes sense though, the best place for buffer is directly before LTC6363.

Good point on the buffer vs phase inverter. I hadn't considered switch resistance problem on input to phase inverter. Thats a good point to remember about inverting amp input impedance.

As always, thanks for the good advice and critiques

[Kleinstein]

A main factor for the slew rate is the GBW. The other part is the input stage and on with how much input difference it is still increasing the rate of voltage change. A simple BJT based input is linear for some 40 mV or so and saturates when higher. With extra resistors for input degeneration the range can be extended, but at the cost of higher noise.  So the very low noise BJT based OPs should have a relatively fixed ratio of slew rate to GBW with a rather low slew rate.

FET inputs usually have a larger linear range and thus a higher slew rate for the same GBW. How much depends on the design details. For low voltage parts the slew rate is a less important design parameter. So lower priority to a slew rate and often not that mich slew rate. With higher supply the slew rate gets more important as a design target. So these OPs may have a higher slew rate at the same GBW. The effect of the design supply voltage is more like a market thing, AFAIK not a principle effect - so it is only a general trend, with possible exceptions.

The slew rate is usually a thing of the current the input stage can deliver and the compensation cap. So it does not change much with the ouput voltage. So the slew rate should be valid nearly all the way to the ouput limits.  For RR OPs the slew rate may change with the common mode voltage, especially near one end. This is because there are usually 2 input stages and a cross over beteween the 2, usually some 1-2 V from one rail. The two stages often have the same GBW, but not necessary the same slew rate.
To get a good PSRR the input stage current usually does not change much with the actual supply. So yes the sew rate would be essentially the same with a 5 V or 24 V supply. It is just less likely to find a high slew rate in a 5 V specified part, than for a part designed for 30 V.
As an example the CMOS MCP6021 and OPA192 have both 10 MHz GBW, but 7 V/µs for the 5 V part and 20 V/µs for the 30 V OPA192. The OP192 would still keep the speed at 5 V supply. The BJT based OP27 is lightly slower at 8 MHz but still has only 2.8V/µs  (because it is a low noise BJT baed part). There are higher SR (at comparable GBW) BJT based parts (e.g. TLE2141), but this comes at higher noise.

[David Hess]

Slew rate is limited by the input stage current charging the compensation capacitance.  Increasing the input stage current without limiting transconductance requires a larger compensation capacitance for stability so slew rate does not increase.  So the way to increase slew rate is to reduce input stage transconductance to allow for higher input stage current without increasing the compensation capacitance.

JFETs start out with lower transconductance than bipolar transistors so for the same compensation capacitance, they can operate with a higher input stage current producing a higher slew rate.

Emitter degeneration is not the only way to reduce transconductance so there are low noise high slew rate bipolar amplifiers.  Transconductance reduction is also used for other purposes.  324 style amplifiers use it to reduce the size of the compensation capacitor from about 30 picofarads to 5 picofarads, which saves considerable die space making them less expensive to produce.  Later 741 style operational amplifiers did the same thing to reduce cost which also allowed dual parts to be made.

National application note A has an excellent analysis of the issues.

[Crossphased]

Thanks for that David, interesting. So does higher slew rate generally imply higher bias current then as well?

That is a really good article

[Crossphased]

Here's another sort of unrelated question-

Started work on the Voltage attenuation and sampling section. Working on the OVP. A thought came to mind regarding using protection diodes: sometimes it is assumed the rail is a good reference point to sink overvoltage. But that depends on the sinking capability for the LDO on that rail. So... when using protection diodes, do you typically place series resistance ahead of the diodes, to limit current the LDO must handle in case of overvoltage event?

[Kleinstein]

The slew rate does not directly correlate with the bias current. It is more like a little more supply current needed. The bias current tends to go up with lower noise devices, though FET inputs can get low noise also with a low bias.
With BJT based OPs, lower noise often comes with more bias, though there can be some compensation on the current (but not on the current noise that comes with the bias).

For the protection it usually needs some way to limit the input current and only than clamp the voltage seen by the amplifier to a safe values.
The current limit can bea simple resistor (or a chain for higher peak voltage), but also a PTC and a combination of FETs (e.g. 2 depletion MOSFETs back to back with a resistor in between). A combination is also possible and maybe needed. For the longer time a relay may reduce the current even more.
The supply can sink some current - usually up to the minimal supply current needed for the circuit. LDO usually can not sink much current. It is more like some need a minimal current to be stable.  The limit at the supply may be a bit high anyway, and one may want a slightly lower limit / auxiliary voltage with something like zeners. The clamping to the supply is more like a secondary path in case the power is off.

[David Hess]

Thanks for that David, interesting. So does higher slew rate generally imply higher bias current then as well?

In practice it does not because before the input stage current is raised to increase the slew rate, the compensation capacitance will be decreased instead producing the same result.  Eventually however the compensation capacitance cannot be decreased further and the input stage current will have to be increased resulting in greater input bias current.

Note that it may not be possible to decrease the input stage current for the reasons given in that National Semiconductor application note.  Doing so will move the input stage poles to lower frequencies compromising performance.  The input stage tail current and compensation capacitance are not the only things which ultimately limit AC performance.

[Crossphased]

Put together some preliminary part of the AFE for the Voltage sense. Small choke/resistor/cap to help attenuate transients. For current limit protection , using the depletion fets. These ones, CPC3982TTR, seem to be the best ones available. Tolerates up to 800 V, and also only 380 Rds on. On the other hand the LND150 only tolerates up to 500V, and has 1k Rds_on. Most of the other depletion fets only go up to 600V.

+5V to +50V expected at the input. With 1k series R in between the depletion fets, this should limit current to 1 or 2 mA. Then, divide by 20 (compensated @ 1 Mc), followed by diff Amp PGA. LTC6373 has very low bias current, 2pA typical, 25 pA max over temperature. With 300k series resistance on input this yields error of .6uV typical, 7.5uV max.  The PGA has gains of .25, .5, 1,2,4,8, so can do further attenuation or some gains too. With 300k resistance + depletion fets I think the PGA is well protected, and internal protection diodes should be able to handle a few mA in overvoltage event.

Next step is anti alias filter before the ADC. What target freq for the filter do you shoot for? Certainly you want something above the target BW, so you're not attenuating the signal. What harmonic do you shoot for in the pass band for the filter? Pass the second or third harmonic? For The ADC, it samples up to 2 Msps, so Nyquist freq is 1 Mhz. It would be nice to get 1 Mhz bandwidth out of this, but 500 khz would be ok

[Kleinstein]

The capacitance for compensation is rather small. Compared to the parasitics 0.5 pF is rather small.  Is a trim of the gain actually needed ? Just for trimming the compensation it is usually easier to trim the capacitance at the low side.  The amplifier usually also has some input capacitance, and this may be nonlinear.

The Nyquist limit is the theoretical absolute maximum - so a practical AA fitler has to be quite a bit lower. Getting 1 MHz BW is essentially impossible 500 kHz would already be hard. The AA fitler sets the BW and usually one starts with the required BW for the task and than decides on the sampling rate and ADC. The required BW and accuracy depends on the application. It is more than a certain harmonic to include. There is also more than a hard limit all good below the BW limit and all bad above. The transition is gradually, often with phase errors coming up well below the amplitude changes.

A point that effects the filter calculation is the amplitude of out of band signals. It makes a difference if the out of band signal is small anyway (e.g. a sensor with limited BW) or if there is possibly large interference (E.g. radio signal). One may have to accept that a large out of band signal will still get trough at a level higher than the noise limit.

[Crossphased]

The Nyquist limit is the theoretical absolute maximum - so a practical AA fitler has to be quite a bit lower. Getting 1 MHz BW is essentially impossible 500 kHz would already be hard. The AA fitler sets the BW and usually one starts with the required BW for the task and than decides on the sampling rate and ADC. The required BW and accuracy depends on the application. It is more than a certain harmonic to include. There is also more than a hard limit all good below the BW limit and all bad above. The transition is gradually, often with phase errors coming up well below the amplitude changes.

A point that effects the filter calculation is the amplitude of out of band signals. It makes a difference if the out of band signal is small anyway (e.g. a sensor with limited BW) or if there is possibly large interference (E.g. radio signal). One may have to accept that a large out of band signal will still get trough at a level higher than the noise limit.

Thankyou for that Kleinstein. Ok, so you're saying the AA should be set lower than Nyquist limit? ie less than half the sample rate? I mean, then some of the in band signal could be attenuated. What freq do you shoot for as -3 db point?

Another question I have is regarding the practicality of paralleling of ADCs. Two scenarios:
1. Two ADCs, one is SAR to capture high freq content, say 1-10Msps, 14-16 bit resolution. Second ADC is 24 bit, delta sigma, 30 ksps, to capture high resolution at low frequency. Is it possible to parallel these two, without degrading the signal of interest? Do they need to be attached to separate buffers to avoid sample and hold noise from interfering with each other, or maybe just single high speed buffer to drive the ADC inputs?

2. Two ADCs, both delta sigma, same speed and resolution. Put in parallel to decrease noise and jncrease resolution. Basically correlated double sampling. What measures need to be taken to actually decrease noise in this scenario. Do the sample periods need to be synced so they are non overlapping?

[Kleinstein]

For the AA filter one usually wants quite some attenuation at the Nyquist frequency. This is often the starting point. Some want an attenuation of the full dynamic range there - though I thing this is a bit too strict a requitement in most cases. So still some -40 dB at the Nyquist frequency may be a reasonable target. Depending one the type of AA filter this may mean a rather low -3 dB point (e.g. a factor 10 below the Nyquist limit with simple 2nd order fitler), or the other way around it needs a rather steep filter (e.g. 7 th order elliptic) to get the -3 dB point relatively close to the Nyquits limit, like a factor of 2 or 1.5. Things are a bit the other way around as with DDS frequency generators with the DACs there.
Because of the complications with the AA filter, it is often good to have a rather high sampling rate and than use some digital filtering AA to reduce the data rate a bit.

How much different ADCs influence each other really depends on the ADCs. Some have internal buffers and may get away without seprate buffers, but for the highest performance separate buffers are definitely a good idea. The buffers already with one ADC have trouble to provide the ideally low source impedance wanted by most low noise ADCs.

Because of the AA filtering problem the sampling rate of a SAR and SD ADC are not directly comparable. The SD ADC can often get away with a lower sampling rate, as less of the BW is lost to the AA filter. One still has to look at the type of filter in the SD ADC - the BW may be lower the fs/2.

A high speed 16 bit ADC may still be good also for the low frequency part and the higher sampling rate also adds to the dynamic. So the slower 24 bit SD ADC  may not give much lower noise. Especially with the SD ADCs the nominal resolution is quite a bit higher than the effective resolution. This especially true for the higherst BW they support. The resolution is usually given for the lowest BW they support, or just as the digital side data format.

[Crossphased]

Got some more work done on this over the weekend. Put together two AA filters, which one is used will depend on which ADC is used for Vsense. The AD4003 (2Msps) looks good, but a couple others that are interesting are ADS1675 (4 Msps) and AD7960 (5 Msps). The two filters thus are targeted for cutoff @ 1Mhz and 2 Mhz. Performance of two filters:

Filt1:
300 khz = -3 db
1 Mhz = -35 db

Filt2:
800 khz = -3db
2 Mhz = -36 db

Schematic for the two filters is attached. Also, picture is attached of the filter performance.

Is there a name for this type of filter, where capacitor is coupled to the opposite output phase of the FDA?

[Kleinstein]

The FETs at the input may not work very well together with the relatively low impedance divider at the input. The protextion adds some resistance and this can effect the gain stability. The transistor R_on is highly temperature dependent (some 6000 ppm/K).
With already a resistor for the divider, one may get away with just the upper resistor in the divider for protection (still needs a suitable type - so not a single 0603).
A fast, high Z input is allways a challange.

The filter behind the drivers looks like is may work, but could have quite some output impedance. Parasitics could also cause some trouble, especially with the inductors. There is coupling and parasitic capacitance / self resonance. I would like to have at least some filtering already before the first amplifier. 

[Crossphased]

The FETs at the input may not work very well together with the relatively low impedance divider at the input. The protextion adds some resistance and this can effect the gain stability. The transistor R_on is highly temperature dependent (some 6000 ppm/K).
With already a resistor for the divider, one may get away with just the upper resistor in the divider for protection (still needs a suitable type - so not a single 0603).
A fast, high Z input is allways a challange.

The filter behind the drivers looks like is may work, but could have quite some output impedance. Parasitics could also cause some trouble, especially with the inductors. There is coupling and parasitic capacitance / self resonance. I would like to have at least some filtering already before the first amplifier.

Thanks very much for that Kleinstein. I understood your message about level of attenuation for f_nyquest/2. Signals higher than f_nyquest/2 get folded back and add noise to signal of interest.  Effort was made to add as much attenuation as possible while still keeping reasonable passband.

Regarding the filter having quite some output impedance, would you recommend placing the inductor networks in between the the PGA and LTC6363? Or adding another buffer after the filter networks?

I thought about self resonance from the inductors, but expected the 100R resistors would dampen it some. Maybe its a good idea to add pads for series resistors at the chokes. 5R resistors could be placed, or if not necessary, 0R. For the 3.3 uH chokes, actual spice model was downloaded from Wurth, which included parasitic capacitance in the model. Simulation didnt show any issues. I think SRF of the chokes was some 45-50 Mhz.

I have some of those CPC3982 depletion fets on hand, going to do some testing and see what the performance looks like. I see your point about tempco of the fets potentially causing gain stability issues. If the fets are removed, would you suggest adding low leakage protection diodes? Perhaps  bootstrapped.

[Kleinstein]

Without the FETs at the input, one would need protection diodes at the amplifier input. The low end of the divider is relatively low impedance. So one may get away with simple low capacitance diodes. I don't think there is much need to worry about leakage, it is more about the capacitance that can be depend on the voltage. A constant capacitance would not be a big deal, as there is already quite some capacitance, it is the variable part that can cause trouble.

The self resonane would likely not cause a real problem. Just include the capacitance in the simulation, as it can have a slighte effect on the filter passband.
One may even add a capacitor to one pair of coils to make it an additional zero, like in an eliptical filter. So it is more about less resistors, not more.
I don't think one would need an extra buffer stage. An LC filter can be designed in different ways and one has some freedom there to also choose an ouput impedance lower than the input impedance.  It also depends on the ADC in mind. The ADC usually have some suggestions for the input, possibly also with some filtering to get an idea on the preferred capacitance / resistance range. Some also want capacitance to ground.