Homebrew GSPDO Questions

[Wallace Gasiewicz]

I kinda built this:

Only used a Navman Jupiter 12 and a Isotemp 118 12   OCXO (temp controlled frequency)
I had this stuff laying around.
I used an old Sony brick PS also (more junk)

It appears to work, the 10 KHz square waves from the Navman and the divided down 10 KHz from the OCXO line up.
It produces a lot of usable harmonics up to maybe 500 MHz also.

The square waves viewed on my scope were 12 uSec apart when it was cooler in the room and now they are 14 uSec apart. The alignment appears quite stable over days, I do not have time graphing capabilities at this time.
After they line up the output appears stable also.

What Phenomenon causes the Sq Waves to line up and stop moving relative to one another?
Is it "An odd kind of Sympathy?"
I confess I know just about enough to get into trouble.

[bingo600]

What Phenomenon causes the Sq Waves to line up and stop moving relative to one another?

See attached pict
The XOR Gate compares the 10KHz from the Jupiter to the 10KHz out from the PIC , and controls the OCXO's EFC

/Bingo

[Wallace Gasiewicz]

Yea I know the XOR compares the two signals, but what makes it STOP.
Its not like the two signals are exactly on top of one another. If they were there would be no control voltage. No XOR output.

[thinkfat]

The short answer is: You've built a PLL, and it "locks" the VCXO to the GPS.

A slightly longer answer is that the XOR gate acts as a phase discriminator. It outputs a PWM that represents the phase difference between the two 10kHz signals. This PWM is then low-pass filtered (this is your loop filter) and applied to the EFC input of the VCXO. While the frequencies are not aligned, the EFC "wobbles", and so does the output frequency of the VCXO. When the frequencies are identical, the wobbling stops. The phases are now locked to each other, the phase angle is determined by the propagation delays of the XOR gate and the PLL filter.

EDIT: Strike that. The phase angle is determined by the tuning voltage required to bring the divided-down VCXO to the same frequency. Every change in phase (e.g. due to frequency difference) will cause a correction of the frequency, bringing it back into lock.

[Wallace Gasiewicz]

Thinkfat:

I get that. I know that it is like a PLL.
So any minor change in the phase difference, which here is really a very minor change in freq difference, causes a different control voltage and hence changes the freq of the XO.  I get that.
I just cannot wrap my head around why it stops at equal freq. Is it because it really never completely stops but keeps readjusting at a undiscernable (at least to me) rate?
This is why I used a temp controlled oscillator, I figured the wobble or phase shifting would be less over the short term verses a varicap VCXO.

[edpalmer42]

Thinkfat:

I get that. I know that it is like a PLL.
So any minor change in the phase difference, which here is really a very minor change in freq difference, causes a different control voltage and hence changes the freq of the XO.  I get that.
I just cannot wrap my head around why it stops at equal freq. Is it because it really never completely stops but keeps readjusting at a undiscernable (at least to me) rate?
This is why I used a temp controlled oscillator, I figured the wobble or phase shifting would be less over the short term verses a varicap VCXO.

You're correct.  The disciplining never stops.  It can't because the oscillator is always aging - drifting up and/or down and it must be continuously tweaked to keep it on frequency.  The loop will automagically do whatever is necessary to get the 10 KHz from the GPS to be identical to the 10 KHz derived from the oscillator - within the limitations imposed by the loop filter.  This helps smooth out any noise that might appear on the GPS output.

I'm curious about the 22K - 20uf series string at the bottom right corner of your schematic.  I'm not a PLL expert, but I would have expected the EFC line to come off the connection point between those two components rather than where it's shown.  What is their purpose?

By the way, component numbering would be a really nice addition to the schematic! 

[srb1954]

The circuitry around the LM1117 doesn't look right - there should be another resistor between OUT and ADJ to set the output voltage.

[Wallace Gasiewicz]

You are correct about the LM1117.  I did not use that particular part. I uses an old SONY 18 V power brick then used LM voltage controllers.
My OCXO needs 14.2 volts, which I was lucky to get considering the PS voltage. Little overhead. I also used a 5 Volt regulator and used TTL rather than CMOS, This is because I am using up my junk, hopefully.
The OCXO has an intrinsic 5 V surface mount regulator and uses the 14.2 volts for heating the XTAL using a Mosfet controlled by the voltage from the XOR (with a transistor somewhere and an Op amp). The Mosfet is essentially the heater.

I did not need 3.3 volts since my Navman with the chip can use 5 V.

[Wallace Gasiewicz]

Ed:

The 22K - 20uf series string along with the 5 uF cap at the bottom right corner convert the square wave out of the XOR gate to a DC to provide the voltage to control the OCXO heater. I did measure the voltage at the control pin of the OCXO and it looks like DC.
I used Tantalum caps.

[edpalmer42]

Ed:

The 22K - 20uf series string along with the 5 uF cap at the bottom right corner convert the square wave out of the XOR gate to a DC to provide the voltage to control the OCXO heater. I did measure the voltage at the control pin of the OCXO and it looks like DC.
I used Tantalum caps.

Yes, I know that.  I wasn't sure if it was intentional or if the loop filter was supposed to be a two stage RC filter.  The way you drew it, either is possible.  But when I look at James Miller's original schematic I see the same circuitry.  So I'm guessing it adds a pole or zero to the loop equation.  My brain starts to shut down when I think about such things so I'll leave it at that.

[Wallace Gasiewicz]

ED;

I cannot find the equation, but isn't there an equation for caps and resistance in a filter for 1/2 wave power supplies???
Also one involving a big inductor?
Could this be the sort of same thing?

Wally

[edpalmer42]

See!  I told you my brain was starting to shut down!  Instead of 'loop equation', I probably should have said 'loop response'.  Yes, there are equations for power supply filters and they are basically similar to what you're doing here.  If you really want to get into it, there are many books and articles on PLLs and their design and construction.

A couple that I know of are "Design of phase-locked loop circuits, with experiments" by Berlin and "Phaselock Techniques" by Gardner.  Gardner is pretty heavy but Berlin is intended for hobbyists.

Articles and web pages are almost too numerous to mention, but here are a few:
Brooks Shera's original article that started the DIY GPSDO era - https://www.qsl.net/n9zia/wireless/QST_GPS.pdf
James Miller's design that yours is based on - http://www.jrmiller.online/projects/ministd/frqstd0.htm
There are a bunch of Arduino updates for Shera's design.  Just search for <"brooks shera" gpsdo>

[Wallace Gasiewicz]

Ed:

I looked again at the schematic and I see what you are talking about. I noticed that myself when I built the thing. I donno why the EFC comes off the loop filter where it does rather than at the other point where the 22K resistor and 20 uF cap are joined. I just built it and didn't question the original plan.
Perhaps it is designed this way to keep the 20 uF cap from discharging too rapidly, otherwise another resistor would have to be employed between the EFC of the Oscillator and the 20 uF Cap to keep the cap slowly discharging???

Wally

[thinkfat]

Simulate it, play with the values. LTspice is free.