Electronics > Metrology

integrator for multi-slope/charge balance ADC


I am considering starting a project involving self-built integrating ADCs and have several questions. To provide context, I'll first explain my setups and goals.

Test Setup - Common Parts
Vref: Provided from ADR1399
Test Voltages: +7V, +5V, and multiple GNDs
Analog Switches: Utilized in the setup
Control: Managed by an STM32G474. I know this part and I can squeeze every nanoseconds from available periphery
Output Monitoring: Conducted using a DMM6500 high-speed digitizer
Test Setup - Adjustable Part
Testing different integrator structures
Testing various switch types and supply voltages (This part might be unnecessary; see the Goals section for more details)
  Learning Phase:
      Understanding how integrator parameters and ADC structure affect performance (noise, linearity, stability, etc.)
  Integrator Characterization:
Building an integrator model to linearize the physical integrator
Switch Characterization:
Developing a switch model to determine injection, leakage, etc.
Integrator Types: What types of combined integrators are used in Multi-slope and charge balance ADCs? Kleinstein and Jaromir discuss using a kind of HP34401 Multi-slope3 integrator. I am interested in exploring modern electronics like Multi-slope4 high-speed ADCs.
Integrator Output Swing: What are the reasonable ranges for integrator output swing (Vmax, Vmin)? Are these voltages dependent on the type of capacitor used?
Capacitor Types: What types of capacitors are typically used? I assume COG/NPO for modern designs, while older slow-speed designs used foil capacitors. Is this correct?
I appreciate your time and expertise in addressing these questions.
Best regards,

For the capacitor the choice is relatively easy. Good ceramic capacitors (e.g. TDK C0G) get lower dielectric absorbtion than most film types (maybe except PTFE) and they are small and affordable in the usual size needed (e.g. < 10 nF) for a multi-slope ADC.

For the integrator swing, more swing allows for a smaller capacitor and less voltage noise for the final / initial charge. If this is really relevant depends - with 1 PLC and slower it often is not that imporant.
Classical the swing was some +-10 V max, so that amplifiers with a +-15 V supply were sufficient. I would not consider the swing a very important parameter. For tests it is always helpful to have some headroom for variations. A small integrator capacitor also makes parasitic capacitance more relevant.

For the actual integrator the logic choice today is a combination of 2 OP-amps, to keep the input voltage really close to zero. This is one precision OP-amp and a fast amplifier for the output. I see no more need for the 3 amplifier version as in the 3458, as there are now fast enough precision amplifiers (e.g. OPA140).

A bigger question is what type of ADC to build with different option for the modulation and the choice of run-down phase or charge measurement on the fly for contineous integration. 
This choice also effects the choice for the reference switches: rel. slow modulation can use current type switching at the integrator side (e.g. like 34401), while fast modulation works better with voltage side switching (like 3446x).
For the modulation it is mainly the choice between
1) classic  2 case modulaton like in 34401,3458,K200x, LD120 or
2) variable PWM like FB (e.g. Solarton, KS3446x).

Usually there is no real need to model the switches in details. The point is keeping the number of switching events constant, so that charge injection only gives an offset that is easy to subtract.
The noise part is relatively easy, though there can be quite some noise sources and in an optimized design several source tend to be comparable.
The stability is mainly a thing of the parts used, especially the resistors.
The linearity part is difficult, as it is about small non ideal effects, beyond the normal linear modelling and is easy to miss parts.


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