LM399 based 10 V reference

[iMo]

Hello,

I did 5 T.C. measurements (each lasting one complete day)
every measurement with a different XTAL for the ATTINY85.
(2.45 MHz, 4.91 MHz, 10 MHz, 20 MHz and one with 8:1 prescaler)

The voltage for the overview is measured at 25 deg C.
The T.C. is the linear approximation (slope of the green curves) over ~15 to 40 deg C.
PWM is kept constant. at the precalculated value which should give exactly 10V at the output for the given LM399#3.

with best regards

Andreas

OK, you kept "PWM duty" constant (hard-coded in your fw) and you changed the "PWM frequency" (also hard-coded in your fw) by replacing the 4 Xtals, and the TC is the lin interpolation between the 4+1 Xtal measurements.

[Andreas]

Hello,

exactly. The "dots" are the measurement points. The rest is imagination 

with best regards

Andreas

[iMo]

Preparing to try NCC-1701 Vishay MPM-divider...
It's not exactly 10V output, but cheep and i hope is pretty good stable for my 6.5 DMMs.

FYI: Maxim does the similar:

1:1-1:30 30k end to end divider with 2ppm/degC resistance-ratio tempco (for <3.5 ratios):

https://www.maximintegrated.com/en/products/analog/data-converters/digital-potentiometers/MAX5491.html

PS:

1:1-1:10 10k divider, up to 1.5ppm/degC ratio tempco
https://www.maximintegrated.com/en/products/analog/data-converters/digital-potentiometers/MAX5492.html

1:1-1:100 100k divider, up to 1ppm/degC ratio tempco
https://www.maximintegrated.com/en/products/analog/data-converters/digital-potentiometers/MAX5490.html

From DS:

..and custom ratios are also available upon request..

And the Vishay https://www.vishay.com/docs/60001/mpm.pdf to compare https://www.maximintegrated.com/en/alternatives.cfm/part/SOT23/pk/437

[branadic]

Hi Andreas,

I didn't forget the T.C. measurement, but was of the bench for a while because of illness.

-branadic-

[Andreas]

Hello,

I made some LTSPICE-simulations for the ION board of Branadic.
Reason was to see if the integrator filter around the first OP-Amp can be reduced in size after we found out that C4 should be rather 10uF instead of 1uF.

Starting from 1uF, 1.5uF and 1uF for C1,C2,C3 and reducing to 100nF for all
I also tried to simulate the influence of the low frequency part from the dithering.
First I tried to put a sine of 1kHz and 40 mV Amplitude (10V/256) in series to the input (on top of the LM399 voltage).
But I soon decided to put the 40 mV sine in series to the ADG419 output.
To get all details I had to put the maximum simulation distance to 2ns. (So each calculation several hours).
Simulations were all done with a 10uF and 10nF output filter so that changes in the integrator can be seen more easily.

Here some results:
If all 3 capacitors are used there seems to be no difference if 1uF, 10uF or 100nF are populated.
Except for Startup time after power up which scales exactly to the 1uF or 100 nF value.
I will have to do further simulations with lower Sine frequency and reduced capacitors to see where the limits are.
Especially as the full period time is several seconds for the dithering.

Although there is no difference on the VOut2 node it makes a large difference on the VUC1 node wether C1 is connected to Gnd around (100uV high frequency spikes) or the UC1 node (8 mV high frequency spikes).
As I also can see high frequency spikes on my scope I take this serious.
So the suggestion of Kleinstein for C1 to GND should ease the filtering.

Interestingly I can omit C2 with only minor changes on the output signal or UC1.

But for now I only would put C1 against GND instead of UC1.

with best regards

Andreas

[Kleinstein]

The resistance of R1+R2+R3 = 300 K is rather high, even for the LTZ2057.  So if the filter is not that critical, I would prefer a reduced resistance instead of much smaller caps. R1 may have to stay at a relatively high value to keep the R_on effect and the current flowing back to C4 small. However I see no big problem reducing R2 and R3, maybe to something like 10-20 K. These 2 are just filtering a low amplitude signal.

AFAIK the lowest frequency from the modulation should not be so super low, more like the same as if one would use plain PWM for the same resolution. So with some 22 Bit resolution and 4 MHz clock the period should be near 1 Hz. At least this happens with 1st. order digital filtering.
Higher order digital filtering is supposed to reduce the amplitude quite a lot, so that not much analog filtering is needed anymore, even of there is a small very low frequency part.
Even if the code allows for 24 Bit or even 32 Bit resolution (to simply the code and use the CPU carry), there should be not lower frequency part if the last bits in the set value are 0.

[pigrew]

Thanks for the simulation results.


I just ordered my "Analog" board, along with STM32F334 and MSP430F5172 digital boards. They should arrive towards the end of next week. I'm leaning more towards the MSP430 timer_D, as it is generated internally with a ring oscillator, apparently with a length directly controllable by registers (so no wacky PLL glitches). Though it will drift with temperature, I hope it will be fairly stable.

I'm happy to share my layout files upon request (PM me). The boards were cheap enough (2-layer, 1mm thick) that it doesn't make sense to mail spares ($10 for everything, including shipping from HK).

[Andreas]

Hello,

did some further simulations (now with my "final" population).
The 1uF, 1.5uF + 1uF (Gnd) for the integrator part.
10uF (foil) to reduce the ripple + spikes.
And a further 4K7 + 1uF low pass.

Simulated several sine frequencies as "low frequency modulation"
At low frequencies (50 Hz and below to 0.1Hz) the filter could be better
But on the other side the 40mV amplitude is shurely more than that
what we will get as change of +/-4 counts in the existing 10kHz triangle signal of some 10 uVpp.

So some results and the overview table (which was wrong regarding the 10uF in the previous post).

with best regards

Andreas

[iMo]

Is that an ".io" or the ".ic" (the correct one) LTspice directive in your simulation??

[iMo]

I've been experimenting with the decreasing the opamp's output current and boosting the output current with 399 classic circuit. Is there any experience with that transistor at the output? More noise or drift?

[Kleinstein]

The OP in the filter does not see much DC load. So just adding the transistor would not work . With some extra DC load the extra transistor would not change much. If at all the extra transistor could allow to use a slightly smaller resistor for R4 - however it looks like the capacitor is more important than the resistor.

For the output stage the extra transistor could be useful to reduce heating of the OP under heavy load. It would not change much with noise and drift, as the transistor is in the loop.

[pigrew]

I also thought about doing that, but it seemed unnecessary. The BJT would add a bit of noise. Another technique would be a resistor between 15V and the op-amp output (to provide the current), 1mA and 7V 3V would make it a 7k 3k resistor.

ADDENDUM: It's also possible that the pull-up would reduce the op-amp's switching noise, since the switched caps would be injecting less current. (I also changed the 7V figure to 3V)

[iMo]

..For the output stage the extra transistor could be useful to reduce heating of the OP under heavy load. It would not change much with noise and drift, as the transistor is in the loop.

Yes, we talking here the output stage only (399 classic). I don't see any diff against the naked opamp's output in tempco drift. No idea about the added noise, imho it should be by orders lower than the 399. Except the way higher current capability the boosted opamp's output gets some emi/esd protection as well..

[Kleinstein]

There is no extra noise expected. However there is also essentially not added ESD / EMI protection as the he feedback path is still there, though one could have a small series resistor here for some protection (but than added noise from the resistor and possibly drift). 

[iMo]

The fb path is resistive - 399 cathode resistor and divider resistor.

[Andreas]

Is that an ".io" or the ".ic" (the correct one) LTspice directive in your simulation??

Attached the latest simulation file

[Andreas]

Hello,

I did a 2nd sample of branadics ION PCB.

This time I wanted to be more flexible with the processor so it is built on a Sub-Board connected to the programming connector.
The capacitors are according to the latest simulation except for C3 which is connected to UC1 instead of GND.
Since I ran out of LT1763-5 I simply used a LP2950 for the 5V regulator in TO-92 (SMD mounted)
The 4K7/1uF filter at the output is built with a 0805 1uF X7R capacitor. (so no foil at the moment).
The 10uF WIMA is mounted on the "2nd floor" above some other components.

On the sub-board I use a PIC12F1840 together with a 10 MHz XTAL to get ~10kHz PWM.
Power consumption is 3.7mA for the whole cirquit compared to 4.1 mA of the ATTINY85 with 2.45 MHz and sleep mode.
The sleep mode on the PIC cannot be used since it would also stop the PWM output.

With the new filter population the 10kHz PWM clock is no longer visible (below the noise floor)
when being measured with a LNA 10Hz - 100kHz according to AN83 (LT).

The diagram to be compared with (with the previous filter) is described here:
https://www.eevblog.com/forum/metrology/lm399-based-10-v-reference/msg2080246/#msg2080246

with best regards

Andreas

[matches]

Hi.

Earlier in this thread the use of the AD107 was recommended when building a self biased version.
HP did so for the 34401A, I think Keithley for the 2000, 2015, ...

LT suggests the LT1001.

Can someone help me understand why to prefer the AD107 over the LT1001?

Regards

[Andreas]

Hello,

some T.C. measurements over PWM-frequency with the 2nd sample on branadics PCB.
The PIC-based solution shows this time a much larger T.C. at 9.765 as sample #1. (0.56 ppm/K)
Whereas voltage over frequency increases again.

see post:
https://www.eevblog.com/forum/metrology/lm399-based-10-v-reference/msg2218482/#msg2218482

And T.C. over frequency shows a negative slope instead of a positive slope.
"Zero T.C." would be at negative frequencies.

we have:  - 18.8 ppb/kHz
and :        +0.104 mV/kHz

now the big question:
- is the stray from ADG419 from device to device for the T.C. so large
- or is the different processor (PIC) the guilty. (e.g. different rise time at input)

-> we need much more samples/measurements

with best regards

Andreas

[iMo]

The higher PWM freq the higher temperature of the ADG switch, more stray capacitance leakage, more losses in the 10uF capacitor (a nonlinearity?).

[Kleinstein]

I don't think the power used by the ADG419 is a significant factor.  Also the loss in the capacitors should be not such a big effect - to a large part dielectric absorption is still linear.

The effects I see that could contribute significant to the TC are the change in R_on of the DG419.  The R_on contributes a little to nonlinearity as current in both phases is different.  This effect should get larger if the 100 K resistor at the filter is reduced. However this effect should be largely independent of the frequency. So it's more like part of the TC extrapolated to zero PWM.

Another temperature dependent effect is from a change in the switching time of the AD633. Besides the internal switching time also the level for detecting the logic signal could change with temperature and this way, depending on the slew rate of the control signal effect the timing.  The ADG619 is relatively slow - a faster switching chip might be better.

I don't see a large effect related directly to the µC or the slightly larger stray capacity from the adapter board. I theory there could be an effect of the PWM signal coupling to the µCs clock circuit and this way leading to some phase shift there, that would effect the PWM accuracy. However this should be more like a transient effect and linear in the PWM frequency.

Capacitive coupling from the control signal to the filter input should be relative to the rather low switch resistance. It could still contribute somewhat, and since the switch resistance increased with time would also be temperature dependent. Assuming something like 1 pF, this could contribute something like 5 pC of charge and at a 40 Ohms switch resistance would be some 2 µV at 10 kHz PWM frequency. However a similar effect would happen for the other side and this would to a large part compensate. So only the R_on difference would be effective e.g. some 5 Ohms from 0 V to 10 V. So I don't see a significant contribution.

AFIAK the rise time of the AVR and PIC is not that different. In addition the rise time is way shorter than the DG419 switch speed.

So may guess would be more with the different ADG419 sample than the µC.

[Grandchuck]

Here is my fun box enclosed in Styrofoam and sealed with duct tape.  To get it to a useful state, I soldered the appropriate voltage selection pins together.  It is powered on 24/7 and has been for months.  It has settled into a useful state at 9.817495 volts and wanders no more than 2 ppm.  My home lab is rather constant for temp and humidity.

[pigrew]

Small updates on my PWM implementation:

I've received the boards I've ordered, and have built up a MSP430 MCU board, finding out I've made a few mistakes along the way (but nothing unfixable)....

The MCU can operate in two modes: free running at up to about 1 GHz, or XO-disciplined at up to about 400 MHz.

Running with a 8MHz XTAL, multiplied to 24 MHz, used to discipline a 384 MHz timer clock, outputting 10 kHz, uses about 2.7 mA @ 3.3V. stdev(period) ~ 18.3ns, p-p(period) ~ 120. Enabling "clock error accumulation" correction increases the jitter slightly, but probably should be left disabled in this application.

Free-running with a 256 MHz clock uses about 1.2 mA, though with a much higher temperature-coefficient. stdev(period) ~ 21ns, p-p(period) ~ 135.

These measurements were performed with a MSO-X 4154A oscilloscope, having it measure the period of a single output cycle.

I think my preference would be XO-disciplined because of its much lower TC. The higher current consumption can be mitigated by using a switching DC-DC converter (though not the one that I had originally chosen).

Next up is populating my analog board... I like the MSP430 enough that I won't bother with the STM32F334.

One interesting thing was that when setting the period, the lowest 3 bits are ignored in 8x clock mode, and the lowest 4 bits are ignored in 16x clock mode. The pulse width parameter is controllable with full 16-bit resolution.

(Some of the mistakes: The pins I used for TD0 have higher channel->channel skew than the other available pins. Also, TD0.0 can only output the full period, not PWM (unless you set the period to a power of 2 (2^12, 2^14, 2^16, etc). Next revision will use TD0.1 and TD0.2 as the outputs. The micro's FLL only multiplies, but doesn't divide, so it is not very adjustable if you use a high-frequency XTAL. Oh, and I mixed up the pins of the LDO regulator on the PCB.)

Once I get the whole thing running well, my plan is to integrate the boards back onto a single PCB.

[pigrew]

I've developed firmware for the MSP430 to run the PWM using sigma-delta modulation, plus built up enough of the analog PCB to be able to output a somewhat stable 10V. Yay.

Source code is posted athttps://github.com/pigrew/msp399pwm.

In terms of performance, it (or the Keithley 2000) is reasonably stable (staying within 30 uV of 10V over a few minutes) and quite adjustable (32-bit resolution). The PWM adjustment ISR takes about 3.5us, allowing operation at over 50 kHz without glitches (faster in the future with further optimization). The circuits draws about 20 mA at 18V and 18C, most of which is the LM399's heater current. The MCU board uses a DC-DC converter while all of the analog circuitry is driven at 15 V with a LDO. I have a simple RC filter at the output (10u/4.7k), but will populate the output amplifier soon.

A plot of a quick frequency sweep is attached, showing a gain of 0.069 mV/kHz.

[iMo]

While curious about how your 32bit DAC works and looking at the code and SD DAC whitepaper you refer to, let me kindly ask you - does it mean you modulate (within a periodic ISR) a 16bit PWM duty with the sigma delta modulator's 1bit output?