Electronics > Metrology

Low noise chopper and DIY nV meter

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I took Mark's suggestion on the RC filter in front of the ADC, and it worked really well. I changed the values to 4R7/ 2.7nF CM + 10nF DM. The CM capacitance was chosen to limit the potential slew rate of signals at the terminals by keeping the RC time constant over 12.5 ns as mentioned in the datasheet. For the low gain setting, the NSD dropped from 3-4 to 1.51 nV/rtHz at 500kSPS and 2.5-3 to 1.50 nV/rtHz at 2 MSPS. It didn't really make sense to me that the NSD was as high as it was at 2 MSPS. Referred to the input at low gain, I was seeing about 0.3 nV/rtHz from the ADC + driver and reading about 1.7 nV/rtHz at the analog out but then seeing close to 3 nV/rtHz in the ADC readings. With the new RC filter here are the NSDs I got, referred to the ADC inputs:

fs = 500k; 55.40 nV/rtHz
fs = 1M; 43.66 nV/rtHz
fs = 2M; 35.94 nV/rtHz

If you plot the PSD against 2/fs for these values, by my math, the slope should be the square of the RMS noise of the ADC and the intercept should be the driver noise. The linearity with these three points is good (r^2 = 0.9998). If you extract the values from this, you get a driver NSD of 26.65 nV/rtHz and an ADC noise of 24.3 uVRMS. The driver noise is very close to expectations (LTSpice said 28 nV/rtHz), but the RMS noise of the ADC is about double what the datasheet lists as the typical value (12.5 uVRMS). The RMS value isn't just ADC noise though - it's also broadband differential noise at the inputs that can alias back into the passband as well as broadband common mode noise doing the same but reduced by the CMRR. The measured broadband NSD at the ADC inputs is actually matches the predicted value pretty closely without the 10nF DM cap, though that could be coincidental. I will probably try a simple 4R7/10nF (CM) for the version with the ADR1399 to see if that works any better. Either way, it seems that the values you would suspect should be fine (like 68R/2.7nF for 500kSPS and 33R/1nF for 2MSPS) leave quite a bit on the table. The predictions for system noise with ADI's online calculator do not match my results for those combinations with this topology, and the errors are numbers that are not convenient to express as percentages.

This is more of a general interest thing than of direct relevance to the NVM because 24 nV/rtHz at the ADC inputs is more than good enough to not impact the results with either gain setting. The mystery of the interaction between ADC noise and the input signal is still unsolved - note that here, the NSD at 500kSPS referred to the chopper input is 1.5 nV/rtHz though the ADC noise was greater than it was previously at 2 MSPS. My attempts to probe the input with a fast DC amplifier didn't find anything suspicious, but I was running into the noise floor of the instrument I used to get the spectra.

I have gotten preliminary linearity results with both boards. The ADR1399 board looks good, the LTC6655 board not so much. I need to get my low-level source up and running to really figure out what the issue is with the ladder. I suspect it is related to intermodulation/aliasing as the points that were out of trend were also drifting a lot. I ran some long captures with both boards with the modulator frequency at 1800 Hz and averaging 30 cycles to get an output data rate of 60 Hz. A peak around 10 mHz was noticeable with the LTC6655 board, and I attributed this to the poor antialiasing performance of simple block averaging filters. I changed the code to allow higher order sinc filters (up to sinc3) because all the cascaded integrator-comb calculations can be done in fixed point. I ran a couple tests where I changed the ODR to 28.12 Hz (32 averages) to ensure there would be an alias of the mains frequency peak in the sinc1. The peak was not visible in either the sinc2 or sinc3 runs, but the sinc3 run had somewhat higher white noise density (about 10% higher), so I used the sinc2 filter for block averaging in another long capture with the LTC6655 board.

I got a bit more than 4 days of data before the BMS cut off the power, and the noise performance with the sinc2 filter was very good. The spectrum remained flat a bit below 1 mHz. There was a fair amount of drift (about 7 nV). I attribute this to the increased efficiency of the buck converters on the SMPS board at lower voltage. I did some regression analysis with time, input temperature, and the first derivative of input temperature as independent variables. I selected portions of the dataset where the correlation coefficient between temperature and time were low r^2<0.1 and got positive temperature coefficients of 0.25-0.6 nV/K. Obviously, this is not the best way of determining the tempco, but it is clearly quite small as there was quite a bit of temperature variability during the capture. The sensitivity to temperature change is between -1.5 and -2 nV*h/K. I think that both the drift and sensitivity to temperature change could be improved in a different case with the board supported differently. With the space taken up by 4x21700 batteries, there is very little extra room in the Hammond extruded Al case this was designed for.

The ADR1399 board does not seem to show the same downward drift as the battery discharges. I think this is probably because the increased efficiency effect is cancelled out by the increased current demand of the reference heater as the voltage between the heater pins drops. HTR- is supplied by the Cuk converter, so the associated components will dissipate more heat as the current increases. I included time domain plots and ffts for all these long captures. I RMS averaged the FFT data into logarithmically distributed bins to make it possible to see what is going on on the right-hand side of the plot.

I was underwhelmed with the performance of the Pomona low-thermal binding posts for this application because it really became critical to prevent air movement around them to reduce noise from transient thermal EMFs. I changed to a LEMO 0S size receptacle using the normal contact material, and that really helped. For some reason, it was also very helpful to put a CM choke at the input (just by wrapping the wires around an amorphous core to get about 1.5 mH). I don't have a shorting plug, but when I shorted the inputs at the end of a second receptacle and a length of cable, the offset relative to the internal short was about 200 nV, and that value seems to be reasonably stable.

I have identified a couple ways in which the protection on the power rails is inadequate, mostly by killing a couple AD4030s in fault states. In future revisions, I am going to add TLV431 + PNP clamps to most of the positive rails and increase bulk capacitance to prevent this sort of thing. The AD4030 (and probably the AD4630 as well) seems to be very susceptible to death. When the 1V8 rail had a transient overvoltage event from me accidentally shorting the +9V and +2V rails while I was probing the PSU (the latter supplies +1V8), only the ADC, two TMP117s, and the LDO died. All the glue logic and MCU survived unscathed. Also, the THP210 can actually pull the 5V4 rail above the absolute maximum for the AD4030 (I saw it hit about 6.5V) through the clamping diodes that limit the input signal swing. If the 1V8 rail dies, the ADC input switches do not turn off inputs above 5V, and that leads to another failure mode for the ADC. This is obviously problematic because any short to ground on the 1V8 rail will definitely lead to the death of the ADC.

Maybe a variation of the overvoltage protection circuit figure 91, page 27 is also interesting in your rail protection case?
https://www.analog.com/media/en/technical-documentation/data-sheets/ada4177-1_4177-2_4177-4.pdf / https://opendcm.blogspot.com/2020/04/revised-analog-front-end-over-voltage.html
Cant remember if i already proposed it. I need to do some simulations on it myself, as it seemingly avoids the necessary transient reducing bulk capacitance.
Losing those high cost ADCs surely brings a tear to the eye.  :(

When you lose one by shorting two pins while probing, it also brings some curses to the lips. I prefer to reflow BGA packages in the oven, so I had to take off a few of the though-hole compounds as well. No fun.

It seems like opencdm version of that protection circuit has an issue because it allows the input of the op amp to go two diode drops above the positive rail, but the idea in the ADA4177 datasheet is pretty cool. In this case, I think it will be easier to use clamps on the supplies as I mentioned because you only need one per rail (for the +5V4 rail) and you get protection against unforeseen causes of overvolting a rail, such as bridging two pins with a probe tip.

I rewrote the firmware for the NVM in hopes of making it more understandable in the future as well as making general improvements and fixing some issues. One of the key issues was horrifically bad DNL (in the neighborhood of 1%), which had the feel of a firmware issue. The new firmware did indeed solve the problem, though there are still some bugs to work out that crop up with certain combinations of parameters. To test the linearity with the new firmware, I ran five 11-point sweeps from 0 to 1 mV using a source based on a DAC11001B and a resistor divider. The source INL should be in the <1 ppm range. The maximum linearity deviation I saw for these sweeps was about -1.5 ppm, which is a deviation of -1.5 nV from the straight line connecting the endpoints. I have attached a scatter plot for these preliminary results.

One of the issues I have run into with measuring external voltages is susceptibility to (probably) EMI, where simply attaching a cable, even if the inputs are shorted internally, increases noise and can affect the offset. I suspect capacitive coupling or leakage between chassis and circuit grounds, but I will need to investigate more. Once I find a way of getting better control over this, I will run some more experiments to get better linearity data.


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